Intel has unveiled some interesting advances in semiconductor manufacturing at the International Solid-State Circuits Conference (ISSCC), showcasing the capabilities of its highly anticipated Intel 18A process technology. The presentation highlighted significant improvements in SRAM bit cell density. The PowerVia system, coupled with RibbonFET (GAA) transistors, is at the heart of Intel's node. The company demonstrated solid progress with their high-performance SRAM cells, achieving a reduction from 0.03 µm² in Intel 3 to 0.023 µm² in Intel 18A. High-density cells showed similar improvement, shrinking to 0.021 µm². These advancements represent scaling factors of 0.77 and 0.88 respectively, which are significant achievements in SRAM technology, once thought to be done with scaling benefits.

Implementing PowerVia technology is an Intel-first approach to addressing voltage drops and interference in processor logic areas. Using an "around the array" scheme, Intel strategically applies PowerVias to I/O, control, and decoder elements while optimizing bit cell design without a frontal power supply. The macro bit density of 38.1 MBit/mm² achieved by Intel 18A puts the company in a strong competitive position. While TSMC reported matching figures with their N2 process, Intel's comprehensive approach with 18A, combining PowerVia and GAA transistors, could challenge Smausng and TSMC, with long-term aspirations to compete for premium clients currently served by TSMC, including giants like NVIDIA, Apple, and AMD.

Intel has officially announced that its "Clearwater Forest" Xeon processor family will be arriving somewhere in the first half of 2026. During a recent earnings call, interim co-CEO—Michelle Johnston Holthaus—discussed Team Blue's product roadmap for 2025 and beyond: "this year is all about improving Intel Xeon's competitive position as we fight harder to close the gap to the competition. The ramp of Granite Rapids has been a good first step. We are also making good progress on Clearwater Forest, our first Intel 18A server product that we plan to launch in the first half of next year." Press outlets have (correctly) pointed out that Intel's "Clearwater Forest" Xeon processors were originally slated for release in 2025, so the company's executive branch has seemingly admitted—in a low-key manner—that their next-gen series is delayed. Industry whispers from last autumn posit that Team Blue foundries were struggling with their proprietary 18A (1.8 nm) node process—at the time, watchdogs predicted a postponement of "Clearwater Forest" server processors.

The original timetable had "Clearwater Forest" server CPUs arriving not long after the launch of Intel's latest line of "Sierra Forest" products—288-core models from the Xeon 6-series. The delay into 2026 could be beneficial—The Register proposes that "Xeons bristling with E-cores" have not found a large enough audience. Holthaus disclosed a similar sentiment (in the Q4 earnings call): "what we've seen is that's more of a niche market, and we haven't seen volume materialize there as fast as we expected." Despite rumors swirling around complications affecting chip manufacturing volumes, Intel's temporary co-leaders believe that things are going well. David Zinsner—Team Blue's CFO—stated: "18A has been an area of good progress...Like any new process, there have been ups and downs along the way, but overall, we are confident that we are delivering a competitive process." His colleague added: "as the first volume customer of Intel 18A, I see the progress that Intel Foundry is making on performance and yield, and I look forward to being in production in the second half, as we demonstrate the benefits of our world-class design."

Intel shared some news and updates about its upcoming CPU architectures during the Q4 earnings call. Intel confirmed that "Panther Lake", its next major CPU, is set to be released in late 2025. "Panther Lake" will use Intel's latest 18A manufacturing process and might be part of the Core Ultra 300 series. "Panther Lake" is rumored to combine next-generation "Cougar Cove" P-cores with existing "Skymont" E-cores both in the Compute complex, and in the SoC tile as low-power island E-cores. However, Intel hasn't confirmed if it will be available for desktop systems.

The following CPU architecture, "Nova Lake", is set to debut in 2026. Unlike "Panther Lake", we know "Nova Lake" will work on desktop computers. This suggests desktop users might need to wait until 2026 for an upgrade unless Intel surprises us with a desktop version of "Panther Lake" or an alternative option.

Intel Corporation today reported fourth-quarter and full-year 2024 financial results. "The fourth quarter was a positive step forward as we delivered revenue, gross margin and EPS above our guidance," said Michelle Johnston Holthaus, interim co-CEO of Intel and CEO of Intel Products. "Our renewed focus on strengthening and simplifying our product portfolio, combined with continued progress on our process roadmap, is positioning us to better serve the needs of our customers. Dave and I are taking actions to enhance our competitive position and create shareholder value."

"The cost reduction plan we announced last year to improve the trajectory of the company is having an impact," said David Zinsner, interim co-CEO and chief financial officer of Intel. "We are fostering a culture of efficiency across the business while driving toward greater returns on our invested capital and improved profitability. Our Q1 outlook reflects seasonal weakness magnified by macro uncertainties, further inventory digestion and competitive dynamics. We will remain highly focused on execution to build on our progress and unlock value."

Intel Foundry has announced the onboarding of new defense industrial base (DIB) customers, Trusted Semiconductor Solutions and Reliable MicroSystems, as part of the third phase of the Rapid Assured Microelectronics Prototypes - Commercial (RAMP-C) efforts under the Trusted & Assured Microelectronics (T&AM) Program in the Office of the Under Secretary of Defense for Research and Engineering (OUSD (R&E)). The RAMP-C project, awarded through the Strategic & Spectrum Missions Advanced Resilient Trusted Systems (S²MARTS) Other Transaction Authority (OTA), allows DIB customers to take advantage of Intel Foundry's leading-edge Intel 18A process technology and advanced packaging for prototypes and high-volume manufacturing of commercial and DIB products for the U.S. Department of Defense (DoD).

"We are very excited to welcome Trusted Semiconductor Solutions and Reliable MicroSystems to the RAMP-C project we are engaged in with the DoD. The collaboration will drive cutting-edge, secure semiconductor solutions essential for our nation's security, economic growth and technological leadership. We are proud of the pivotal role Intel Foundry plays in supporting U.S. national defense and look forward to working closely with our newest DIB customers to enable their innovations with our leading-edge Intel 18A technology," said Kapil Wadhera, vice president of Intel Foundry and general manager of Aerospace, Defense and Government Business Group.

Intel at its 2025 International CES keynote unveiled its next-generation mobile processor, codenamed "Panther Lake." Intel confirmed that the chip will be built on its homebrew Intel 18A foundry node. The current "Lunar Lake" and "Arrow Lake" processors see the company leverage TSMC N3 node for the Compute tiles. "Panther Lake" would see the x86-64 core IP return to an Intel node. "Panther Lake" is rumored to combine next-generation "Cougar Cove" P-cores with existing "Skymont" E-cores both in the Compute complex, and in the SoC tile as low-power island E-cores. "Panther Lake" is expected to debut in the second half of 2025.

During Barclays 22nd Annual Global Technology Conference, Intel was a guest and two of the interim company co-CEOs Michelle Johnston Holthaus and David Zinsner gave a little update on the state of affairs at Intel. One of the most interesting aspects of the talk was Intel's upcoming "Panther Lake" processor—a direct successor to Intel Core Ultra 200S "Arrow Lake-H" mobile processors. The company confirmed that Panther Lake would utilize an Intel 18A node and that a few select customers have powered on Panther Lake on the E0 engineering sample chip. "Now we are using Intel Foundry for Panther Lake, which is our 2025 product, which will land on 18A. And this is the first time that we're customer zero in a long time on an Intel process," said interim co-CEO Michelle Johnston Holthaus, adding, "But just to give some assurances, on Panther Lake, we have our ES0 samples out with customers. We have eight customers that have powered on, which gives you just kind of an idea that the health of the silicon is good and the health of the Foundry is good."

While we don't know what ES0 means for Intel internally, we can assume that it is one of the first engineering samples on the 18A. The "ES" moniker usually refers to engineering samples, and zero after it could be the first design iteration. For reference, Intel's "Panther Lake-H" will reportedly have up to 18 cores: 6 P-cores, 8 E-cores, and 4 LP cores. The design brings back low-power island E-cores in the SoC tile. The P-cores use "Cougar Cove," which should have a higher IPC than "Lion Cove," while keeping the existing "Skymont" E-cores. The SoC tile may move from Arrow Lake's 6 nm to a newer process to fit the LP cores and an updated NPU. The iGPU is said to use the Xe3 "Celestial" architecture. With Arrow Lake-H launching in early 2025, Panther Lake-H likely won't arrive until 2026.

A few days ago, we published a report about Intel's 18A yields being at an abysmal 10%. This sparked quite a lot of discussion among the tech community, as well as responses from industry analysts and Intel's now ex-CEO Pat Gelsinger. Today, we are diving into known information about Intel's 18A node and checking out what the yields of possible products could be, using tools such as Die Yield Calculator from SemiAnalysis. First, we know that the defect rate of the 18A node is 0.4 defects per cm². This information is from August, and up-to-date defect rates could be much lower, especially since semiconductor nodes tend to evolve even when they are production-ready. To measure yields, manufacturers use various yield models based on the information they have, like the aforementioned 0.4 defect density. Expressed in defects per square centimeter (def/cm²), it measures manufacturing process quality by quantifying the average number of defects present in each unit area of a semiconductor wafer.

Measuring yields is a complex task. Manufacturers design some smaller chips for mobile and some bigger chips for HPC tasks. Thus, these two would have different yields, as bigger chips require more silicon area and are more prone to defects. Smaller mobile chips occupy less silicon area, and defects occurring on the wafer often yield more usable chips than wasted silicon. Stating that a node only yields x% of usable chips is only one side of the story, as the size of the test production chip is not known. For example, NVIDIA's H100 die is measuring at 814 mm²—a size that is pushing modern manufacturing to its limits. The size of a modern photomask, the actual pattern mask used in printing the design of a chip to silicon wafer, is only 858 mm² (26x33 mm). Thus, that is the limit before exceeding the mask and needing a redesign. At that size, nodes are yielding much less usable chips than something like a 100 mm² mobile chip, where defects don't wreak havoc on the yield curve.

In case you're wondering why Intel went with TSMC 3 nm to build the Compute tile of its "Arrow Lake" processor, and the SoC tile of "Lunar Lake," instead of Intel 3, or even Intel 20A, perhaps there's more to the recent story about Broadcom voicing its disappointment in the Intel 18A foundry node. The September 2024 report didn't specify a number to what yields on the Intel 18A node looked like to spook Broadcom, but we now have some idea as to just how bad things are. Korean publication Chosun, which tracks developments in the electronics and ICT industries, reports that yields on the Intel 18A foundry node stand at an abysmal 10%, making it unfit for mass-production. Broadcom validated Intel 18A as it was prospecting a cutting-edge node for its high-bandwidth network processors.

The report also hints that Intel's in-house foundry nodes going off the rails could be an important event leading up to the company's Board letting go of former CEO Pat Gelsinger, as huge 2nd order effects will be felt across the company's entire product stack in development. For example, company roadmaps put the company's next-generation "Clearwater Forest" server processor, slated for 2025, as being designed for the Intel 18A node. Unless Intel Foundry can pull a miracle, an effort must be underway to redesign the chip for whichever TSMC node is considered cutting-edge in 2025.

Intel Corporation and the Biden-Harris Administration announced today that the U.S. Department of Commerce and Intel have reached agreement on terms to award the company up to $7.86 billion in direct funding for its commercial semiconductor manufacturing projects under the U.S. CHIPS and Science Act. The award will support Intel's previously announced plans to advance critical semiconductor manufacturing and advanced packaging projects at its sites in Arizona, New Mexico, Ohio and Oregon. Intel also plans to claim the U.S. Treasury Department's Investment Tax Credit, which is expected to be up to 25% of qualified investments of more than $100 billion.

"With Intel 3 already in high-volume production and Intel 18A set to follow next year, leading-edge semiconductors are once again being made on American soil," said Pat Gelsinger, CEO of Intel. "Strong bipartisan support for restoring American technology and manufacturing leadership is driving historic investments that are critical to the country's long-term economic growth and national security. Intel is deeply committed to advancing these shared priorities as we further expand our U.S. operations over the next several years."

Yesterday, Intel launched its Xeon 6 family of server processors based on P-cores manufactured on Intel 3 node. While the early reviews seem promising, Intel is preparing a more advanced generation of processors that will make or break its product and foundry leadership. Codenamed "Clearwater Forest," these CPUs are expected to be the first high-volume production chips based on the Intel 18A node. We have pictures of the five-tile Clearwater Forest processor thanks to Tom's Hardware. During the Enterprise Tech Tour event in Portland, Oregon, Tom's Hardware managed to take a picture of the complex Clearwater Forest design. With compute logic built on 18A, this CPU uses Intel's 3-T process technology, which serves as the foundation for the base die, marking its debut in this role. Compute dies are stacked on this base die, making the CPU building more complex but more flexible.

The Foveros Direct 3D and EMIB technologies enable large-scale integration on a package, achieving capabilities that previous monolithic single-chip designs could not deliver. Other technologies like RibbonFET and PowerVia will also be present for Clearwater Forest. If everything continues to advance according to plan, we expect to see this next-generation CPU sometime next year. However, it is crucial to note that if this CPU shows that the high-volume production of Intel 18A is viable, many Intel Foundry customers would be reassured that Intel can compete with TSMC and Samsung in producing high-performance silicon on advanced nodes at scale.

All eyes have been on Intel since we announced Q2 earnings. There has been no shortage of rumors and speculation about the company, including last week's Board of Directors meeting, so I'm writing today to provide some updates and outline what comes next. Let me start by saying we had a highly productive and supportive Board meeting. We have a strong Board comprised of independent directors whose job it is to challenge and push us to perform at our best. And we had deep discussions about our strategy, our portfolio and the immediate progress we are making against the plan we announced on August 1.

The Board and I agreed that we have a lot of work ahead to drive greater efficiency, improve our profitability and enhance our market competitiveness—and there are three key takeaways from last week's meeting that I want to focus on:

• We must build on our momentum in Foundry as we near the launch of Intel 18A and drive greater capital efficiency across this part of our business.
• We must continue acting with urgency to create a more competitive cost structure and deliver the $10B in savings target we announced last month.
• We must refocus on our strong x86 franchise as we drive our AI strategy while streamlining our product portfolio in service to Intel customers and partners.

We have several pieces of news to share that support these priorities.

Intel Corp. and Amazon Web Services. Inc., an Amazon.com company, today announced a co-investment in custom chip designs under a multi-year, multi-billion-dollar framework covering product and wafers from Intel. This is a significant expansion of the two companies' longstanding strategic collaboration to help customers power virtually any workload and accelerate the performance of artificial intelligence (AI) applications.

As part of the expanded collaboration, Intel will produce an AI fabric chip for AWS on Intel 18A, the company's most advanced process node. Intel will also produce a custom Xeon 6 chip on Intel 3, building on the existing partnership under which Intel produces Xeon Scalable processors for AWS.

According to a recent Reuters report, Intel's 18A node doesn't seem to be production-ready. As the sources indicate, Broadcom has been reportedly testing Intel's 18A node on its internal company designs, which include an extensive range of products from AI accelerators to networking switches. However, as Broadcom received the initial production run from Intel, the 18A node seems to be in a worse state than initially expected. After testing the wafers and powering them on, Broadcom reportedly concluded that the 18A process is not yet ready for high-volume production. With Broadcom's comments reflecting high-volume production, it signals that the 18A node is not producing a decent yield that would satisfy external customers.

While this is not a good sign of Intel's Fundry contract business development, it shows that the node is presumably in a good state in terms of power/performance. Intel's CEO Pat Gelsinger confirmed that 18A is now at 0.4 d0 defect density, and it is now a "healthy process." However, alternatives exist at TSMC, which proves to be a very challenging competitor to take on, as its N7 and N5 nodes had a defect density of 0.33 during development and 0.1 defect density during high-volume production. This leads to better yields and lower costs for the contracting party, resulting in higher profits. Ultimately, it is up to Intel to improve its production process further to satisfy customers. Gelsinger wants to see Intel Foundry as "manufacturing ready" by the end of the year, and we can see the first designs in 2025 reach volume production. There are still a few more months to improve the node, and we expect to see changes implemented by the end of the year.

Intel has begun sampling the test tools for their "Oak Stream" platform which will house the "Diamond Rapids" generation of processors sometime in late 2025 or early 2026. Previously rumored to continue using the "Birch Stream" platform LGA 7529 socket that will soon be shipping with the 288-core flavor of the "Sierra Forest" efficiency core Xeons as well as 120-core "Granite Rapids" performance core Xeons, "Diamond Rapids" appears to instead be moving up to a substantially larger LGA 9324 socket. This is Intel's next-next generation of Xeon from what is shipping today, following up on the next-gen Intel 18A based "Clearwater Forest" which was only just reported to be powering on earlier this month. Other than the codename there is almost nothing currently known about "Diamond Rapids" but the rumor mill is already fired up and mentioning things such as increased core counts, 16 DRAM channels (similar to what AMD is expected to introduce with EPYC "Venice") and PCI-E 6.0 support.

The LGA 9324 test interposer for use with Intel's Gen 5 VR Test Tool that appeared on their Design-in Tools storefront before the page went to a 404 error carried a price tag of $900 USD and stipulated that this was a pre-order with an expected shipment date in Q4 2024.

Intel announced that it has postponed the 2024 edition of its Innovation event to 2025. Among other things, the first-party event showcases innovations from the company's various business units made in the preceding year, includes a few key product launches, and teasers for what's next. The Innovation 2024 was poised to be particularly important for the company, as it was expected to launch its next generation Core Ultra "Arrow Lake" processors not just for mobiles, but even the desktop platform. Other key product showcase items include Xeon 6 server processors, and Gaudi 3 AI accelerator, besides updates from the company's foundry business, particularly the Intel 20A and Intel 18A nodes.

Intel's postponement of Innovation 2024 can be seen as a move to demonstrate sincerity that the company working to meet its goal of cutting cost of revenue by $10 billion through FY 2024, something that will bear results by mid-2025. It would have probably felt inappropriate for the company to host a lavish product showcase event in light of this. That said, there's no word on how this affects launch of products such as Core Ultra "Arrow Lake," it's possible that the company may launch them in a low-key dedicated media presentation.

Intel today announced that its lead products on Intel 18A, Panther Lake (AI PC client processor) and Clearwater Forest (server processor), are out of the fab and have powered-on and booted operating systems. These milestones were achieved less than two quarters after tape-out, with both products on track to start production in 2025. The company also announced that the first external customer is expected to tape out on Intel 18A in the first half of next year.

"We are pioneering multiple systems foundry technologies for the AI era and delivering a full stack of innovation that's essential to the next generation of products for Intel and our foundry customers. We are encouraged by our progress and are working closely with customers to bring Intel 18A to market in 2025." -Kevin O'Buckley, Intel senior vice president and general manager of Foundry Services

Intel Corporation today reported second-quarter 2024 financial results. "Our Q2 financial performance was disappointing, even as we hit key product and process technology milestones. Second-half trends are more challenging than we previously expected, and we are leveraging our new operating model to take decisive actions that will improve operating and capital efficiencies while accelerating our IDM 2.0 transformation," said Pat Gelsinger, Intel CEO. "These actions, combined with the launch of Intel 18A next year to regain process technology leadership, will strengthen our position in the market, improve our profitability and create shareholder value."

"Second-quarter results were impacted by gross margin headwinds from the accelerated ramp of our AI PC product, higher than typical charges related to non-core businesses and the impact from unused capacity," said David Zinsner, Intel CFO. "By implementing our spending reductions, we are taking proactive steps to improve our profits and strengthen our balance sheet. We expect these actions to meaningfully improve liquidity and reduce our debt balance while enabling us to make the right investments to drive long-term value for shareholders."

Today marks a new milestone in the growth of Intel Foundry's design ecosystem as key partners Ansys, Cadence, Siemens, and Synopsys have announced the availability of reference flows for Intel's embedded multi-die interconnect bridge (EMIB) advanced packaging technology. This comes on the heels of recent announcements where those same partners declared readiness for Intel 18A designs. "Today's news shows how Intel Foundry continues to combine the best of Intel with the best of our ecosystem to help our customers realize their AI systems ambitions," said Suk Lee, vice president for Ecosystem Development, Intel Foundry.

The success of Intel Foundry is rooted in collaboration with a vibrant design ecosystem. This ensures customers can access our leading process and packaging technologies. Now, in collaboration with our ecosystem partners, we are making it as easy and as fast as possible for companies to optimize, fabricate and assemble their system-on-chip designs through our foundries, while enabling their designers with validated EDA tools, design flows and IP portfolios for silicon-through-package design. This systems foundry approach allows our customers to innovate at every layer of the stack so they can meet the complex computing demands of the AI era, where chip architectures increasingly rely on multiple CPUs, GPUs and NPUs in a package to achieve performance requirements.

Intel Core Ultra "Lunar Lake-MX" will be the company's bulwark against Apple's M-series Pro and Max chips, designed to power the next crop of performance ultraportables. The MX codename extension denotes MoP (memory-on-package), which sees stacked LPDDR5X memory chips share the package's fiberglass substrate with the chip, to conserve PCB footprint, and give Intel greater control over the right kind of memory speed, timings, and power-management features suited to its microarchitecture. This is essentially what Apple does with its M-series SoCs powering its MacBooks and iPad Pros. Igor's Lab scored the motherlode on the way Intel has restructured the various components across its chiplets, and the various I/O wired to the package.

When compared to "Meteor Lake," the "Lunar Lake" microarchitecture sees a small amount of "re-aggregation" of the various logic-heavy components of the processor. On "Meteor Lake," the CPU cores and the iGPU sat on separate tiles—Compute tile and Graphics tile, respectively, with a large SoC tile sitting between them, and a smaller I/O tile that serves as an extension of the SoC tile. All four tiles sat on top of a Foveros base tile, which is essentially an interposer—a silicon die that facilitates high-density microscopic wiring between the various tiles that are placed on top of it. With "Lunar Lake," there are only two tiles—the Compute tile, and the SoC tile.

Intel and Arm have signed a memorandum of understanding that finalizes the Emerging Business Initiative, their collaboration to support the startup community. The initiative builds on the April 2023 multi-generation agreement to enable chip designers to build low-power compute system-on-chips (SoCs) on the Intel 18A process. Together, the companies will provide essential intellectual property (IP) and manufacturing support, while also making financial assistance available, to foster innovation and growth for startups developing a range of devices and servers built on Arm-based SoCs and manufactured by Intel Foundry. The Emerging Business Initiative was announced last month at Intel Foundry Direct Connect in San Jose, California.

"Intel Foundry and Arm share the belief that for technology to benefit everyone, the building blocks of innovation must be available to anyone. Startups play a crucial role in bringing the great promise of transformations like AI to reality. The Emerging Business Initiative provides a path for new companies to leverage leading-edge Arm-based SoCs and Intel Foundry's global manufacturing capabilities to make their ideas real," said Stuart Pann, Intel senior vice president and general manager of Foundry Services.

Artificial intelligence isn't just driving headlines and stock valuations. It's also "pushing the boundaries of silicon technology, packaging technology, the construction of silicon, and the construction of racks and data centers," says Intel's Bob Brennan. "There is an insatiable demand," Brennan adds. Which is great timing since his job is to help satisfy that demand.

Brennan leads customer solutions engineering for Intel Foundry, which aims to make it as easy and fast as possible for the world's fabless chipmakers to fabricate and assemble their chips through Intel factories. "We are engaged from architecture to high-volume manufacturing—soup to nuts—and we present the customer with a complete solution," Brennan asserts.

Cadence's digital and custom/analog flows are certified on the Intel 18A process technology. Cadence design IP supports this node from Intel Foundry, and the corresponding process design kits (PDKs) are delivered to accelerate the development of a wide variety of low-power consumer, high-performance computing (HPC), AI and mobile computing designs. Customers can now begin using the production-ready Cadence design flows and design IP to achieve design goals and speed up time to market.

"Intel Foundry is very excited to expand our partnership with Cadence to enable key markets for the leading-edge Intel 18A process technology," said Rahul Goyal, Vice President and General Manager, Product and Design Ecosystem, Intel Foundry. "We will leverage Cadence's world-class portfolio of IP, AI design technologies, and advanced packaging solutions to enable high-volume, high-performance, and power-efficient SoCs in Intel Foundry's most advanced process technology. Cadence is an indispensable partner supporting our IDM2.0 strategy and the Intel Foundry ecosystem."

Intel Corp. today launched Intel Foundry as a more sustainable systems foundry business designed for the AI era and announced an expanded process roadmap designed to establish leadership into the latter part of this decade. The company also highlighted customer momentum and support from ecosystem partners - including Synopsys, Cadence, Siemens and Ansys - who outlined their readiness to accelerate Intel Foundry customers' chip designs with tools, design flows and IP portfolios validated for Intel's advanced packaging and Intel 18A process technologies.

The announcements were made at Intel's first foundry event, Intel Foundry Direct Connect, where the company gathered customers, ecosystem companies and leaders from across the industry. Among the participants and speakers were U.S. Secretary of Commerce Gina Raimondo, Arm CEO Rene Haas, Microsoft CEO Satya Nadella, OpenAI CEO Sam Altman and others.

Pat Gelsinger—CEO of Intel Corporation—happily revealed late last month, during an earnings call: "Clearwater Forest, our first Intel 18A part for servers has already gone into fab and Panther Lake for clients will be heading into Fab shortly." The former is positioned as the natural successor to Team Blue's many-times-delayed Xeon "Sierra Forest" (all E-Core) processor family. Intel's second generation E-core Xeon "Clearwater Forest" design is expected to launch in 2025, with a deployment of "Darkmont" efficiency-oriented cores. Official product roadmaps and patch notes have revealed basic "Clearwater Forest" information, but we have not seen many leaks. Bionic_Squash has a history of releasing strictly internal Intel presentation slides—Meteor Lake (MTL-S) desktop SKUs were uncovered last April.

Their latest discovery does not include any photo or documented evidence—Bionic_Squash's concise social media post stated: "Clearwater Forest uses 3D stacking with hybrid bonding." This claim points to the possible deployment of Foveros Direct advanced packaging—this technology was expected to be ready at some point within the second half of 2023, although a mid-December technology showcase implied that things were behind schedule. The fanciest "Clearwater Forest" Xeon processors could arrive with a maximum total of 288 E-core count (and 288 threads)—according to Wccftech analysis: "The CPU package is going to consist of a base tile on top of the interposer which is connected through a high-speed I/O, EMIB, and the cores will be sitting on the topmost layer...Foveros Direct technology will allow direct copper-to-copper bonding, enabling low resistance interconnects and around 10-micron bump pitches. Intel itself states that Foveros Direct will blur the boundary between where the wafer ends and the package begins."