Friday, December 13th 2024
Intel "Panther Lake" Confirmed on 18A Node, Powering-On With ES0 Silicon Revision
During Barclays 22nd Annual Global Technology Conference, Intel was a guest and two of the interim company co-CEOs Michelle Johnston Holthaus and David Zinsner gave a little update on the state of affairs at Intel. One of the most interesting aspects of the talk was Intel's upcoming "Panther Lake" processor—a direct successor to Intel Core Ultra 200S "Arrow Lake-H" mobile processors. The company confirmed that Panther Lake would utilize an Intel 18A node and that a few select customers have powered on Panther Lake on the E0 engineering sample chip. "Now we are using Intel Foundry for Panther Lake, which is our 2025 product, which will land on 18A. And this is the first time that we're customer zero in a long time on an Intel process," said interim co-CEO Michelle Johnston Holthaus, adding, "But just to give some assurances, on Panther Lake, we have our ES0 samples out with customers. We have eight customers that have powered on, which gives you just kind of an idea that the health of the silicon is good and the health of the Foundry is good."
While we don't know what ES0 means for Intel internally, we can assume that it is one of the first engineering samples on the 18A. The "ES" moniker usually refers to engineering samples, and zero after it could be the first design iteration. For reference, Intel's "Panther Lake-H" will reportedly have up to 18 cores: 6 P-cores, 8 E-cores, and 4 LP cores. The design brings back low-power island E-cores in the SoC tile. The P-cores use "Cougar Cove," which should have a higher IPC than "Lion Cove," while keeping the existing "Skymont" E-cores. The SoC tile may move from Arrow Lake's 6 nm to a newer process to fit the LP cores and an updated NPU. The iGPU is said to use the Xe3 "Celestial" architecture. With Arrow Lake-H launching in early 2025, Panther Lake-H likely won't arrive until 2026.
Source:
Conference Transcript
While we don't know what ES0 means for Intel internally, we can assume that it is one of the first engineering samples on the 18A. The "ES" moniker usually refers to engineering samples, and zero after it could be the first design iteration. For reference, Intel's "Panther Lake-H" will reportedly have up to 18 cores: 6 P-cores, 8 E-cores, and 4 LP cores. The design brings back low-power island E-cores in the SoC tile. The P-cores use "Cougar Cove," which should have a higher IPC than "Lion Cove," while keeping the existing "Skymont" E-cores. The SoC tile may move from Arrow Lake's 6 nm to a newer process to fit the LP cores and an updated NPU. The iGPU is said to use the Xe3 "Celestial" architecture. With Arrow Lake-H launching in early 2025, Panther Lake-H likely won't arrive until 2026.
17 Comments on Intel "Panther Lake" Confirmed on 18A Node, Powering-On With ES0 Silicon Revision
The real question though is: Will it run Crysis?
EDIT: This is actually nothing new. Information regarding to chip powering on is nearly half year old.
Are they trolling investors? Michelle, for god's sake, get yourself synchronized, would ya?
:p
We know only that it powers on and boots in customers machines. There's a loooooong time ahead, I see launch somewhere in Q3/24 at best.
Low power cores are good for notebook PCs where battery power is sometimes something people want - but, low-power cores cause desktop PCs to be less effective.
Engineering Sample -1?
For every 3 P cores, it should add 1 SP ("super core"), a brute force core, forming a set of 4 cores with 3 P cores + 1 SP (super core), since the software is (since forever) very poorly designed and practically always overloads 1 or 2 cores of the processor, even if it has dozens of cores. In this way, the software should be designed to overload the "super core" when it is very difficult or impossible to fragment the processing in the other cores.
In short, features of modern fast cores are not really present in Skymont.