MacBook Air aficionados, at least most of them, have been longing for an OLED-equipped variant for quite a while now. OLED displays, especially the tandem-style units that Apple ships with its iPad Pros, have undeniable advantages over tradition LCDs, such as a near-infinite contrast ratio, near-instant response times, and excellent color reproduction. The fear of panel burn-in does exist, although as OLED technology progresses, such fears continue to subside. That said, for those who are holding out for it, the grapevine indicates they will have to hold their horses for a while longer.

A recent report by The Elec has stated that the MacBook Air, which was previously expected to get the OLED treatment sometime in 2027, has now been delayed by another two years. As such, the MacBook Air is now not expected to boast an OLED display before 2029 at the earliest. The Elec claims that the primary cause behind the delay is the lackluster sales boost brought by the OLED upgrade to the iPad Pro lineup, which fell short of what Apple anticipated. That said, the MacBook Air will utilize "Oxide TFT" technology for its LCDs starting 2027, allowing for improved color accuracy, energy efficiency, and contrast. MacBook Pros have already utilized the technology since 2022, and are still expected to boast OLED panels by 2026.

Intel product change notification documents—published on January 6—have revealed the planned "End of Life" (EOL) phasing out of 12th Generation "Alder Lake" mobile processor models. Tom's Hardware has pored over the listed products/SKUs and concluded that the vast majority of Team Blue's mobile-oriented Alder Lake selection are destined for retirement. Team Blue's HX series is being kept alive for a little while longer. Two documents show differing "discontinuance timelines" for their respective inventories—including lower-end Celeron and Pentium Gold SKUs, as well as familiar higher-up Core i3, i5, i7, and i9 families. U, P, H and HK-affixed models are lined up for the chopping block.

Intel's 13th Generation "Raptor Lake" mobile processor selection—comprised of Core 100 (series 1) and Core 200 (series 2)—offers similar silicon makeup. Many equivalent alternatives to older generation "Alder Lake" chips reside here—Tom's Hardware presented a key example: "i5-1235U, which is designated for thin and lightweight laptops. OEMs can instead opt for the i5-1335U, the Core 5 120U, or the Core 5 220U, as they're just better bins of the 1235U on the same FCBGA1744 socket." A significant number of Alder Lake mobile SKUs will be available to OEMs for ordering up until 26 April, with final shipments heading out on 25 October. The rest have been assigned a July 25 order cut-off date, with final shipments scheduled on 26 January 2026.

During Barclays 22nd Annual Global Technology Conference, Intel was a guest and two of the interim company co-CEOs Michelle Johnston Holthaus and David Zinsner gave a little update on the state of affairs at Intel. One of the most interesting aspects of the talk was Intel's upcoming "Panther Lake" processor—a direct successor to Intel Core Ultra 200S "Arrow Lake-H" mobile processors. The company confirmed that Panther Lake would utilize an Intel 18A node and that a few select customers have powered on Panther Lake on the E0 engineering sample chip. "Now we are using Intel Foundry for Panther Lake, which is our 2025 product, which will land on 18A. And this is the first time that we're customer zero in a long time on an Intel process," said interim co-CEO Michelle Johnston Holthaus, adding, "But just to give some assurances, on Panther Lake, we have our ES0 samples out with customers. We have eight customers that have powered on, which gives you just kind of an idea that the health of the silicon is good and the health of the Foundry is good."

While we don't know what ES0 means for Intel internally, we can assume that it is one of the first engineering samples on the 18A. The "ES" moniker usually refers to engineering samples, and zero after it could be the first design iteration. For reference, Intel's "Panther Lake-H" will reportedly have up to 18 cores: 6 P-cores, 8 E-cores, and 4 LP cores. The design brings back low-power island E-cores in the SoC tile. The P-cores use "Cougar Cove," which should have a higher IPC than "Lion Cove," while keeping the existing "Skymont" E-cores. The SoC tile may move from Arrow Lake's 6 nm to a newer process to fit the LP cores and an updated NPU. The iGPU is said to use the Xe3 "Celestial" architecture. With Arrow Lake-H launching in early 2025, Panther Lake-H likely won't arrive until 2026.

Fujitsu has previewed its next-generation Monaka processor, a 144-core powerhouse for data center. Satoshi Matsuoka of the RIKEN Center for Computational Science showcased the mechanical sample on social media platform X. The Monaka processor is developed in collaboration with Broadcom and employs an innovative 3.5D eXtreme Dimension System-in-Package architecture featuring four 36-core chiplets manufactured using TSMC's N2 process. These chiplets are stacked face-to-face with SRAM tiles through hybrid copper bonding, utilizing TSMC's N5 process for the cache layer. A distinguishing feature of the Monaka design is its approach to memory architecture. Rather than incorporating HBM, Fujitsu has opted for pure cache dies below compute logic in combination with DDR5 DRAM compatibility, potentially leveraging advanced modules like MR-DIMM and MCR-DIMM.

The processor's I/O die supports cutting-edge interfaces, including DDR5 memory, PCIe 6.0, and CXL 3.0 for seamless integration with modern data center infrastructure. Security in the design is taken care of with the implementation of Armv9-A's Confidential Computing Architecture for enhanced workload isolation. Fujitsu has set ambitious goals for the Monaka processor. The company aims to achieve twice the energy efficiency of current x86 processors by 2027 while maintaining air cooling capabilities. The processor aims to do AI and HPC with the Arm SVE 2 support, which enables vector lengths up to 2048 bits. Scheduled for release during Fujitsu's fiscal year 2027 (April 2026 to March 2027), the Monaka processor is shaping up as a competitor to AMD's EPYC and Intel's Xeon processors.

Global sales of total semiconductor manufacturing equipment by original equipment manufacturers (OEMs) are forecast to set a new industry record, reaching $113 billion in 2024, growing 6.5% year-on-year, SEMI announced today in its Year-End Total Semiconductor Equipment Forecast - OEM Perspective at SEMICON Japan 2024. Semiconductor manufacturing equipment growth is expected to continue in the following years, reaching new records of $121 billion in 2025 and $139 billion in 2026, supported by both the front-end and back-end segments.

"Three consecutive years of projected growth in investments in semiconductor manufacturing reflect the vital role our industry plays in underpinning the global economy and advancing technology innovation," said Ajit Manocha, SEMI president and CEO. "Since our July 2024 forecast, the outlook for 2024 semiconductor equipment sales has brightened, especially with stronger-than-expected investments from China and in AI-related sectors. Together with our forecast extension through 2026, it highlights the robust growth drivers across segments, applications, and regions."

Apple is reportedly considering diversifying its chip manufacturing strategy with a new silicon manufacturer: Intel. While the upcoming iPhone 17 series, expected next year, will likely feature A19 chips produced by TSMC, a recent rumor from Chinese leaker Fixed Focus Digital hints at a potential switch to Intel for the A20 chipsets powering the 2026 iPhone 18 series. The A18 and A18 Pro chipsets debuted alongside the iPhone 16 series in September 2024, manufactured using TSMC's N3E node. Apple's A19 chips are expected to upgrade to TSMC's N3P node. According to the source, Apple is seeking an Intel 20A node. However, since the A20 node is canceled in favor of 18A, Apple could be an Intel Foundry customer for either 18A or 14A nodes.

Despite the buzz, skepticism persists. Intel has historically struggled with process node transitions and even outsourced production of its Arrow Lake CPUs to TSMC, raising questions about its readiness to deliver on Apple's demands. On the other hand, alternative reports suggest Apple might stick with TSMC's yet-unnamed 2 nm node for the A20, maintaining continuity in its supply chain. As the iPhone 18 series remains two years away, much can change. For now, we are left speculating whether this rumored collaboration with Intel represents a new chapter in Apple's chipset innovation or just a rumor with little substance. If the US government mandates more domestic production, chip designers could be looking at some of the more local manufacturing options, like Intel does on US soil. That could force Apple, NVIDIA, AMD, and Qualcomm to look into Intel's offerings.

For over half a century, general-purpose processors have been built on the Tomasulo algorithm, developed by IBM engineer Robert Tomasulo in 1967. It's a $500B industry built on specialized CPU, GPU and other chips for different computing tasks. Hardware startup Ubitium has shattered this paradigm with a breakthrough universal processor that handles all computing workloads on a single, efficient chip - unlocking simpler, smarter, and more cost-effective devices across industries - while revolutionizing a 57-year-old industry standard.

Alongside this, Ubitium is announcing a $3.7 million in seed funding round, co-led by Runa Capital, Inflection, and KBC Focus Fund. The investment will be used to develop the first prototypes and prepare initial development kits for customers, with the first chips planned for 2026.

NVIDIA today announced incoming changes to its GeForce Now game streaming service, some of which are not likely to sit well with gamers. The biggest, and likely most controversial change coming to GeForce Now is the addition of monthly playtime caps for all GeForce Now users, regardless of which plan they're on. According to the blog post announcing the changes, GeForce Now gamers will be limited to 100 hours of gameplay per month in addition to the daily playtime caps. NVIDIA will allow gamers who don't use their whole monthly cap to roll 15 hours of game time into the following month.

It's not all bad news, however, as NVIDIA also announced that it will be increasing the resolution and image quality of the GeForce Now Performance tier—previously Priority—from 1080p to 1440p. The Ultimate and Basic tiers remain unchanged in both name and feature set. NVIDIA says the playtime limit was necessary in order "to continue providing exceptional quality and speed—as well as shorter queue times." Of course players can buy extra playtime at a rate of $2.99 for 15 hours of GeForce Now Performance and $5.99 for 15 hours of GeForce Now Ultimate. The playtime limits will come into effect on January 1, 2025, and anyone that signs up for a paid GeForce Now subscription before then won't be subjected to the new playtime limits until January 2026.

According to TechNews Taiwan, Intel has made significant progress in implementing ASML's cutting-edge High-NA EUV lithography technology. The company has successfully completed the assembly of its second High-NA "Twinscan EXE" EUV system at its Portland facility, as confirmed by Mark Phillips, Intel's Director of Lithography Hardware. Christophe Fouquet, CEO of ASML, highlighted that the new assembly process allows for direct installation at the customer's site, eliminating the need for disassembly and reassembly, thus saving time and resources. Phillips expressed enthusiasm about the technology, noting that the improvements offered by High-NA EUV machines have surpassed expectations compared to standard EUV systems. Given the massive $380 million price point of these High-NA systems, any savings are valuable in the process.

The rapid progress in installation and implementation of High-NA EUV technology at Intel's facilities positions the company strongly for production transition. With all necessary infrastructure in place and inspections of High-NA EUV masks already underway, Intel aims to have its Intel 14A process in mass production by 2026-2027. As Intel leads in High-NA EUV adoption, other industry giants are following suit. ASML plans to deliver High-NA EUV systems to TSMC by year-end, with rumors suggesting that TSMC's first system will possibly arrive in September. Samsung has also committed to the technology, although recent reports indicate a potential reduction in their procurement plans. Additionally, this development has sparked discussions about the future of photoresist technology, with Phillips suggesting that while Chemically Amplified Resist (CAR) is currently sufficient, future advancements may require metal oxide photoresists. This provides a small insight into Intel's future nodes.

Intel has begun sampling the test tools for their "Oak Stream" platform which will house the "Diamond Rapids" generation of processors sometime in late 2025 or early 2026. Previously rumored to continue using the "Birch Stream" platform LGA 7529 socket that will soon be shipping with the 288-core flavor of the "Sierra Forest" efficiency core Xeons as well as 120-core "Granite Rapids" performance core Xeons, "Diamond Rapids" appears to instead be moving up to a substantially larger LGA 9324 socket. This is Intel's next-next generation of Xeon from what is shipping today, following up on the next-gen Intel 18A based "Clearwater Forest" which was only just reported to be powering on earlier this month. Other than the codename there is almost nothing currently known about "Diamond Rapids" but the rumor mill is already fired up and mentioning things such as increased core counts, 16 DRAM channels (similar to what AMD is expected to introduce with EPYC "Venice") and PCI-E 6.0 support.

The LGA 9324 test interposer for use with Intel's Gen 5 VR Test Tool that appeared on their Design-in Tools storefront before the page went to a 404 error carried a price tag of $900 USD and stipulated that this was a pre-order with an expected shipment date in Q4 2024.

0patch plans to combat Microsoft's ending Windows 10 support by offering unofficial security updates for the 2015 operating system. Microsoft is ending Windows 10 security updates on October 14, 2025, after which the OS will stop receiving patches for vulnerabilities. The Redmond giant will provide you with an option to update your Windows 10 build, however, with a hefty fee slapped. Extended Security Updates (ESU) pricing structure follows a tiered model that doubles each year. From October 2025 to October 2026, the cost is $61 per device. The following year, from October 2026 to October 2027, the price increases to $122 per device. In the final year, spanning October 2027 to October 2028, the cost rises to $244 per device. For users planning to maintain Windows 10 until October 2028, the total expense over the three-year period would amount to $427 per device.

However, 0patch, a company focused on providing unofficial security updates for Windows OSes, will provide Windows 10 users with free and paid security updates post-end of service. Their system focuses on delivering targeted "micropatches" for critical vulnerabilities that emerge after Microsoft's official support ends. These micropatches are designed to be extremely precise and minimal, often consisting of just a few CPU instructions. A key feature of 0patch's approach is its non-invasive nature. The patches are applied directly to running processes in the computer's memory, leaving the original Microsoft files untouched. This method allows for rapid deployment of security fixes without requiring system reboots or interrupting user activities. The patching process is designed to be seamless and virtually unnoticeable to users. For instance, a user working on a document wouldn't experience any disruption while a micropatch is being applied. This approach is particularly beneficial for servers, where continuous uptime is crucial, as patches can be implemented without any downtime.

Micron has announced more precise timeframes for the commencement of operations at its two new memory facilities in the United States during its Q3 FY2024 results presentation. The company expects these fabs, located in Idaho and New York, to begin production between late 2026 and 2029. The Idaho fab, currently under construction near Boise, is slated to start operations between September 2026 and September 2027. Meanwhile, the New York facility is projected to come online in the calendar year 2028 or later, pending the completion of regulatory and permitting processes. These timelines align with Micron's original plans announced in 2022 despite recent spending optimizations. The company emphasizes that these investments are crucial to support supply growth in the latter half of this decade.

Micron's capital expenditure for FY2024 is set at approximately $8 billion, with a planned increase to around $12 billion in FY2025. This substantial rise in spending, targeting a mid-30s percentage of revenue, will support various technological advancements and facility expansions. A substantial portion of this increased investment - over $2 billion - will be dedicated to constructing the new fabs in Idaho and New York. Additional funds will support high-bandwidth memory assembly and testing, as well as the development of other fabrication and back-end facilities. Sanjay Mehrotra, Micron's CEO, underscored the importance of these investments, stating that the new capacity is essential to meet long-term demand and maintain the company's market position. He added that these expansions, combined with ongoing technology transitions in Asian facilities, will enable Micron to grow its memory bit supply in line with industry demand.

JEDEC is currently presiding over standards for 6th generation high bandwidth memory (AKA HBM4)—the 12 and 16-layer DRAM designs are expected to reach mass production status in 2026. According to a ZDNET South Korea report, involved manufacturers are deliberating over HBM4 package thicknesses—allegedly, decision makers have settled on 775 micrometers (μm). This is thicker than the previous generation's measurement of 720 micrometers (μm). Samsung Electronics, SK Hynix and Micron are exploring "hybrid bonding," a new packaging technology—where onboard chips and wafers are linked directly to each other. Hybrid bonding is expected to be quite expensive to implement, so memory makers are carefully considering whether HBM4 warrants its usage.

ZDNET believes that JEDEC's agreement—settling on 775 micrometers (μm) for 12-layer and 16-layer stacked HBM4—could have: "a significant impact on the future packaging investment trends of major memory manufacturers. These companies have been preparing a new packaging technology, hybrid bonding, keeping in mind the possibility that the package thickness of HBM4 will be limited to 720 micrometers. However, if the package thickness is adjusted to 775 micrometers, 16-layer DRAM stacking HBM4 can be sufficiently implemented using existing bonding technology." A revised schedule could delay the rollout of hybrid bonding—perhaps pushed back to coincide with a launch of seventh generation HBM. The report posits that Samsung Electronics, SK Hynix and Micron memory engineers are about to focus on the upgrading of existing bonding technologies.

The Samsung Group has formed a new cross-department alliance—according to South Korea's Sedaily—this joint operation will concentrate on the research and development of a "dream substrate." The company's Electronics, Electrical Engineering, and Display divisions are collaborating in order to accelerate commercialization of "glass substrate" chip packaging. Last September, Intel revealed its intention to become an industry leader in "glass substrate production for next-generation advanced packaging." Team Blue's shiny new Arizona fabrication site will be taking on this challenge, following ten years of internal R&D work. Industry watchdogs reckon that mass production—in North America—is not expected to kick off anytime soon. Sensible guesstimates suggest a start date somewhere in 2030.

The Sedaily article states that Samsung's triple department alliance will target "commercialization faster than Intel." Company representatives—in attendance at CES 2024—set a 2026 window as their commencement goal for advanced glass substrate chip package mass production. An unnamed South Korean industry watcher has welcomed a new entrant on the field: "as each company possesses the world's best technology, synergies will be maximized in glass substrate research, which is a promising field...it is also important to watch how the glass substrate ecosystem of Samsung's joint venture will be established." Glass substrate packaging is ideal for "large-area and high-performance chip combinations" due to inherent heat-resistant properties and material strength. So far, the semiconductor industry has struggled with its development—hence the continued reliance on plastic boards and organic materials.

According to renowned Apple analyst Ming-Chi Kuo, Apple is actively working on a foldable 20.3-inch MacBook, with mass production expected to begin in 2027. In a recent post on X/Twitter, Kuo stated that this foldable MacBook is currently Apple's only foldable product with a clear development schedule. Kuo's revelation comes amidst frequent inquiries about whether Apple plans to mass-produce a foldable iPhone or iPad in 2025 or 2026. His latest survey indicates that while Apple may explore these options, the foldable MacBook is the only device with a definitive timeline. This is not the first time rumors have circulated about a potential foldable MacBook from Apple. In 2022, display industry analyst Ross Young and Bloomberg's Mark Gurman both reported that Apple was interested in launching a foldable device with a screen size of around 20 inches.

Details about the foldable MacBook's design remain scarce, but it is expected to feature a single foldable OLED display that can be used in various configurations, such as a laptop mode with a virtual keyboard on the lower half of the screen or as a large tablet when fully unfolded. While competitors like Samsung, Motorola, and Huawei have already released foldable smartphones, Apple appears to be more cautious, focusing on perfecting the technology before bringing a product to market. As the foldable device market evolves, it will be interesting to see how Apple's unique take on the form factor fares. As Apple's first foldable product, it will be interesting to see what design choices are made and what hardware configuration will be present. But we are still relatively far away from the actual release of 2027.

ASML has revealed that its cutting-edge High-NA extreme ultraviolet (EUV) chipmaking tools, called High-NA Twinscan EXE, will cost around $380 million each—over twice as much as its existing Low-NA EUV lithography systems that cost about $183 million. The company has taken 10-20 initial orders from the likes of Intel and SK Hynix and plans to manufacture 20 High-NA systems annually by 2028 to meet demand. The High-NA EUV technology represents a major breakthrough, enabling an improved 8 nm imprint resolution compared to 13 nm with current Low-NA EUV tools. This allows chipmakers to produce transistors that are nearly 1.7 times smaller, translating to a threefold increase in transistor density on chips. Attaining this level of precision is critical for manufacturing sub-3 nm chips, an industry goal for 2025-2026. It also eliminates the need for complex double patterning techniques required presently.

However, superior performance comes at a cost - literally and figuratively. The hefty $380 million price tag for each High-NA system introduces financial challenges for chipmakers. Additionally, the larger High-NA tools require completely reconfiguring chip fabrication facilities. Their halved imaging field also necessitates rethinking chip designs. As a result, adoption timelines differ across companies - Intel intends to deploy High-NA EUV at an advanced 1.8 nm (18A) node, while TSMC is taking a more conservative approach, potentially implementing it only in 2030 and not rushing the use of these lithography machines, as the company's nodes are already developing well and on time. Interestingly, the installation process of ASML's High-NA Twinscan EXE 150,000-kilogram system required 250 crates, 250 engineers, and six months to complete. So, production is as equally complex as the installation and operation of this delicate machinery.

SK Hynix has unveiled ambitious High Bandwidth Memory (HBM) roadmaps at SEMICON Korea 2024. Vice President Kim Chun-hwan announced plans to mass produce the cutting-edge HBM3E within the first half of 2024, touting 8-layer stack samples already supplied to clients. This iteration makes major strides towards fulfilling surging data bandwidth demands, offering 1.2 TB/s per stack and 7.2 TB/s in a 6-stack configuration. VP Kim Chun-hwan cites the rapid emergence of generative AI, forecasted for 35% CAGR, as a key driver. He warns that "fierce survival competition" lies ahead across the semiconductor industry amidst rising customer expectations. With limits approaching on conventional process node shrinks, attention is shifting to next-generation memory architectures and materials to unleash performance.

SK Hynix has already initiated HBM4 development for sampling in 2025 and mass production the following year. According to Micron, HBM4 will leverage a wider 2048-bit interface compared to previous HBM generations to increase per-stack theoretical peak memory bandwidth to over 1.5 TB/s. To achieve these high bandwidths while maintaining reasonable power consumption, HBM4 is targeting a data transfer rate of around 6 GT/s. The wider interface and 6 GT/s speeds allow HBM4 to push bandwidth boundaries significantly compared to prior HBM versions, fueling the need for high-performance computing and AI workloads. But power efficiency is carefully balanced by avoiding impractically high transfer rates. Additionally, Samsung is aligned on a similar 2025/2026 timeline. Beyond pushing bandwidth boundaries, custom HBM solutions will become increasingly crucial. Samsung executive Jaejune Kim reveals that over half its HBM volume already comprises specialized products. Further tailoring HBM4 to individual client needs through logic integration presents an opportunity to cement leadership. As AI workloads evolve at breakneck speeds, memory innovation must keep pace. With HBM3E prepping for launch and HBM4 in the plan, SK Hynix and Samsung are gearing up for the challenges ahead.

A Taiwan Economic Daily news article proposes that a couple of high profile clients are considering TSMC's 2 nanometer process—Apple is widely believed to be the first customer to join the foundry's queue for cutting edge services. The report posits that Intel is also signed up on the Taiwanese firm's 2 nm reservation list—TSMC is expected to start production in 2025—insiders reckon that Team Blue's "Nova Lake" CPU family is the prime candidate here. Its CPU tile is alleged to utilize TSMC 2 nm node. Intel's recent "Core" processor roadmaps do not display any technologies beyond 2025—many believe that "Nova Lake" is pencilled in for a loose 2026 launch window, perhaps within the second half of the year.

The existence of "Nova Lake" was revealed late last year by HWiNFO patch notes—a short entry mentioned preliminary support for the family's integrated GPU. Intel is engaged in hyping up of its own foundry's 20A and 18A processes, but remain reliant on TSMC plants for various bits of silicon. Industry tipsters reckon that aspects of "Lunar Lake" CPUs are based on the Taiwanese foundry's N3B node. Team Blue Corporation and United Microelectronics Corporation (UMC) announced a new development partnership last week, but initial offerings will arrive on a relatively passé "12-nanometer semiconductor process platform." TSMC's very advanced foundry services seem to be unmatched at this juncture.

Apple has announced a partnership deal with Amkor, one of the leading chip packaging and testing manufacturers, which will build a two billion US Dollar silicon packaging facility in Peoria, Arizona. Being the only US-based OSAT (outsourced semiconductor assembly and test) provider, Amkor has decided to invest its funds and apply for the CHIPS Act, hoping to get a part of the funding from the US government's grant budget. The state-of-the-art facility in Arizona will feature over 500,000 square feet (46,452 square meters) of cleanroom space for packaging and testing chips. Using Amkor's latest technologies, the plant will support advanced computing, automotive, and communications chip packaging. It is tailored to meet the capacity needs of major customer Apple starting in 2025-2026. Apple will be the largest customer, with the Amkor facility packaging Apple-designed chips produced at the nearby TSMC wafer fabrication plant.

Building a chip packaging facility in the US with advanced packaging types means that the domestic manufacturing of advanced silicon is now possible across almost the entire supply chain, with OSAT now being present on US soil as well. In the initial phase, this partnership will enable domestic advanced packaging capabilities for leading-edge chips down to 3 nm nodes, which Apple plans to utilize for its A and M series of processors. Along with the creation of an estimated 2,000 local jobs, the investment serves as a boost to the local economy as well. Additionally, Amkor is TSMC's strategic partner, meaning future designs and packaging will cooperate without any delays.

International Data Corporation (IDC) has upgraded its Semiconductor Market Outlook by calling a bottom and return to growth that accelerates next year. IDC raised its September 2023 revenue outlook from $518.8 billion to $526.5 billion in a new forecast. Revenue expectations for 2024 were also raised from $625.9 billion to $632.8 billion as IDC believes the U.S. market will remain resilient from a demand standpoint and China will begin recovering by the second half of 2024 (2H24).

IDC sees better semiconductor growth visibility as the long inventory correction subsides in two of the largest market segments: PCs and smartphones. Automotive and Industrials elevated inventory levels are expected to return to normal levels in 2H24 as electrification continues to drive semiconductor content over the next decade. Technology and large flagship product introductions will drive more semiconductor content and value across market segments in 2024 through 2026, including the introduction of AI PCs and AI Smartphones next year and a much-needed improvement in memory ASPs and DRAM bit volume.

Thanks to the TMTPost interview with the Global Vice President and China President of ASML, Shen Bo, the Dutch semiconductor equipment manufacturer has revealed that around 1,400 of its deep ultraviolet (DUV) lithography and metrology machines are currently installed in China. The company is expected to achieve a global output of 600 DUV equipment units by the end of 2025. Shen Bo stated that the company aims to install 500-600 units of DUV machinery in China by late 2025 or early 2026. The growth in ASML's Chinese revenues was notably high, with China contributing 46% of the company's system sales in 3Q 2023, representing an 82% revenue increase from the previous quarter.

China plans to build 25 12-inch wafer fabs in the next five years, covering logic wafers, DRAM, and MEMS production. ASML currently has a substantial presence in China, with 16 offices, 12 warehouses, distribution centers, development centers, training centers, and maintenance centers. The company employs over 1,600 people for its China operations. Despite the export restrictions imposed by the US government, ASML anticipates that the new measures will have little impact on its financial outlook for 2023 as it strives to meet the growing demand for semiconductor manufacturing equipment in the global market.

Ever since the creation of A64FX for the Fugaku supercomputer, Fujitsu has been plotting the development of next-generation CPU design for accelerating AI and general-purpose HPC workloads in the data center. Codenamed Monaka, the CPU is the latest creation for TSMC's 2 nm semiconductor manufacturing node. Based on Armv9-A ISA, the CPU will feature up to 150 cores with Scalable Vector Extensions 2 (SVE2), so it can process a wide variety of vector data sets in parallel. Using a 3D chiplet design, the 150 cores will be split into different dies and placed alongside SRAM and I/O controller. The current width of the SVE2 implementation is unknown.

The CPU is designed to support DDR5 memory and PCIe 6.0 connection for attaching storage and other accelerators. To bring cache coherency among application-specific accelerators, CXL 3.0 is present as well. Interestingly, Monaka is planned to arrive in FY2027, which starts in 2026 on January 1st. The CPU will supposedly use air cooling, meaning the design aims for power efficiency. Additionally, it is essential to note that Monaka is not a processor that will power the post-Fugaku supercomputer. The post-Fugaku supercomputer will use post-Monaka design, likely iterating on the design principles that Monaka uses and refining them for the launch of the post-Fugaku supercomputer scheduled for 2030. Below are the slides from Fujitsu's presentation, in Japenese, which highlight the design goals of the CPU.

According to TechNews.tw, TSMC could postpone its 2 nm semiconductor manufacturing node for 2026. If the rumors about TSMC's delayed 2 nm production schedule are accurate, the implications could reverberate throughout the semiconductor industry. TSMC's alleged hesitancy could be driven by multiple factors, including the architectural shift from FinFET to Gate-All-Around (GAA) and potential challenges related to scaling down to 2 nm. The company is a crucial player in this space, and a delay could offer opportunities for competitors like Samsung, which has already transitioned to GAA transistor architecture for its 3 nm chips. Given the massive demand for advanced nodes due to the rise of AI, IoT, and other next-gen technologies, it is surprising to hear "sluggish" demand reports.

However, it's also possible that it's too early for customers to make firm commitments for 2025 and beyond. TSMC has dismissed these rumors, stating that construction is progressing according to plan, which includes having 2 nm pilot run in 2024, and mass production in the second half of 2025.. Despite this, any delay in TSMC's roadmap could serve as a catalyst for shifts in market dynamics. Companies that rely heavily on TSMC's advanced nodes might need to reassess their timelines and strategies. Moreover, if Samsung can capitalize on this opportunity, it could somewhat level the playing field. As of now, though, it's essential to approach these rumors with caution until more concrete information becomes available.

Hardware leaker, YuuKi_AnS, has briefly turned their attention away from all things Team Blue—their latest leak points to upcoming server-grade processors chez AMD. A Zen 6 core-based 9006 EPYC CPU series, codenamed "Venice," is expected to arrive within two to three years along with an all-new SP7 socket—this information seems to have been sourced from an unnamed server manufacturer's product roadmap. A partial view of said slide also reveals forthcoming equipment powered by Intel "Falcon Shore" and NVIDIA "Blackwell" GPU technologies.

As reported a couple of months ago, older insider info has AMD using "Weisshorn" as an in-house moniker for Zen 6 "Morpheus" architecture, destined for Venice CPUs—alleged to form part of a 2025/2026 EPYC lineup. YuuKi_AnS proposes that these will utilize either 12-channel or 16-channel DDR5 memory configurations—thus providing plenty of bandwidth across hundreds of Zen cores. Altogether very handy for cloud, enterprise, and HPC workloads—industry experts reckon that 384-core counts are feasible on single packages. Naturally, a Team Red timeline dictates that Zen 5 "Nirvana" is due before Zen 6 "Morpheus," so EPYC 9005 "Turin(-X)" and 8005 "Turin-Dense" lineups are (allegedly) up for a 2024-ish launch window on SP5 (LGA-6096) and SP6 (LGA 4094) socket types.

Jon Peddie Research reports the growth of the global PC-based graphics processor unit (GPU) market reached 61.6 million units in Q2'23 and PC CPU shipments decreased by -23% year over year. Overall, GPUs will have a compound annual growth rate of 3.70% during 2022-2026 and reach an installed base of 2,998 million units at the end of the forecast period. Over the next five years, the penetration of discrete GPUs (dGPUs) in the PC will grow to reach a level of 32%.

Year to year, total GPU shipments, which include all platforms and all types of GPUs, decreased by -27%, desktop graphics decreased by -36%, and notebooks decreased by -23%.