Intel's next-generation client CPU staple product, "Nova Lake-S", has reportedly taped out of TSMC's fabs in Taiwan. Our previous speculation from the rumor mill suggested that Intel would utilize its own internal 18A node, with help from TSMC's 2 nm high-volume manufacturing. According to SemiAccurate, Intel has taped out a compute tile on TSMC's N2 node, meaning that Nova Lake-S will likely utilize a mix of 18A and TSMC N2 for its compute tiles. A possible reason for this decision is that Intel is building a chain of fall-backs to rely on in case its 18A node doesn't deliver, or it anticipates demand so high that its internal manufacturing capacity can't provide. Either way, clients can expect the product to be delivered on time in H2 of 2026, but under the hood, some interesting solutions may be present.

As far as the exact date, the time from a tapeout to final product is months away. Right now, the taped-out silicon tile is being powered on in Intel's labs and tested, running various test cases that stress out the silicon for multiple use cases and check for correctness of operation. Typically, power on takes a few weeks to a month to achieve, and final high-volume manufacturing will commence only a few months later. From that point, another two to three months are needed for manufacturing and shipping the product, meaning that Q3 of 2026 is the most likely target for Nova Lake-S. As a reminder, the CPU will combine 52 cores (16 P-cores, 32 E-cores, and four LPE-cores) paired with 8,800 MT/s memory controller and Xe3 "Celestial" for graphics rendering and Xe4 "Druid" for media and display duties, making it definitely an interesting product, as well as a difficult manufacturing target due to the heterogenous complexity.

European Processor Initiative (EPI) is nearing completion of its first goal. SiPearl, the leading developer behind the Rhea1 processor, has finally reached the tapeout stage after a string of delays, but it will not be ready for delivery until 2026 at the earliest. When the project launched in 2020, SiPearl planned to begin production in 2023; however, the 61 billion-transistor chip only entered tapeout this summer. The design, built on TSMC's N6 process, features 80 Arm Neoverse V1 cores alongside 64 GB of HBM2E memory and a DDR5 interface. While these specifications once looked cutting‑edge, the industry has already moved on, and Rhea1's raw performance may seem dated by the time samples are available. SiPearl initially explored a RISC‑V architecture back in 2019 but abandoned it after early feedback and comments highlighted the instruction set's immaturity for exascale computing.

Development was further interrupted by shifting core‑count debates, with teams alternately considering 72 cores, then 64, before finally settling on 80 cores by 2022. Those back‑and‑forth decisions, combined with evolving performance expectations, helped push the timeline back by years. Despite missing its original schedule, Rhea1 remains vital to European ambitions for high‑performance computing sovereignty and serves as the intended CPU for the Jupiter supercomputer. Thanks to Jupiter's modular design, the system was not left idle; its GPU booster module, running NVIDIA Grace Hopper accelerators, is already operational and approximately 80 percent complete. With the CPU clusters slated for mid-2026 deployment, full system readiness is expected by the end of 2026. To support this effort, SiPearl has recently secured €130 million in new financing from the French government, industry partners, and Taiwan's Cathay Venture. As Rhea1 finishes its goal, work on Rhea2 is already underway, and we can expect more updates about Rhea2 in a year or two.

Micron has achieved a significant advancement of the HBM4 architecture, which will stack 12 DRAM dies (12-Hi) to provide 36 GB of capacity per package. According to company representatives, initial engineering samples are scheduled to ship to key partners in the coming weeks, paving the way for full production in early 2026. The HBM4 design relies on Micron's established 1β ("one-beta") process node for DRAM tiles, in production since 2022, while it prepares to introduce EUV-enabled 1γ ("one-gamma") later this year for DDR5. By increasing the interface width from 1,024 to 2,048 bits per stack, each HBM4 chip can achieve a sustained memory bandwidth of 2 TB/s, representing a 20% efficiency improvement over the existing HBM3E standard.

NVIDIA and AMD are expected to be early adopters of Micron's HBM4. NVIDIA plans to integrate these memory modules into its upcoming Rubin-Vera AI accelerators in the second half of 2026. AMD is anticipated to incorporate HBM4 into its next-generation Instinct MI400 series, with further information to be revealed at the company's Advancing AI 2025 conference. The increased capacity and bandwidth of HBM4 will address growing demands in generative AI, high-performance computing, and other data-intensive applications. Larger stack heights and expanded interface widths enable more efficient data movement, a critical factor in multi-chip configurations and memory-coherent interconnects. As Micron begins mass production of HBM4, major obstacles to overcome will be thermal performance and real-world benchmarks, which will determine how effectively this new memory standard can support the most demanding AI workloads.

InstLatX64 has spent a significant chunk of time investigating AMD web presences; last month they unearthed various upcoming "Zen 5" processor families. This morning, a couple of mysterious CPU identifiers—"B50F00, B90F00, BA0F00, and BC0F00"—were highlighted in a social media post. According to screen-captured information, Team Red's Linux team seems to be patching in support for "Zen 6" technologies—InstLatX64 believes that the "B50F00" ID and internal "Weisshorn" codename indicate a successor to AMD's current-gen EPYC "Turin" server-grade processor series (known internally as "Breithorn"). Earlier in the month, a set of AIDA64 Beta update release notes mentioned preliminary support for "next-gen AMD desktop, server and mobile processors."

In a mid-April (2025) announcement, Dr. Lisa Su and colleagues revealed that their: "next-generation AMD EPYC processor, codenamed 'Venice,' is the first HPC product in the industry to be taped out and brought up on the TSMC advanced 2 nm (N2) process technology." According to an official "data center CPU" roadmap, "Venice" is on track to launch in 2026. Last month, details of "Venice's" supposed mixed configuration of "Zen 6" and "Zen 6C" cores—plus other technical tidbits—were disclosed via a leak. InstLatX64 and other watchdogs reckon that some of the latest identifiers refer to forthcoming "Venice-Dense" designs and unannounced Instinct accelerators.

Over a year ago, industry moles started chattering about a potential "late 2025" launch of NVIDIA "Rubin" AI accelerators/ GPUs. According to older rumors, one of the successors to current-gen "Blackwell" hardware could debut in chiplet-based "R100" form. Weeks ahead of Christmas 2024, Taiwanese insider reports pointed to Team Green's development of the "Rubin" AI project being sixth months ahead of schedule. Despite this extra positive outlook, experts surmised that the North American giant would not be rushing out shiny new options—especially with the recent arrival of "Blackwell Ultra" products. A lot of leaks seem to be coming from sources at (or adjacent to) TSMC.

Taiwan's top foundry service is reportedly in the "Rubin" equation; with a 3 nm (N3P) node process and CoWoS-L packaging linked to "R100." According to local murmurs, the final "taping out"—of Rubin GPUs and Vera CPUs—is due for completion this month. Trial production is expected run throughout the summer, with initial samples being ready for distribution by September. According to a fresh Ctee TW news report, unnamed supply chain participants reckon that NVIDIA's "new chip development schedule is smoother than before, and mass production (of Rubin and Vera chips) will begin as early as 2026." In theory, the first publicly exhibited final examples could turn up at CES 2026.

Qualcomm Incorporated today announced that it has reached an agreement with Alphawave IP Group plc regarding the terms and conditions of a recommended acquisition by Aqua Acquisition Sub LLC, an indirect wholly-owned subsidiary of Qualcomm Incorporated, for the entire issued and to be issued ordinary share capital of Alphawave Semi at an implied enterprise value of approximately US$2.4 billion.

The acquisition of Alphawave Semi aims to further accelerate, and provide key assets for, Qualcomm's expansion into data centers. Qualcomm Oryon CPU and Hexagon NPU processors are well positioned to meet the growing demand for high-performance, low-power computing, which is being driven by a rapid increase in AI inferencing and the transition to custom CPUs in data centers.

The news we've been waiting to share with you all is here! Bloodstained: The Scarlet Engagement is coming in 2026. Helmed by Creative Director SHUTARO and produced by IGA. Bloodstained: The Scarlet Engagement is an entirely new 2.5D side-scrolling RPG that will introduce exciting new lore, characters, gameplay and features to the Bloodstained franchise.

THE STORY
16th-century England drowns in the shadow of the Ethereal Castle and its deadly inhabitants. All attempts to fight this evil have been met with failure and death. In a desperate, final attempt, two heroes rise together against the Demon Lord Elias' reign of terror: Leonard Brandon and Alexander Kyteler. Leo is a young fighter with the Church's Black Wolves clan. Alex is a knight of the kingdom's White Stags and the lone survivor of an earlier expedition to fight Elias.

Kioxia announced its medium to long-term growth strategy and as a part of its growth strategy, the company is betting on advanced SSD technology to capture more market share. The company's most ambitious project is a breakthrough SSD that combines their XL-FLASH memory with a brand-new controller design. "We're taking our ultra-fast XL-Flash memory chips, which use single-level cells, and pairing them with a completely new controller," a company representative explained. "This combination should give us unprecedented performance for small-scale data operations. We're targeting over 10 million IOPS, and we plan to have samples ready by the second half of 2026." The company is also working closely with major GPU manufacturers to optimize performance for AI and graphics-intensive applications.

Meanwhile, Kioxia is rolling out its current generation of SSDs built on 8th generation BiCS FLASH technology. The CM9 series targets AI systems that need both blazing speed and rock-solid reliability to get the most out of expensive GPU hardware. On the other end, the LC9 series focuses on massive storage capacity, hitting 122 terabytes per drive for applications like large-scale databases that power AI inference systems.

Intel's "Nova Lake-S" desktop processors are getting the finishing touches, with a likely arrival scheduled for the second half of 2026. As the successor to "Arrow Lake Refresh," Nova Lake-S introduces a modular design that separates graphics and media functions across distinct tiles. This approach builds on experience from "Meteor Lake," which splits its graphics engine from its media and display units onto separate chiplets. For Nova Lake-S, Intel plans to employ two different GPU architectures: Xe3 "Celestial" for graphics rendering and Xe4 "Druid" for media and display duties, all within a single package. Celestial will manage primary 3D rendering and gaming workloads, while Druid will handle display pipelines and hardware-accelerated video encoding and decoding. By utilizing a more advanced process node, such as TSMC's 2 nm, Intel can optimize media engine performance without increasing costs for the entire GPU subsystem.

On the CPU side, Nova Lake-S is expected to span four primary SKU tiers. The flagship model could feature 52 cores (16 P-cores, 32 E-cores, and four LPE-cores). A 28-core version may target high-end laptops and desktops with eight P-cores, 16 E-cores, and four low-power E-cores. A 16-core variant could serve both the lower-power desktop and laptop segments, featuring four P-cores, eight E-cores, and four low-power E-cores. Finally, an 8-core entry-level part offers four P-cores and four low-power E-cores. Although it remains uncertain whether all SKUs will combine both Xe3 and Xe4 tiles, Intel's tile-based strategy makes it straightforward to mix and match GPU configurations for different market segments. Rumors also suggest that Intel may use its 18A node alongside TSMC's advanced processes for various tile elements. As Panther Lake mobile parts approach the second half of 2025 and Arrow Lake Refresh prepares for its desktop release, Nova Lake-S is the pinnacle of Intel's advanced chip packaging.

Early indications of AMD's next-generation Ryzen processors have surfaced as AIDA64's newest beta release adds initial support for Ryzen 10000 "Zen 6" desktop, server, and mobile chips. The update was noted by X user HXL, suggesting that AMD has quietly shared basic specifications with developers of hardware monitoring software. Looking back, AIDA64 tends to announce chip support almost a year before official launches, so these new processors may not appear until Computex 2026. Leaks from March 2025 suggest that AMD's Zen 6 desktop lineup, currently codenamed Medusa Ridge, will remain compatible with the existing AM5 socket. This news should please PC enthusiasts because it means many users will not have to replace their motherboards when upgrading. Reports indicate that Medusa Ridge CPUs may include 12-core chiplet dies, marking a step forward from previous architectures.

These chips are expected to be manufactured using TSMC's N3P process, which is designed to deliver improved power efficiency and higher frequencies. Additionally, a Zen 6-based X3D series is likely to feature a 3D V-Cache, targeting gamers. A model like the Ryzen 7 10800X3D could follow the success of the 9800X3D by offering strong performance at its price. On the mobile side, "Medusa Point" processors are rumored to incorporate up to 22 hybrid cores that combine performance and efficiency cores under the Zen 6 architecture. However, these mobile chips seem to be further off, with a launch window set for late 2026 or early 2027. Although AIDA64's beta edition now recognizes Ryzen 10000 series chips, AMD's usual schedule suggests we will not see them in shops until mid-2026 at the earliest. Still, compatibility with AM5 and a move to a more advanced process promise meaningful improvements when Zen 6 finally arrives.

Dell Technologies (NYSE: DELL) announces financial results for its fiscal 2026 first quarter. The company also provides guidance for its fiscal 2026-second quarter and full year.

First-Quarter Summary

• First-quarter revenue of $23.4 billion, up 5% year over year
• First-quarter operating income of $1.2 billion, up 21% year over year, and non-GAAP operating income of $1.7 billion, up 10%
• First-quarter diluted EPS of $1.37, flat year over year, and non-GAAP diluted EPS of $1.55, up 17%

After recording strong results in the first quarter of 2025, IDC is increasing its traditional PC forecast for 2025—this comes despite the significant impact that US tariffs have had on its trading partners' market sentiment. Global PC volume is now expected to reach 274 million in 2025, growing +4.1% over the prior year. Beyond 2025, IDC forecasts a slight contraction in 2026 due in part from volume stabilization following Windows 11 migration and to a more difficult comparison given a stronger market in 2025.

"The 90 day pause and tariffs exemption applied to personal computers, combined with a definite level of uncertainty on what will happen after the 90 day pause, is motivating PC manufacturers to seize the moment and ship larger than anticipated volumes in the US," said Jean Philippe Bouchard, research VP with IDC's Worldwide PC Trackers. "However, expectations of worsening macroeconomic conditions around the world and in the US characterized by upward pressures on prices and degrading consumer sentiment, will impact the PC market in the second half of 2025. Nonetheless, IDC expects commercial demand for PCs to be healthy in 2025 as the Windows 11 migration continues steadily."

NVIDIA today reported revenue for the first quarter ended April 27, 2025, of $44.1 billion, up 12% from the previous quarter and up 69% from a year ago.

On April 9, 2025, NVIDIA was informed by the U.S. government that a license is required for exports of its H20 products into the China market. As a result of these new requirements, NVIDIA incurred a $4.5 billion charge in the first quarter of fiscal 2026 associated with H20 excess inventory and purchase obligations as the demand for H20 diminished. Sales of H20 products were $4.6 billion for the first quarter of fiscal 2026 prior to the new export licensing requirements. NVIDIA was unable to ship an additional $2.5 billion of H20 revenue in the first quarter.

AMD is already looking ahead to its Zen 7 generation and is planning the final details for its next generation of Zen IP. The first hints come from YouTuber "Moore's Law Is Dead," which points to a few interesting decisions. AMD plans to extend its multi‑class core strategy that began with Zen 4c and continued into Zen 5. Zen 7 will reportedly include three types of cores: the familiar performance cores, dense cores built for maximum throughput, and a new low‑power variant aimed at energy‑efficient tasks, just like Intel and its LP/E-Cores. There is even an unspecified "PT" and "3D" core. By swapping out pipeline modules and tweaking their internal libraries, AMD can fine‑tune each core so it performs best in its intended role, from running virtual machines in the cloud to handling AI workloads at the network edge.

On the manufacturing front, Zen 7 compute chiplets (CCDs) are expected to be made on TSMC's A14 process, which will now include a backside power delivery network. This was initially slated for the N2 node but got shifted to the A16/A14 line. The 3D V‑Cache SRAM chiplets underneath the CCDs will remain on TSMC's N4 node. It is a conservative choice, since TSMC has talked up using N2‑based chiplets for stacked memory in advanced packaging, but AMD appears to be playing it safe. Cache sizes should grow, too. Each core will get 2 MB of L2 cache instead of the current 1 MB, and L3 cache per core could expand to 7 MB through stacked V‑Cache slices. Standard CCDs without V‑Cache will still have around 32 MB of shared L3. A bold rumor suggests an EPYC model could feature 33 cores per CCD, totaling 264 cores across eight CCDs. Zen 7 tape‑out is planned for late 2026 or early 2027, and we probably won't see products on shelves until 2028 or later. As always with early-stage plans, take these details with a healthy dose of skepticism. The final Zen 7 lineup could look quite different once AMD locks down its roadmap.

At the recent AI Semiconductor Forum in Seoul, Samsung Electronics revealed that it will adopt hybrid bonding in its upcoming HBM4 memory stacks. This decision is intended to reduce thermal resistance and enable an ultra‑wide memory interface, qualities that become ever more critical as artificial intelligence and high‑performance computing applications demand greater bandwidth and efficiency. Unlike current stacking methods that join DRAM dies with tiny solder microbumps and underfill materials, hybrid bonding bonds copper‑to‑copper and oxide‑to‑oxide surfaces directly, resulting in thinner, more thermally efficient 3D assemblies. High‑bandwidth memory works by stacking multiple DRAM dies on top of a base logic die, with through‑silicon vias carrying signals vertically through each layer. Traditionally, microbumps routed horizontal connections between dies, but as data rates increase and stack heights grow, these bumps introduce significant electrical and thermal limitations.

Hybrid bonding addresses those issues by allowing interconnect pitches below 10 micrometers, which lowers both resistance and capacitance and improves overall signal integrity. SK hynix has taken a different path. The company is enhancing its molded reflow underfill (MR‑MUF) process to produce 16‑Hi HBM4 stacks that comply with JEDEC's maximum height requirement of 775 micrometers. The company believes that if its advanced MR‑MUF technique can achieve performance on par with hybrid bonding, they will avoid the substantial capital investment needed for the specialized equipment that true 3D copper bonding requires. The cost and space demands of hybrid bonding equipment are significant. Specialized lithography and alignment tools occupy more clean‑room real estate, increasing capital expenditures. Samsung may mitigate some of these costs through Semes, its in‑house equipment subsidiary, but it remains uncertain whether Semes can deliver production‑ready hybrid bonding systems in time for mass production. If Samsung successfully qualifies its HBM4 stacks using hybrid bonding, which it plans to begin manufacturing in 2026, the company could gain a competitive edge over Micron and SK hynix.

In December, we reported that Intel's next‑generation Arc graphics cards, based on the Xe3 "Celestial" IP, are finished. Tom Petersen of Intel confirmed that the Xe3 IP is baked, meaning that basic media engines, Xe cores, XMX matrix engines, ray‑tracing engines, and other parts of the gaming GPU are already designed and most likely awaiting trial fabrication. Today, we learn that Intel has reached pre‑silicon validation, meaning that trial production is imminent. According to the X account @Haze2K1, which shared a snippet of Intel's milestones, a pre‑silicon hardware model of the Intel Arc Xe3 Celestial IP is being used to map out frequency and power usage in firmware. As a reminder, Intel's pre‑silicon validation platform enables OEM and IBV partners to boot and test new chip architectures months before any physical silicon is available, catching design issues much earlier in the development cycle.

Intel provides OEMs and IBVs access to a secure, cloud‑based environment that faithfully emulates hardware‑representative systems, allowing developers to validate firmware and software stacks from anywhere without the need for physical labs. Most likely, Intel is running massive emulations of hardware on FPGAs, which act as an ASIC chip—an Arc Xe3 GPU in this case. The pre‑silicon validation team is now optimizing the power‑frequency curve and the voltage in sleep, rest, and boost states, as well as their respective frequencies. With the Xe3 IP taking many forms, engineers are experimenting with every possible form factor, from mobile to discrete graphics. Additionally, data pathways depend on these frequency curves, which in turn rely on power states that allow voltage to spike up and down as the application requires. As this work is now complete, engineers are moving on to other areas for optimization, and once the silicon returns from volume production, it will be fully optimized. We expect the first trial of silicon soon, with volume production by the end of the year or in early 2026.

Intel is preparing to launch its first "Panther Lake" mobile processor later this year, but only one configuration will arrive in 2025. This SKU features four high-performance P-cores paired with eight E-cores, leaves out the lower-power efficiency cores, and packs four Xe3 GPU cores. With a 45 W TDP, it is clearly aimed at mainstream gaming laptops rather than ultralight notebooks. Panther Lake fills the gap left by "Lunar Lake" with a higher power envelope and a more performance-oriented design. Lunar Lake ranged from 17 W to 28 W, while Panther Lake's 45 W shows Intel is targeting users who need more sustained compute and graphics throughput. Rumors indicate additional Panther Lake variants will arrive in Q1 of 2026, when Intel plans to have more SKUs shipping to OEMs from volume production.

One such SKU is expected to feature 12 Xe3 GPU cores for premium thin-and-light laptops without discrete graphics. All of Panther Lake processors combine "Cougar Cove" performance cores with "Darkmont" efficiency cores, following Intel's hybrid approach introduced with "Meteor Lake". Intel's decision to stagger the rollout reflects supply chain considerations and product segmentation by power and graphics capability. Gaming laptops that can rely on integrated Xe3 graphics will welcome this 45 W chip, while other form factors may wait for next year's lower-power or ultralight 15 W models. Qualification with OEM partners should begin later this year, with laptop shipments expected by late Q4 2025. Until Intel shares more details on the rest of the Panther Lake lineup, much remains speculative.

A series of April leaks have suggested that Apple's mixed reality headset engineering team is concocting two distinct next-gen solutions. Mid-month, leakers shared alleged early shots of "Vision Air"-related connectors and external parts—hinting at a potential dark blue colorway. Combined with a selection of fairly legitimate-sounding predictions from a notorious industry watcher, so-called Vision Pro sequels are on the way. Apple's Chinese manufacturing partners are reportedly deep into mass production of crucial "Vision Pro 2" components. Mark Gurman's "Power On" newsletter has provided plenty of inside knowledge stories over the past couple of months—his latest article included a section dedicated to fresh VR/AR insights: "I reported earlier this month that Apple is full steam ahead on two new successors to the Vision Pro (2023): a lighter version at a cheaper price point, and a Mac-tethered model aimed at applications that need maximum responsiveness."

He continued: "all signs point to the lighter model arriving between the end of this year and the first half of 2026. Despite the first version selling poorly, the company isn't abandoning ship here. The main uncertainty is whether the lighter version will be considered a replacement for the Vision Pro or a cheaper alternative." In theory, Apple could test "more mainstream" gaming waters with an initial rollout of the claimed cheaper + lightweight "Vision Air" model—perhaps set to do battle with readily available rival devices; e.g. Meta's dominant Quest 3 range. A full-blown Vision Pro follow-up could launch later on in 2026—likely reserved for upper-crust customers, with an increased focus on productivity applications.

At the 2025 Shanghai Auto Show, Intel revealed its next-generation automotive system-on-chip lineup, unveiling two ambitious platforms, "Frisco Lake" and "Grizzly Lake". The company described these new designs as key steps toward fully software-driven vehicles, where much of the intelligence is handled by high-performance processors instead of dedicated hardware circuits. Intel said these chips would support advanced driver assistance and richer multimedia features. Intel's second generation Software Defined Vehicle, or SDV, Frisco Lake, is built on the upcoming "Panther Lake" architecture. The first volumes are expected in the first half of 2026, and TDP options will be among 20-65 W to meet different use cases. Intel says Frisco Lake will deliver ten times more AI performance and sixty-one percent better energy efficiency compared to the current Raptor Lake-based platform.

The new graphics block is based on the third-generation Xe architecture, known as "Celestial", replacing the older Battlemage design. Frisco Lake also supports twelve simultaneous camera inputs and up to two hundred and eighty audio channels. Linux kernel patch analysis also shows Frisco Lake cores are based on Panther Lake, confirming Intel's adaptation of its client CPUs for automotive use. Looking further ahead, Intel shared an early roadmap for its third-generation SDV platform, Grizzly Lake, which should arrive in the first half of 2027. Codenamed Monument Peak, these chips will use "Nova Lake" cores and may offer up to 32 efficiency-optimized cores along with an integrated Xe GPU capable of about seven TeraFLOPS. Additional features include support for six independent displays, twelve camera interfaces, and compliance with automotive safety standards.

TSMC today unveiled its next cutting-edge logic process technology, A14, at the Company's North America Technology Symposium. Representing a significant advancement from TSMC's industry-leading N2 process, A14 is designed to drive AI transformation forward by delivering faster computing and greater power efficiency. It is also expected to enhance smartphones by improving their on-board AI capabilities, making them even smarter. Planned to enter production in 2028, the current A14 development is progressing smoothly with yield performance ahead of schedule.

Compared with the N2 process, which is about to enter volume production later this year, A14 will offer up to 15% speed improvement at the same power, or up to 30% power reduction at the same speed, along with more than 20% increase in logic density. Leveraging the Company's experience in design-technology co-optimization for nanosheet transistor, TSMC is also evolving its TSMC NanoFlex standard cell architecture to NanoFlex Pro, enabling greater performance, power efficiency and design flexibility.

Fireshine Games is delighted to introduce Duskfade, an all-new 3D action-platformer inspired by classic platformers of times gone by, coming to the PlayStation 5 (PS5) system, Xbox Series X|S, and PC in 2026.

Embark on an unforgettable adventure as Zirian, a young workshop apprentice, as he sets out to restore time itself in a world enshrouded by eternal night. Shatter the shackles of time as you jump, swing, and slash through a vibrant clockpunk world, blending nostalgia with modern gameplay in this timeless love letter to action-platformer classics.

Rejoice, Gungeoneers! Kaliber has heard your prayers! Enter the Gungeon 2 is in active development and will be coming to PC (Steam) and Nintendo Switch 2 in 2026. You can wishlist it now, even if you don't own a PC. Enter the Gungeon 2 is a reloaded, high-caliber sequel, enhanced with a new 3D art style, new weapons, new enemies, and expanded gameplay. Battle through familiar and unknown areas of the ruined Gungeon, uncovering secrets and mastering powerful weapons while destroying legions of Gundead, previously confined to the 2D plane. Choose from an expanding roster of Gungeoneers, new and old, rescue marooned heroes, and grow stronger through powerful passive and active items, blessings, curses, and your mastery of a vast arsenal of weapons.

And seek to understand why you find yourself under assault in the Gungeon once again…We're thrilled to finally reveal Enter the Gungeon 2—you've been asking for it for so long! But please note we're still in the midst of development, so we can't share too much just yet. In the meantime, we've set up an official Discord server for Dodge Roll, and we'd love to hear your thoughts on the announcement. Join to share your feedback, get updates directly from the team, enjoy giveaways, and hang out with other Gungeoneers.

Mark Gurman—Bloomberg's resident soothsayer of Apple inside track info—has disclosed predictive outlooks for next-generation M5 chip-based MacBooks. Early last month, we experienced the launch of the Northern Californian company's M4 MacBook Air series—starting at $999; also available in a refreshing metallic blue finish. The latest iteration of Apple's signature "extra slim" notebook family arrived with decent performance figures. As per usual, press and community attention has turned to a potential successor. Gurman's (March 30) Power On newsletter posited that engineers are already working on M5-powered super slim sequels—he believes that these offerings will arrive early next year, potentially reusing the current generation's 15-inch and 13-inch fanless chassis designs.

In a mid-February predictive report, Gurman theorized that Apple was planning a major overhaul of the MacBook Pro design. A radical reimagining of the long-running notebook series—that reportedly utilizes M6 chipsets and OLED panels—is a distant prospect; perhaps later on in 2026. The Cupertino-headquartered megacorp is expected to stick with its traditional release cadence, so 2025's "M5" refresh of MacBook Pro models could trickle out by October. Insiders believe that Apple will reuse existing MacBook Pro shells—the last major redesign occurred back in 2021. According to early February reportage, mass production of the much-rumored M5 chip started at some point earlier in the year. Industry moles posit that a 3 nm (N3P) node process was on the order books, chez TSMC foundries.

Intel's freshly concluded Vision 2025 "Products Update and GTM" showcase included a segment dedicated to forthcoming Core Ultra 300 "Panther Lake" client processors. Industry watchdogs have grabbed a select few screenshots from Team Blue's broadcast from Las Vegas, Nevada—one backdropped slide confirms that Intel's next-generation mobile CPU series will launch in 2026. This information mirrors the company's Chinese office presenting of an AI PC roadmap—coverage of last month's event highlighted a scheduled first quarter 2026 "volume" arrival of "Core Ultra Next-gen Panther Lake (18A)."

Going back to early March, Intel leadership refuted online rumors of "Panther Lake" mobile CPUs being delayed into 2026, due to alleged problems encountered during the development of the Foundry service's 18A process node. An interviewed executive repeatedly insisted that his firm's brand-new series was on track for release within the second half of 2025. Fast-forward to the end of last week; Lip-Bu Tan expressed a similar outlook in a letter addressed to investors. The newly-established boss stated: "we will further enhance our (leadership) position in the second half of this year with the launch of Panther Lake, our lead product on Intel 18A, followed by Nova Lake in 2026." Industry insiders propose that the Core Ultra 300 series will become available in a very limited capacity come October, via an Early Enablement Program (EEP). Returning to this week—Jim Johnson, senior vice president of the firm's Client Computing Group, informed a watchful audience about the merits of his group's design: "I'm personally excited about Panther Lake because it combines the power efficiency of Lunar Lake, the performance of Arrow Lake, and is built to scale 18A and is on track for production later this year...Our client roadmap is the most innovative we've ever had, and we are far from done."

In a letter to customers, Micron has announced upcoming memory price increases extending through 2025 and 2026, citing persistent supply constraints coupled with accelerating demand across its product portfolio. The manufacturer points to significant demand growth in DRAM, NAND flash, and high-bandwidth memory (HBM) segments as key drivers behind the pricing strategy. The memory market is rebounding from a prolonged oversupply cycle that previously depressed revenues industry-wide. Strategic production capacity reductions implemented by major suppliers have contributed to price stabilization and subsequent increases over the past twelve months. This pricing trajectory is expected to continue as data center operators, AI deployments, and consumer electronics manufacturers compete for limited memory allocation.

In communications to channel partners, Micron emphasized AI and HPC requirements as critical factors necessitating the price adjustments. The company has requested detailed forecast submissions from partners to optimize production planning and supply chain stability during the constrained market period. With its pricing announcement, Micron disclosed a $7 billion investment in a Singapore-based HBM assembly facility. The plant will begin operations in 2026 and will focus on HBM3E, HBM4, and HBM4E production—advanced memory technologies essential for next-generation AI accelerators and high-performance computing applications from NVIDIA, AMD, Intel, and other companies. The price increases could have cascading effects across the AI and GPU sector, potentially raising costs for products ranging from consumer gaming systems to enterprise data infrastructure. We are monitoring how these adjustments will impact hardware refresh cycles and technology adoption rates as manufacturers pass incremental costs to end customers.