Digital Chat Station (DCS)—a dedicated watcher of futuristic smartphone chip developments—has returned to a favorite topic: Qualcomm's rumored "Snapdragon 8 Elite Gen 2" mobile chipset. The tenured technological soothsayer disclosed compelling "SM8850" details over a month ago; mostly focusing on key next-gen upgrades. His latest bulletin reiterates many past claims, but a new proposition points to a significant bump in onboard AI-crunching capabilities. DCS's latest dose of inside track knowledge points to the Gen 2 chip's NPU computing power being bumped up "to 100 TOPS."

At the tail end of their bulletin, DCS mentioned an interesting new feature: "(the SM8850) chip natively supports hardware-level sunlight screen; display brightness of new devices will be greatly improved, and the native-level super frame will be further improved." In a separate post, DCS hinted about a forthcoming "Snapdragon 8 flagship chip-powered" smartphone that will make use of a "new silicon" 7800 mAh capacity battery. Commenters have linked OnePlus to this development—Chinese electronics firms seem to be ahead of mainstream South Korean rivals, with their formulations of silicon-carbon battery technology. DCS's freshest theory did not place the cutting-edge "Snapdragon 8 Elite Gen 2" chip alongside a super high-capacity power cell, but examples of this potent combination could arrive later this year.

Late last month, Kurnal (@Kurnalsalts) shared a partial die shot of a supposed Nintendo Switch 2 chipset—this teaser image seemed to verify previous leaked claims about the forthcoming next-gen hybrid gaming console being powered by a custom NVIDIA "T239" SoC design. Two weeks after the fact, Kurnal has boasted about delivering an alleged "world's first Nintendo Switch 2 die shot." Their social media post included a couple of key specification data points: "Samsung 8N (8 nm), eight Cortex-A78C cores, (shared) 4 MB L2 cache, and 1536 CUDA/6TPC 'Ampere' GPU." Another leaker—Geekerwan—said that they acquired a "Switch 2 motherboard" via Xianyu. This Chinese equivalent to eBay seems to be a veritable treasure trove of tech curiosities.

Earlier on in 2025, black market sellers were attempting to offload complete pre-launch Switch 2 packages for big money. As reported by VideoCardz, recent acquisitions only involved the securing of non-functional motherboard + SoC units—Kurnal disclosed a 1000 RMB (~$138 USD) price point. Digital Foundry's Richard Leadbetter is a very visible advocate of the Switch 2 chipset being based on a mature 8 nm Samsung node process. His personal belief was aimed at certain critics; these opposers predicted 5 nm manufacturing origins. Older leaks suggested a larger than expected die footprint—relative to Switch 1's internal setup; almost twice the size—leading to Leadbetter's conclusion. Comparison charts—produced by Kurnal and Geekerwan—propose an occupied area of 207 mm².

AMD today announced financial results for the first quarter of 2025. First quarter revenue was $7.4 billion, gross margin was 50%, operating income was $806 million, net income was $709 million and diluted earnings per share was $0.44. On a non-GAAP(*) basis, gross margin was 54%, operating income was $1.8 billion, net income was $1.6 billion and diluted earnings per share was $0.96.

"We delivered an outstanding start to 2025 as year-over-year growth accelerated for the fourth consecutive quarter driven by strength in our core businesses and expanding data center and AI momentum," said Dr. Lisa Su, AMD chair and CEO. "Despite the dynamic macro and regulatory environment, our first quarter results and second quarter outlook highlight the strength of our differentiated product portfolio and consistent execution positioning us well for strong growth in 2025."

Around late April, MediaTek confirmed that their CEO—Dr. Rick Tsai—will be delivering a big keynote speech—on May 20—at this month's Computex 2025 trade show. The company's preamble focuses on their "driving of AI innovation—from edge to cloud," but industry moles propose a surprise new product introduction during proceedings. MediaTek and NVIDIA have collaborated on a number of projects; the most visible being automative solutions. Late last year, intriguing Arm-based rumors emerged online—with Team Green allegedly working on a first time attempt at breaking into the high-end CPU consumer market segment; perhaps with the leveraging of "Blackwell" GPU architecture. MediaTek was reportedly placed in the equation, due to expertise accumulated from their devising of modern Dimensity "big core" mobile processor designs. At the start of 2025, data miners presented evidence of Lenovo seeking new engineering talent. Their job description mentioned a mysterious NVIDIA "N1x" SoC.

Further conjecture painted a fanciful picture of forthcoming "high-end N1x and mid-tier N1 (non-X)" models—with potential flagship devices launching later on this year. According to ComputerBase.de, an unannounced "GB10" PC chip could be the result of NVIDIA and MediaTek's rumored "AI PC" joint venture. Yesterday's news article divulged: "currently (this) product (can be) found in NVIDIA DGX Spark (platforms), and similarly equipped partner solutions. The systems, available starting at $3000, are aimed at AI developers who can test LLMs locally before moving them to the data center. The chip combines a 'Blackwell' GPU with a 'Grace' Arm CPU (in order) to create an SoC with 128 GB LPDDR5X, and a 1 TB or 4 TB SSD. The 'GB10' offers a GPU with one petaflop of FP4 performance (with sparsity)." ComputerBase reckons that the integrated graphics solution makes use of familiar properties—namely "5th-generation Tensor Cores and 4th-generation RT Cores"—from GeForce RTX 50-series graphics cards. When discussing the design's "Grace CPU" setup, the publication's report outlined a total provision of: "20 Arm cores, including 10 Cortex-X925 and 10 Cortex-A725. The whole thing sits on a board measuring around 150 × 150 mm—for comparison: the classic NUC board format is 104 × 101 mm."

Die shots of Intel's "Arrow Lake" desktop processors have appeared online, confirming the chiplet design we have known about since the launch. The images annotated by the YouTube channel HighYield show a four‑tile arrangement mounted on a base die made with Intel's 22 nm FinFET process. The compute tile sits at the top left, built on TSMC's N3B node and covering 117.24 mm². To its right are the SoC tile on TSMC's N6 node measuring 86.65 mm², and the GPU tile, which houses four Xe cores alongside an Arc Alchemist render slice. The I/O tile, at 24.48 mm² on the same N6 node, completes the group at the bottom left. Intel has redesigned its hybrid core layout for Arrow Lake, moving away from separate P‑core and E‑core clusters. Four of the eight high‑performance P‑cores line the die's outer edges, with the remaining four in the center. In between these lie the four efficiency E‑core clusters, each sharing 3 MB of L2 cache. A unified 36 MB L3 cache ring bus connects to every core, allowing E‑cores to tap into that larger cache pool for the first time. Intel aims to spread heat more evenly and boost background task performance.

The I/O tile integrates Thunderbolt 4 controllers, PCIe buffers and PHYs. The SoC tile carries display engines, media accelerators and DDR5 memory controllers. All tiles are bonded to the base die via Intel's Foveros Omni stacking technology. Arrow Lake also reflects a shift in Intel's manufacturing strategy. Plans to use Intel's 20A node were dropped in favor of TSMC processes, making this the first desktop CPU from Intel that relies almost entirely on external foundries. On the software side, Intel has begun offering its IPO profiles in select prebuilt systems. These presets optimize CPU and memory settings for a hassle‑free performance boost that remains within warranty limits. Meanwhile, the native 200S Boost overclocking option is rolling out via BIOS updates. Early tests suggest that 200S Boost alone yields modest gains unless paired with very high-speed DDR5 modules, while IPO profiles deliver more consistent improvements with mainstream memory configurations.

Mid-way through April, a few Asian media outlets proposed a fairly recent formation of Xiaomi's "chip platform department"—most likely operating as part of the Chinese corporation's mobile phone development operation. Industry insiders claimed that this special branch was tasked with the designing of "Xuanjie" chipsets, with added expertise provided by an ex-Qualcomm marketing director. Weeks later, Jukanlosreve has weighed in with alleged new details. The keen tracker—of unannounced flagship smartphone chips and semiconductor business revelations—believes that previous leaks were of merit, but made some corrections.

Given reported greater than expected "new division" headcounts, Xiaomi probably established its "Xring SoC" team a while ago—on this topic, Jukanlosreve divulged: "it operates as a new company; independent of the original parent firm. It's not a small team either—it has over 1000 people. To be honest, I see it as a positive development if a domestically produced chip gets used in a domestically made smartphone and sold globally. I genuinely hope it becomes reality. If Xring succeeds, it might encourage more companies to get involved, and even engineers currently working at major firms could see better pay opportunities."

Espressif Systems announced ESP32-C5, the industry's first RISC-V SoC that supports 2.4 GHz and 5 GHz dual-band Wi-Fi 6, along with Bluetooth 5 (LE) and IEEE 802.15.4 (Zigbee, Thread) connectivity. Today, we are glad to announce that ESP32-C5 is now in mass production.

ESP32-C5 is designed for applications that require high-efficiency, low-latency wireless transmission. ESP32-C5 has a 32-bit single-core processor which can clock up to 240 MHz in speed. It has a 384 KB on-chip SRAM along with external PSRAM support, 320 KB of ROM. It has up to 29 programmable GPIOs, supporting all the commonly used peripherals, high speed interfaces like SDIO, QSPI, and the best-in-class security features. The ESP32-C5 also includes an LP-CPU running up to 40 MHz which can act as the main processor for power sensitive applications. To learn more about the various capabilities and features of this MCU, please visit our website.

Yesterday, Chosun Daily published a news report that alleges a key "Galaxy Z Flip 7-related" decision made by Samsung leadership. According to smartphone industry moles, the oft-leaked/rumored "Exynos 2500" chipset destined to debut in the company's next-gen (horizontal) foldable smartphone design. As stated in the South Korean insider article: "this is the first time that Samsung's own mobile application processor (AP) is being installed in a foldable phone." Prior to 2025, Galaxy Flip Z product lines made use of Qualcomm Snapdragon chipsets. Throughout early 2025, leaks have linked the "troubled" Exynos 2500 mobile processor to futuristic Galaxy Z Flip 7, Fold 7, and affordable "FE" Enterprise Edition models. The emergence of a superior 2 nm "Exynos 2600" flagship chip—apparently tailored for Galaxy S26 devices (2026)—has allegedly relegated the lesser SoC into lower leagues.

Semiconductor industry watchdogs reckon that the "Exynos 2500" will be manufactured via Samsung Foundry's own 3 nm GAA node process (aka SF3). Notebookcheck commented on this odd choice: "industry estimates from earlier suggested (SF3) yields were around 40%, making it less than ideal for mass production. But it seems Samsung decided to proceed anyway to save on costs, and likely give a new lease of life to its struggling foundry business." Jukanlosreve followed up with additional inside knowledge, just after the publication of Chosun Daily's news piece. The keen tracker of foundry-related revelations let slip with this observation: "the Exynos 2500 being used in the Flip 7 is said to be a lower-clocked chip due to its low yield. So it might as well be called the E2500E." Samsung is expected to unveil its Galaxy Z Flip 7 smartphone family during an "Unpacked" July event. Experts believe that Foundry employees will accumulate useful experience from the mass production of 3 nm parts; thus leading to improved output of finalized 2 nm (SF2) production lines.

Siemens Digital Industries Software today announced that its continued collaboration with Intel Foundry has resulted in multiple product certifications, updated foundry reference flows, and additional technology enablement leveraging the foundry's leading-edge technologies for next-generation integrated circuits (IC) and advanced packaging. Siemens is a founding partner of the Intel Foundry Accelerator Chiplet Alliance - enabling a new and compelling solution for 3D IC and chiplet offerings to a breadth of semiconductor market verticals.

Intel 18A Certification Achievements
Siemens' industry-leading Calibre nmPlatform tool is now certified for the latest Intel 18A production Process Design Kit (PDK). Intel 18A represents a significant technological leap forward, featuring innovative RibbonFET Gate-all-around transistors and the industry's first PowerVia backside power delivery. This Calibre certification allows mutual customers to continue leveraging the Calibre nmPlatform tool as their industry-standard sign-off solution with Intel Foundry's most advanced manufacturing process, accelerating time-to-market for next-generation chip designs.

Samsung Electronics today reported financial results for the first quarter ended March 31, 2025. The Company posted KRW 79.14 trillion in consolidated revenue, an all-time quarterly high, on the back of strong sales of flagship Galaxy S25 smartphones and high-value-added products. Operating profit increased to KRW 6.7 trillion despite headwinds for the DS Division, which experienced a decrease in quarterly revenue.

The Company has allocated its highest-ever annual R&D expenditure for 2024, and in the first quarter of this year, it has also increased its R&D expenditure by 16% compared to the same period last year, amounting to 9 trillion won. Despite the growing macroeconomic uncertainties due to recent global trade tensions and slowing global economic growth, making it difficult to predict future performance, the Company will continue to make various efforts to secure growth. Additionally, assuming that the uncertainties are diminished, it expects its performance to improve in the second half of the year.

Industry watchdogs have held the belief that Samsung's foundry business has lost several key clients due to alleged yield problems—the South Korean megacorp appears to be diligently working on major improvements with currently "in-progress" manufacturing processes; namely 2 nm GAA (aka SF2). Semiconductor industry insiders believe that TSMC is still leading the way with a recently completed trial run of their own 2 nm design, but rumors of elevated prices have reportedly upset certain important customers. According to a fresh Sedaily news article, Qualcomm has conducted negotiations with Samsung Foundry top brass—semiconductor industry moles claim that a "Snapdragon 8 Elite 2nd generation product" was the main topic of discussion. This next-gen flagship mobile chipset was previously linked to a 3 nm TSMC node, but newer rumors point to a possible spin-off that will utilize a "more advanced 2 nm process"—courtesy of Samsung Electronic's prime "Hwaseong S3" facility.

Sedaily and Jukanlosreve reckon that mass production will kick off at this cutting-edge early next year. Earlier today, Jukanlosreve added extra conjecture/context via a long social media bulletin: "the completed chips are expected to be integrated into Samsung Galaxy smartphones slated for launch in H2 2026. Design work is to finish in Q2 2025, after which mass-production preparations will begin and wafer runs will start in Q1 2026. Output is estimated at roughly 1,000 twelve-inch wafers per month. Given that Samsung's current 2 nm capacity is about 7,000 wafers/month, this project would utilize only around 15 % of its available capacity—suggesting this is a modest order rather than a large-scale win." These predictions have surprised many industry observers; Samsung leadership has seemingly tried to prioritize the in-house Exynos mobile processor designs within futuristic flagship Galaxy smartphone devices. Jukanlosreve reckons that the Samsung Foundry is keen to embrace any new "golden opportunities," given the operation's weakened track record across the past half decade. One unnamed insider posited: "this Qualcomm partnership could pave the way for orders from other big tech players." Sedaily sent a query to Samsung HQ, regarding the latest inside talk—a company spokesperson replied with: "we cannot confirm anything related to customer orders."

Synaptics Incorporated announced it has extended its Veros wireless portfolio with its first family of Wi-Fi 7 systems-on-chips (SoCs) tailored for the Internet of Things (IoT). Comprising the SYN4390 and SYN4384, the scalable offering supports bandwidths up to 320 MHz to deliver 5.8 Gbps peak speed and low latency. The triple-combo SoCs integrate Wi-Fi 7 with Bluetooth 6.0 and Zigbee/Thread, support Matter, and are designed to minimize system cost and power consumption. They target IoT applications requiring reliable performance-over-range for enhanced user experiences across use cases that include 8K video streaming, interactive gaming, security monitoring, immersive AR/VR, and home and automotive entertainment.

Wi-Fi 7's multi-link operation (MLO) allows the devices to send and receive a data stream using multiple frequency bands (2.4 GHz, 5 GHz, 6 GHz) simultaneously in support of low latency, reliable connections, and high throughput for real-time applications like video calls and gaming. Synaptics' architecture provides a power-efficient, cost-effective way to deliver the benefits of MLO.

M31 Technology Corporation (M31), a global provider of silicon intellectual property (IP), today announced that its eUSB2 PHY IP has achieved silicon-proven status on TSMC's 3 nm process and has successfully completed tape-out on TSMC's 2 nm process. As a member of TSMC Open Innovation Platform (OIP) IP Alliance since 2012, M31 has been honored with TSMC OIP Partner of the Year Award for seven consecutive years. In 2020, M31 pioneered its eUSB2 IP solution on the TSMC 7 nm process node, further solidifying its leadership in advanced interface IP development. Since then, M31 has steadily expanded its eUSB2 IP portfolio across TSMC's 5 nm, 3 nm, and most recently, 2 nm process technologies—closely aligning with TSMC's cutting-edge roadmap to accelerate the adoption of AI-enabled smart devices. Looking ahead, M31 is actively developing the next-generation eUSB2 Version 2.0 (eUSB2V2) PHY IP, with ongoing efforts focused on both TSMC's 3 nm and 2 nm process nodes.

Reinforcing its robustness and reliability on advanced nodes, M31's eUSB2 IP solutions have been widely adopted by leading global companies in high-end smartphone chipsets and AI-driven image processing applications. Building on this success, M31 is currently advancing the development of eUSB2V2 IP on TSMC's N3 and N2 process technologies - expanding its comprehensive eUSB2 portfolio to include eUSB2 V1, V2 PHY, and eUSB2 Repeater solutions. Leveraging the eUSB2 standard, eUSB2V2 enhances data transfer rates while maintaining a low-voltage interface and leveraging asymmetric bandwidth technology—allowing TX and RX to operate at different data rates. This significantly improves transmission efficiency, making it ideal for embedded applications such as AI edge computing, smart surveillance, and image processing chips. To accommodate diverse design needs, eUSB2V2 leverages and enhances the I/O architecture based on the eUSB2 standard, supporting data transfer speeds from 480 Mbps up to 4.8 Gbps. The solution delivers a comprehensive eUSB2 platform for high-end SoCs—optimizing power efficiency, performance and design flexibility, while maintaining full compatibility with legacy USB 2.0 devices.

An alleged partial close-up capture of the Nintendo Switch 2's chipset has leaked out; courtesy of Kurnal (@Kurnalsalts). This fresh leak is being hyped up as putting an end to all online debate regarding the upcoming hybrid console's technological underpinnings. Despite late 2024/early 2025 reports pointing to a custom NVIDIA "T239" SoC design, certain voices continued to produce conjecture about a more "cutting edge" solution. Surprisingly, Team Green's PR department did issue a statement about the Switch 2 being powered by: "a custom processor featuring an NVIDIA GPU with dedicated RT Cores and Tensor Cores for stunning visuals and AI-driven enhancements."

As expected, Nintendo staffers remained guarded during recent press junkets—in-depth tech talk was deferred in NVIDIA's general direction. Kurnal's sharing of a speculative "T239" partial die shot does not provide any major new revelations or insights—as discussed on the Nintendo Switch 2 Subreddit, tech enthusiasts continue to rely on specification details from the big hack of NVIDIA repositories (three years ago). Newer speculation has focused on Nintendo's choice of foundry—Digital Foundry's Richard Leadbetter continues to express his personal belief that Nintendo has selected a Samsung 8 nm DUV foundry node. In opposition, certain critics have persisted with a 5 nm EUV node process theory.

PlayStation 5 Pro console—the most innovative PlayStation console to date—elevates gaming experiences to the next level with features like upgraded GPU, advanced ray tracing, and PlayStation Spectral Super Resolution (PSSR) - an AI-driven upscaling that delivers super sharp image clarity with high framerate gameplay. Today we're providing a closer look at the console's internal architecture, as Sony Interactive Entertainment engineers Shinya Tsuchida, PS5 Pro Mechanical Design Lead and Shinya Hiromitsu, PS5 Pro Electrical Design Lead, provide a deep-dive into the console's innovative technology and design philosophy.

Note: in this article, we refer to the PlayStation 5 model released in 2020 as the "original PS5," the PS5 released in 2023 as the "current PS5," and the PS5 Pro released in 2024 as the "PS5 Pro." Do not try this at home. Risk of fires, and exposure to electric shock or other injuries. Disassembling your console will invalidate your manufacturer's guarantee.

Based on recent shipping manifests that point to custom test hardware for its next "Nova Lake‑S" processors, Intel seems to be gearing up for a big desktop platform update. According to documents obtained by NBD.ltd, Intel isn't moving full motherboards yet. Instead, it's sending out mechanical interposers and re-balling jigs for an 888‑ball BGA chip. Those tools, likely meant for the upcoming 900‑series PCH, aren't finished products but specialized fixtures used to check voltage regulation during assembly. Right now, desktop builders are tied to the LGA‑1700 socket, but Nova Lake‑S is expected to adopt LGA 1954, which offers 1,954 active lands (and possibly more than 2,000 total pads when you count debug pins). That boost in pin count could allow Intel to expand power delivery and I/O without compromise. Still, anyone holding out for Nova Lake‑S will have to wait. Intel plans to roll out "Arrow Lake Refresh" later this year, with Nova Lake‑S not arriving until 2026.

Under the "NVL‑S" codename, Nova Lake is said to combine two clusters of eight high‑performance "Coyote Cove" P‑cores with 16 "Arctic Wolf" E-cores, plus four ultra‑low‑power LPE cores in a separate SoC tile. That layout would create a 52‑core hybrid chip, though Intel engineers are reportedly still fine‑tuning the exact mix before tape‑out. The new south‑bridge package measures about 25 × 24 mm (around 600 mm²), slightly smaller than the 650 mm² footprint used by today's 800‑series chipsets. Shipping lists reveal jig sizes from roughly 38 × 28 × 6.97 mm up to 50 × 50 × 6.32 mm, which tells us multiple fixture types are being used in test labs around the world. Additionally, moving from LGA‑1851 to LGA‑1954 could hint at a longer‑lived socket, but Intel's history suggests most desktop platforms span just two generations. Whether Nova Lake‑S or any future "Razer Lake" follow‑up will fully exploit this new interface remains to be seen. We are watching closely as more concrete specs emerge ahead of that 2026 launch.

Last year, leakers posited that Xiaomi engineers were working on proprietary new-generation mobile chipset. The giant Chinese technology company has produced proprietary SoC designs in the past—most notably 2017's Pengpai/Surge S1 (blink, and you missed it)—but has largely relied on a wide swatch of Qualcomm solutions for deployment in smartphones. According to a fairly fresh ITHome news report (via a source at Sina Technology), Xiaomi has established a "chip platform department" under the umbrella of its mobile phone product development division. The exact nature of this newly-formed team remains semi-mysterious, and how it intermeshes with current (rumored) proprietary chip design efforts. The megacorporation's speculated "dedicated chip platform department" is said to be working on a "Xuanjie" SoC series.

Qin Muyun—a former senior director of product marketing at Qualcomm—is purported to be the new department's leader. Insiders believe that Muyun will answer directly to Xiaomi's CEO: Lei Jun. Over the past half decade, company engineers have accumulated chip designing experience in multiple lesser technology fields—ITHome lists: "imaging, fast charging, power management, communication, and display" aspects. Xiaomi leadership could be "shaking up" its first-party SoC development projects. Two weeks ago, rumors turned up online regarding a node process downgrade—from 3 nm to 4 nm. Smartphone industry watchdogs reckon that Xiaomi's forthcoming flagship chipset design will perform on the level of Qualcomm's first generation Snapdragon 8 mobile processor (from 2021).

Cadence today announced that it has entered into a definitive agreement with Arm to acquire Arm's Artisan foundation IP business, consisting of standard cell libraries, memory compilers, and general-purpose I/Os (GPIOs) optimized for advanced process nodes at the leading foundries. The transaction will augment Cadence's expanding design IP offerings, anchored by a leading portfolio of protocol and interface IP, memory interface IP, SerDes IP at the most advanced nodes, and embedded security IP from the pending Secure-IC acquisition.

By increasing its footprint in SoC designs, Cadence is reinforcing its commitment to continuously accelerate customers' time to market and to optimize their cost, power and performance on the world's leading foundry processes. Cadence will acquire the Arm Artisan foundation IP business through an asset purchase agreement with a concurrent technology license agreement, to be signed at closing and subject to any existing rights. As part of the transaction, Cadence will acquire a highly talented and experienced engineering team that is well respected in the industry and can help accelerate development of both related and new IP products.

Sony and Microsoft seem to be involved in the development of handheld gaming consoles, but insiders reckon that respective next-generation offerings will not directly compete with each other. Xbox and ASUS have signalled some sort of collaborative ROG Alloy-esque device; potentially releasing later on in 2025. Whispers of a futuristic PlayStation portable model's chipset design emerged mid-way through March; courtesy of Kepler_L2. The notorious leaker has recent history of reporting inside track knowledge of AMD CPU and GPU architectures/technologies. They alleged that Sony and Team Red's collaborative PS6 APU design project had reached a finalized stage of development, possibly around late 2024/early 2025. Returning to March/April events; Kepler_L2 theorized that a "PS6 Portable" would not be capable of surpassing PlayStation 5 (home console) level performance upon launch in 2028.

The mysterious handheld is said to be powered by a "15 W SoC" manufactured on a non-specific 3 nm node process. Elaborating further, they posit that PlayStation's rumored handheld is capable of running PS5 generation games—bandwidth and power restrictions could reduce resolution and frame rates below that of Sony's current-gen system. Kepler_L2 pictures "PS6 Portable" gaming performance being somewhere in-between Xbox Series S and PlayStation 5 (non-Pro). According to rumors, the handheld's chipset is not related or derived from the PS6 home console's internal setup. Kepler_L2 envisioned a mobile SoC with fewer than 40 compute units (CUs)—several media outlets have added their interpretation of this data point; with a sub-36 count. PlayStation 5's GPU aspect consists of 36 CUs, while the Xbox Series S graphics solution makes do with 20 units. Sony's speculated return to portable territories will be welcomed by owners of older handheld models—namely the Vita and PSP. Famously, these portable products struggled to keep up with competing Nintendo devices.

MediaTek today announced the Dimensity 9400+ SoC, the latest addition to MediaTek's Dimensity flagship chipset family. Providing exceptional Generative and agentic AI capabilities as well as other performance enhancements, the Dimensity 9400+ supports the latest Large Language Models (LLM) while sustaining a super power-efficient design. The Dimensity 9400+ features an All Big Core design, integrating one Arm Cortex-X925 core operating up to 3.73 GHz, combined with 3x Cortex-X4 and 4x Cortex-A720 cores. This powerful configuration accelerates single and multithreaded performance for top-tier Android UX experiences.

"The MediaTek Dimensity 9400+ will make it easier to deliver innovative, personalized AI experiences on-device, combined with enhanced overall performance to ensure your device can handle all tasks with ease," said JC Hsu, Corporate Senior Vice President at MediaTek. "We are working closely with developers and manufacturers to continue building a robust ecosystem of AI applications and other features that will bring a number of speed and privacy benefits to consumers."

Late last month, speculative Snapdragon 8 Elite Gen 2 (aka SM8850) technical details emerged online. Up until then, Digital Chat Station's Weibo channel has delivered all sorts of pre-release information—mostly concentrating on Qualcomm's alleged redeployment of a familiar "2 + 6" core configuration, and selection of TSMC's 3 nm "N3P" node process. Earlier today, the veteran leaker predicted a couple of new-gen improvements—first concentrating on the alleged mobile chipset's "Adreno 840" integrated graphics solution. Digital Chat Station (DCS) believes that the company's engineering team has increased their iGPU design's independent cache size "from 12 MB to 16 MB," leading to: "early setting performance increased by 30%±." It is not clear whether this rumored upgrade has affected the SoC's L2 or L3 cache provisions, but the current-gen Snapdragon 8 Elite mobile processor makes do with 12 MB of L2 cache per cluster. Additionally, DCS reckons that an enlargement of caches has resulted in performance of Qualcomm's "second-generation self-developed CPU architecture" increasing "by 25%±."

As interpreted by Wccftech: "the upcoming SoC will now feature 32 MB of L2 cache, with the L3 count currently unknown at this time. The initial test results revealed that the 'Snapdragon 8 Elite Gen 2' delivered a 30 percent performance increase, but it is unconfirmed if this delta exists between the Snapdragon 8 Elite or some other silicon." DCS has heard whispers about the upcoming chip supporting "new generations of high-speed LPDDR5X/LPDDR6" memory. The mentioning of LPDDR5X is not surprising; given that the current Snapdragon 8 Elite model is already up to snuff with this spec. Just over a year ago, JEDEC was reportedly working on the finalization of LPDDR6 standards for mobile platforms. Shortly thereafter, smartphone industry watchdogs started to theorize about the arrival of a so-called "Snapdragon 8 Gen 4" chip with LPDDR6 RAM in 2025. Fast-forward to the present day; fresh reports suggest that manufacturers will have the option to outfit next-gen flagship devices with "bog-standard" LPDDR5X or faster/more efficient LPDDR6 memory.

Three months ago, AMD unveiled its Ryzen Z2 APU series at CES 2025—purpose made for deployment in next-gen handheld gaming PCs. The officially announced flagship—Ryzen Z2 Extreme "Strix Point," utilizing Zen 5 and RDNA 3.5 technologies—was previously alluded to by leakers in late 2024; albeit with some curious claims regarding an "odd 3+5 core configuration." Last week, Hoang Anh Phu (@AnhPhuH) presented an alleged expanded lineup of Ryzen Z2 processors—headlined by a mysterious "Ryzen AI Z2 Extreme" SKU.

PC hardware watchdogs believe that this speculative variant will eventually arrive with an enabled XDNA 2 NPU (a first for the series); likely readied to take on Intel's Core Ultra 200V "Lunar Lake" processor family. MSI's Core Ultra 7 258V-powered Claw 8 AI+ and Claw 7 AI+ handhelds launched not too long ago, boasting all sorts of Microsoft Copilot+ capabilities. Mid-way through March, an Xbox executive introduced "Copilot for Gaming." Team Red and manufacturing partners are likely jumping onto this "AI gaming" bandwagon with the aforementioned "AI Ryzen Z2 Extreme" chip, as well as Phu's fanciful "Ryzen Z2 A" model. The latter could be a spin-off of AMD's vanilla Ryzen Z2 "Hawk Point" design, with a "switched on" XDNA NPU.

MediaTek has introduced the Kompanio Ultra, the latest milestone in AI-powered, high-performance Chromebooks. Leveraging MediaTek's proven expertise in flagship innovation, this powerful new platform brings fantastic on-device AI capabilities, superior computing performance, and industry-leading power efficiency to the newest Chromebook Plus devices. "The Kompanio Ultra underscores our commitment to delivering groundbreaking computing performance and efficiency that MediaTek has shown as a leader in the mobile compute space for many years," said Adam King, Vice President & General Manager of Computing and Multimedia Business at MediaTek. "We worked closely with Google to ensure the newest Chromebook Plus devices enjoy next-generation on-device AI capabilities, superior performance per watt, and immersive multimedia."

The Kompanio Ultra is MediaTek's most powerful Chromebook processor to date, integrating 50 TOPS of AI processing power to enable on-device generative AI experiences. With MediaTek's 8th-generation NPU, users can expect real-time task automation, personalized computing, and seamless AI-enhanced workflows—with local processing for enhanced speed, security, efficiency, and support for AI workloads without an internet connection. Built on the cutting-edge (TSMC) 3 nm process, the Kompanio Ultra features an all-big-core CPU architecture with an Arm Cortex-X925 processor clocked at up to 3.62 GHz, delivering industry-leading single and multithreaded performance. Whether handling intensive applications like video editing, content creation, or high-resolution gaming, this processor ensures smooth, lag-free performance with unmatched multitasking capabilities.

As expected, Nintendo's lengthy Switch 2 presentation contained very little technical information—the upcoming hybrid console's feature set, software library and user experience were showcased extensively. A series of leaks and plenty of online speculation—going back to earlier in the decade—pointed to the highly-anticipated Switch successor being based on an NVIDIA hardware foundation. A mysterious "Tegra 239" chipset emerged as the "logical" choice for Nintendo's next-gen system, but company representatives will likely not comment on the exact nature of internal components. Several months after the launch of Wii U, independent analysis (by Chipworks) of the host console's "Latte" GPU core verified a Radeon 4650/4670-class design. To the surprise of many industry watchdogs, a Nintendo employee has officially confirmed Switch 2's support of NVIDIA graphics technologies.

As disclosed to IGN—during a press junket—Takuhiro Dohta (senior director of the firm's Planning & Development Division) stated: "we use DLSS upscaling technology and that's something that we need to use as we develop games. And when it comes to the hardware, it is able to output to a TV at a maximum of 4K. Whether the software developer is going to use that as a native resolution, or get it to upscale is something that the software developer can choose. I think it opens up a lot of options for the software developer to choose from. Yes, the GPU does support ray tracing. As with DLSS, I believe this provides yet another option for the software developers to use and a tool for them." When pressed about the exact origins of the console's beating heart, Dohta deflected responsibility in the direction of Team Green: "Nintendo doesn't share too much on the hardware spec...What we really like to focus on is the value that we can provide to our consumers. But I do believe that our partner—NVIDIA—will be sharing some information." As pointed out by VideoCardz, Nintendo's hardware technical manager only mentioned options for the development side of things, not end user features. Yesterday's Metroid Prime 4: Beyond preview segment indicated that the title's Switch 2 Edition will arrive with four profiles; VideoCardz theorizes that DLSS will be used for differing levels—quality/performance—in handheld or docked operation.

Mark Gurman—Bloomberg's resident soothsayer of Apple inside track info—has disclosed predictive outlooks for next-generation M5 chip-based MacBooks. Early last month, we experienced the launch of the Northern Californian company's M4 MacBook Air series—starting at $999; also available in a refreshing metallic blue finish. The latest iteration of Apple's signature "extra slim" notebook family arrived with decent performance figures. As per usual, press and community attention has turned to a potential successor. Gurman's (March 30) Power On newsletter posited that engineers are already working on M5-powered super slim sequels—he believes that these offerings will arrive early next year, potentially reusing the current generation's 15-inch and 13-inch fanless chassis designs.

In a mid-February predictive report, Gurman theorized that Apple was planning a major overhaul of the MacBook Pro design. A radical reimagining of the long-running notebook series—that reportedly utilizes M6 chipsets and OLED panels—is a distant prospect; perhaps later on in 2026. The Cupertino-headquartered megacorp is expected to stick with its traditional release cadence, so 2025's "M5" refresh of MacBook Pro models could trickle out by October. Insiders believe that Apple will reuse existing MacBook Pro shells—the last major redesign occurred back in 2021. According to early February reportage, mass production of the much-rumored M5 chip started at some point earlier in the year. Industry moles posit that a 3 nm (N3P) node process was on the order books, chez TSMC foundries.