Apple is preparing to release a major update for its Vision Pro headset before the end of the year. Inside, the current M2 chip will be replaced by the newer M4 SoC, built on a 3 nm process from TSMC. That extra shrink brings noticeably better CPU and GPU performance and a more capable neural engine, so you'll see smoother AI-powered features right on the headset. Apple hasn't stopped there, listening to early adopters and revamping the headband with softer padding and better balance to shift weight away from your face. At roughly 600 to 650 grams, the Vision Pro can feel heavy after only a few minutes, and this change should make longer sessions feel much more comfortable.

Behind the scenes, Apple is also working on a wired model called N107 for users who need rock-solid, low-latency connections to a Mac. Consider surgical training or complex CAD design, where even the slightest delay is unacceptable. If you're looking for something lighter and more affordable, Apple has that covered as well. A completely new Vision Pro, under the code name N100, is slated for 2027. By using slimmer lenses and lighter materials, it should shed several hundred grams without skimping on screen clarity or battery life. We expect to hear more about it as the Vision Pro 2 launch gets closer.

Cadence today announced the tapeout of the industry's first LPDDR6/5X memory IP system solution optimized to operate at 14.4 Gbps, up to 50% faster than the previous generation of LPDDR DRAM. The new Cadence LPDDR6/5X memory IP system solution is a key enabler for scaling up the AI infrastructure to accommodate the memory bandwidth and capacity demands of next-generation AI LLMs, agentic AI and other compute-heavy workloads for various verticals. Multiple engagements are currently underway with leading AI, high-performance computing (HPC) and data center customers.

The Cadence IP for the JEDEC LPDDR6/5X standard consists of an advanced PHY architecture and a high-performance controller designed to maximize power, performance and area (PPA) while supporting both LPDDR6 and LPDDR5X DRAM protocols for optimal flexibility. The solution supports native integration into traditional monolithic SoCs as well as multi-die system architectures by leveraging the Cadence chiplet framework, enabling heterogeneous chiplet integration. The chiplet framework, including the previous LPDDR generation, was successfully taped out in 2024.

AMD's openSIL project, a solution for open CPU silicon initialization code aimed at replacing traditional AGESA, has reached another milestone. Back in February, we reported on AMD promising full support for "Turin" and "Phoenix" server and client SoCs. The company initially targeted the end of 2024 for the release of proof-of-concept code, but failed to meet this deadline. A new target was subsequently set for the first half of 2025. As we roll into the second half, AMD openSIL now supports only the EPYC 9005 series Turin server processors, with Phoenix client SoCs still in development. AMD firmware engineers explained: "Currently, the Phoenix openSIL PoC release is still being worked on internally at AMD. We have encountered some delays in obtaining the necessary approvals to open-source the code, which has impacted our timeline. We are actively working to resolve these issues and are making every effort to expedite the process."

The path towards a fully open-source silicon initialization code is difficult, as it can expose many microarchitectural details. These are usually closely protected, as IP from Zen cores is valuable. An AMD engineer also added, "We understand the importance of this project to the open-source community and are committed to delivering it as promised." Nonetheless, the primary goal remains achieving full production readiness with the upcoming Zen 6 architecture. The openSIL project promises to enhance Coreboot support and provide developers with full access to low-level system components.

Intel's next-generation "Oak Stream" platform is preparing to accommodate the upcoming "Diamond Rapids" Xeon CPU generation, and we are receiving more interesting details about the top-end configurations Intel will offer. According to the HEPiX TechWatch working group, the Diamond Rapids Intel Xeon 7 will feature up to 192 P-cores in the top-end SKU, split across four 48-core tiles. Intel has dedicated two primary SKU separators, where some models use eight-channel DDR5 memory, and the top SKUs will arrive with 16-channel DDR5 memory. Using MRDIMM Gen 2 for memory will enable Intel to push transfer rates to 12,800 MT/s per DIMM, providing massive bandwidth across 16 channels and keeping the "Panther Cove" cores busy with sufficient data. Intel planned the SoC to reach up to 500 W in a single socket.

As one of the first mass-produced 18A node products, Diamond Rapids will be the first to support Intel's APX, also featuring numerous improvements to the efficiency of AMX. Intel also plans to embed native support for more floating-point number formats, such as NVIDIA's TF32, and lower-precision FP8. As most of the world's inference is good enough to run on a CPU, Intel aims to accelerate basic inference operations for smaller models, enabling power users to run advanced workloads on CPUs alone. With a 1S, 2S, and 4S LGA 9324 configuration, Diamond Rapids will offer 768 cores in a single server rack, with a power usage of only 2000 W. Supporting external accelerators will be provided via the PCIe Gen 6 connector. Scheduled for arrival in 2026, Intel could time the launch to coincide with its upcoming "Jaguar Shores" AI accelerators, making a perfect pair for a complete AI system.

Primemas Inc., a fabless semiconductor company specializing in chiplet-based SoC solutions through its Hublet architecture, today announced the availability of customer samples of the world's first Compute Express Link (CXL) memory 3.0 controller. Primemas has been delivering engineering samples and development boards to select strategic customers and partners, who have played a key role in validating the performance and capabilities of Hublet compared to alternative CXL controllers. Building on this successful early engagement, Primemas is now pleased to announce that Hublet product samples are ready for shipment to memory vendors, customers, and ecosystem partners.

While conventional CXL memory expansion controllers are limited by fixed form factors and capped DRAM capacities, Primemas leverages cutting-edge chiplet technology to deliver unmatched scalability and modularity. At the core of this innovation is the Hublet—a versatile building block that enables a wide variety of configurations.

Next-generation consumer and automotive audio is becoming increasingly sophisticated, and market drivers such as generative AI-based audio processing, immersive soundscapes, and advanced infotainment in software-defined vehicles demand stepped-up audio DSP performance. However, a single DSP can no longer meet escalating compute needs, while multiple DSPs pose significant programming challenges.

Today, OEMs and SoC vendors must perform all multicore hardware design and software development on their own while facing increased time-to-market pressures. At the same time, programmers are grappling with the complexity of software-based synchronization of shared memory regions and the proper partitioning of tasks across the multicore cluster. This can result in designs falling short of performance expectations.

In a market reshaped by the compute demands of AI, Arteris, Inc. (Nasdaq: AIP), a leading provider of system IP for accelerating semiconductor creation, today announced an expansion of its multi-die solution, delivering a foundational technology for rapid chiplet-based innovation. "In the chiplet era, the need for computational power increasingly exceeds what is available by traditional monolithic die designs," said K. Charles Janac, president and CEO of Arteris. "Arteris is leading the transition into the chiplet era with standards-based, automated and silicon-proven solutions that enable seamless integration across IP cores, chiplets, and SoCs."

Moore's Law, predicting the doubling of transistor count on a chip every two years, is slowing down. As the semiconductor industry accelerates efforts to increase performance and efficiency, especially driven by AI workloads, architectural innovation through multi-die systems has become critical. Arteris' expanded multi-die solution addresses this shift with a suite of enhanced technologies that are purpose-built for scalable and faster time-to-silicon, high-performance computing, and automotive-grade mission-critical designs.

Synopsys, Inc. announced today its ongoing close collaboration with Samsung Foundry to power the next generation of designs for advanced edge AI, HPC, and AI applications. The collaboration between the companies is helping mutual customers achieve successful tape-outs of their complex designs using Synopsys' 3DIC Compiler and Samsung's advanced packaging technologies with fast turnaround time. Mutual customers can improve power, performance and area (PPA) with certified EDA flows for SF2P process, and minimize IP integration risk with the high-quality portfolio of IP on Samsung's most advanced process technologies.

"The adoption of Edge AI applications is driving the need for advancements in semiconductor technologies to enable complex computational tasks, improve efficiency, and expand AI capabilities across various industries and applications," said John Koeter, senior vice president for the Synopsys IP Group. "Together with Samsung Foundry, we're enabling the most advanced AI processors across a broad spectrum of use cases from high-performance AI inference engines for data centers to ultra-efficient Edge AI devices like cameras and drones, all optimized for development on sub-2 nm Samsung Foundry process technologies."

TrendForce's latest investigations reveal that 1Q25 revenue for the global IC design industry reached US$77.4 billion, marking a 6% QoQ increase and setting a new record high. This growth was fueled by early stocking ahead of new U.S. tariffs on electronics and the ongoing construction of AI data centers around the world, which sustained strong chip demand despite the traditional off-season.

NVIDIA remained the top-ranking IC design company, with Q1 revenue surging to $42.3 billion—up 12% QoQ and 72% YoY—thanks to increasing shipments of its new Blackwell platform. Although its H20 chip is constrained by updated U.S. export controls and is expected to incur losses in Q2, the higher-margin Blackwell is poised to replace the Hopper platform gradually, cushioning the financial impact.

AMD's Z2 series of processors for handheld gaming devices has been expanded with a pair of new chips, namely the Ryzen AI Z2 Extreme and the Ryzen Z2 A. From AMD's naming scheme, one would assume that the two are quite similar, but if you've kept track of AMD's Z2 product lineup, you're most likely already aware that there are some major differences between the three older SKUs and this time around, we get a further change at the low-end. The new top of the range chip, the Ryzen AI Z2 Extreme appears to be largely the same SoC as the older Ryzen Z2 Extreme, with the addition of a 50 TOPS NPU for AI tasks, which appears to be shared with many of AMD's mobile SoCs.

However, the new low-end entry, the Ryzen Z2 A appears to have more in common with the Steamdeck SoC, than any of the other Z2 chips. It sports a quad core, eight thread Zen 2 CPU, an RDNA 2 based GPU with a mere eight CUs and support for LPDDR5-6400 memory. On the plus side, it has a TDP range of 6-20 Watts, suggesting it would allow for better battery life, assuming devices based on it get a similar size battery as a handheld based on one of the higher-end Z2 SoCs. ASUS is using both of these chips in its two new ROG Ally handheld gaming devices, but Lenovo is expected to follow shortly with its own handheld devices.

Alphawave Semi, a global leader in high-speed connectivity and compute silicon for the world's technology infrastructure, announced the successful tape out of one of the industry's first UCIe IP subsystem on TSMC's N2 process, supporting 36G die-to-die data rates. The solution is fully integrated with TSMC's Chip-on-Wafer-on-Substrate (CoWoS ) advanced packaging technology, unlocking breakthrough bandwidth density and scalability for next-generation chiplet architectures.

This milestone builds on the recent release of the Alphawave Semi AI Platform, proving readiness to support the future of disaggregated SoCs and scale-up infrastructure for hyperscale AI and HPC workloads. With this tape-out, Alphawave Semi becomes one of the industry's first to enable UCIe connectivity on 2 nm nanosheet technology, marking a major step forward for the open chiplet ecosystem.

Nintendo's Switch 2 hybrid console is due to arrive at retail tomorrow (June 5), and pre-launch marketing campaigns are in full swing. The Japanese gaming giant has called in a high profile partner—Jensen Huang—to add some surprisingly technical heft during hype festivities. At this stage in time, NVIDIA's Tegra "T239" chipset is a well known quantity—thanks to years of leaked "internal info," and disabled examples turning up for close analysis in China. Industry experts did not anticipate Nintendo's fairly frank discussions that covered Switch 2's hardware capabilities. The Nintendo "Creator's Voice" video series has featured a number of high-profile third-party software development buddies (including CD Projekt RED), but yesterday's Team Green CEO contribution received widespread press attention.

Jensen paid tribute to Satoru Iwata, a former and much missed Nintendo president. Their collaboration started during the era of OG Switch development: "he wanted to create something no one had seen before. A console powerful enough for big, cinematic games—but small enough to take anywhere. It sounded impossible. But that vision became the original Nintendo Switch. We lost Iwata-san before the launch, but his clarity, his purpose, it still inspires our work every day. Together, we poured everything into that system." As mentioned back in April, NVIDIA dedicated significant resources into making their latest "technical marvel."

This year marks the 40th anniversary of the first commercially available field-programmable gate array (FPGA), introducing the idea of reprogrammable hardware. By creating "hardware as flexible as software," FPGA reprogrammable logic changed the face of semiconductor design. For the first time, developers could design a chip, and if specs or requirements changed mid-stream, or even after manufacturing, they could redefine its functionality to perform a different task. This flexibility enabled more rapid development of new chip designs, accelerating time to market for new products and providing an alternative to ASICs.

The impact on the market has been phenomenal. FPGAs launched a $10+ billion industry and over the past four decades we have shipped more than 3 billion FPGAs and adaptive SoCs (devices combining FPGA fabric with a system-on-chip and other processing engines) to more than 7,000 customers across diverse market segments. In fact, we've been the programmable logic market share leader for the past 25 consecutive years, and we believe we are well positioned for continued market leadership based on the strength of our product portfolio and roadmap.

During a recent Computex keynote presentation, Qualcomm announced the next edition of its Snapdragon Summit. This year's event will take place in Hawaii, starting on September 23 and concluding on the 25th. The company's 2024 new product showcase took place last October, so an earlier than expected scheduled follow-up has caused industry observers to raise a collective eyebrow. Insiders foresee an unveiling of Qualcomm's next-gen flagship notebook/slimline laptop processor; mid-April leaks produced a smattering of elevated (generational) performance numbers. Late last week, Roland Quandt weighed in with fresh pre-release theories: "SC8480XP aka SD X2 Elite in testing with 64 GB RAM... looking like (an) 18-core thing, more and more."

Not long ago, the tenured semiconductor industry watcher linked the alleged Snapdragon X2 Elite flagship chip to a SK Hynix 48 GB RAM and 1 TB SSD-equipped SiP (System-in-Package) test platform. Mid-March "import-export database records" pointed to early evaluations of 18-core processor designs. The very best current-gen Snapdragon X Elite SoC leverages a 12-core "Oryon" design. Additional murmurs have driven speculation about diversified Snapdragon X2 Elite chips; allegedly powering desktop applications. Q1'25 rumors suggested the existence of setups configured with 120 mm AIO cooling solutions.

NVIDIA plans to introduce its first Arm-based "N1/N1x" gaming SoC in Dell's Alienware laptops later this year or early 2026, according to Taiwanese reports. The SoC is being developed with MediaTek, combining an Arm-derived CPU core and NVIDIA's Blackwell GPU architecture. Early rumors suggest that NVIDIA's new SoC will operate within an 80 W to 120 W power range, positioning it among existing high-performance laptop chips. When Qualcomm entered the Arm-based laptop design market with its Snapdragon X-series, it faced challenges because many titles required emulation through Microsoft's Prism framework, leading to compatibility issues and lower frame rates on Arm-based Windows devices. NVIDIA plans to work closely with Microsoft and game developers to ensure that Arm compatibility is present from day one, so every Arm SoC maker will benefit.

Rumors of an Arm-centric NVIDIA chip first appeared in 2023, and recent leaks suggest an engineering prototype already exists. During an earnings presentation earlier this year, NVIDIA CEO Jensen Huang announced that the company plans to integrate Arm CPU blocks into AI-oriented hardware, specifically mentioning the Digits compute system. Dell's CEO, Michael Dell, also hinted at a future AI-capable PC collaboration with NVIDIA, fueling speculation that Alienware will be the first to use the new chip. Beyond gaming, the partnership with MediaTek could lead to broader Arm solutions for both desktops and mobile devices. MediaTek is reportedly working on its own Arm-based PC processors, and AMD is exploring Arm architectures for future Surface devices. NVIDIA's entry into this space could turn Dell's Alienware laptops into a practical testbed for high-performance Arm technology in a market long dominated by x86 workforce.

Three weeks ago, Kurnal and Geekerwan dived deep into Nintendo's alleged Switch 2 chipset. The very brave Chinese leakers are notorious for their acquiring of pre-release and early silicon samples. Last week, their collective attention turned to a brand-new Xiaomi mobile chip: the XRING 01. After months of insider murmurs and official teasers, the smartphone giant recently unveiled its proprietary flagship SoC. According to industry moles, Xiaomi has invested a lot of manpower into a special chip design entity—leadership likely wants to avoid a repeat of prior first-party developed disappointments. Despite rumors of disappointing prototype performance figures, mid-May Geekbench results pointed to the emergent XRING 01 mobile chip being up there with Qualcomm's dominant Snapdragon 8 Elite platform. Die shot analysis has confirmed Xiaomi's selection of a TSMC 3 nm "N3E" node process; also utilized by the latest Apple, Qualcomm and MediaTek flagships. Overall die size is 114.48 mm² (10.8 x 10.6 mm), with 109.5 mm² of used area; comparable to Apple's A18 Pro SoC footprint (refer to Geekerwan's comparison shot, below).

Unlike nearby rivals, the XRING 01 seems to not sport an integrated 5G modem. Notebookcheck surmised: "it is rumored to use an external radio from MediaTek. It isn't located on the actual die itself, and likely a contributing factor to why its size is so small." Annotations indicate the presence of off-the-shelf/licensed Arm CPU cores (ten in total): two Cortex-X925 units, four Cortex-A725 units, two Cortex-A725 units, and two Cortex-A520 units. Additionally, an Arm Immortalis-G925 MP16 iGPU was identified. A 6-core NPU—with 16 MB of cache—was highlighted, but it is not clear whether this is a proprietary effort or something bought in. Observers have noted the absence of SLC cache. GSMArena posited: "the Geekerwan team speculates that (Xiaomi's) omission of the SLC has hurt GPU efficiency—it's pretty fast, but it uses more power than the Dimensity GPU at peak performance. The more efficient CPU combined with the fact that the GPU rarely runs at full tilt makes for pretty good overall efficiency in real-life gaming tests." The XRING department's debut product is impressive, but industry watchdogs are looking forward to refined variants or full-fledged successors.

Last Thursday, Xiaomi revealed its proprietary XRING O1 3 nm mobile chipset. After months of rumors, the Chinese firm's highly anticipated first-party chip design was introduced during their special "A New Beginning" event—held in Beijing. During this multipronged product launch celebration, company leadership disclosed the underpinnings of their first-ever flagship processor. According to official descriptions, Xiaomi's pivotal XRING O1 SoC is built on: "a cutting-edge second-gen 3 nm process with 19 billion transistors, features a 10-core CPU and 16-core Immortalis-G925 GPU, delivering flagship performance with industry-leading power efficiency. It also integrates Xiaomi's fourth-gen ISP and a 6-core NPU offering 44 TOPS for advanced AI processing." Days prior to important ceremonies in China, a joint statement—issued by Qualcomm—detailed an extended Snapdragon chipset supply agreement. The XRING O1 processor line will drive forthcoming Xiaomi 15S Pro smartphones and Pad 7 Ultra tablets; reserved for initial "domestic market" launches. Qualcomm's current flagship offerings are technically superior to Xiaomi's fresh effort, but an ever-shifting political landscape could affect future shipments.

Lu Weibing—a company president and partner—has outlined a vision for XRING's eventual expansion beyond a flagship/high-end product tier. Last week's intro firmly positioned the 3 nm part as premium option that will power suitably expensive Android-based mobile devices. Weibing acknowledged that his team has jumped into the deep end: "(for) this platform capability, it is most difficult to work on smartphone flagship SoC, it has high power consumption demand and its technology is extremely complicated. If you can, then you should have the ability to work on flagship smartphone SoC. (Once you) move to work on other chips, it won't be that difficult." Industry moles posit that Xiaomi's XRING division is already a formidable force, in terms of staff headcounts and experience. The department could be absorbing some inspiration from Apple; namely their custom C1 modem chip. The firm's president painted a picture of things to come: "so we want to focus on the flagship SoC, and then we want to make a capable modem for the future. We have to work on 4G and 5G parts—together with 3G—leading to a complete matrix. So that is what we need to do at this stage." Early leaks have indicated the existence of a binned version of the XRING O1 SoC; present within early Xiaomi Pad 7 Ultra tablet samples. In theory, these compromised chips could be deployed in unannounced cheaper products.

Qualcomm Technologies, Inc. and Xiaomi Corporation are celebrating 15 years of collaboration and have executed a multi-year agreement. The relationship between Qualcomm Technologies and Xiaomi has been pivotal in driving innovation across the technology industry and the companies are committed to delivering industry-leading products and solutions across various device categories globally.

"Qualcomm Technologies has always been one of Xiaomi's most trusted and vital partners, supporting our journey from a startup to a global technology leader. We look forward to continuing the next 15 years of our collaboration and leveraging Qualcomm's cutting-edge Snapdragon platforms and technologies to deliver even more innovative and high-quality products to our customers worldwide," said Lei Jun, CEO of Xiaomi.

Xsight Labs, a leading fabless semiconductor company providing end-to-end connectivity for next-generation hyperscale, edge and AI data center networks, today announced availability of its Arm -based E1-SoC for cloud and edge AI data centers. The E-Series is the only product of its kind to provide full control plane and data path programmability and is the industry's highest performance software-defined DPU (Data Processing Unit). Xsight Labs is taking orders now for its E1-SoC and the E1-Server, the first-to-market 800G DPU.

E1 is the first SoC in the E-Series, Xsight Labs' SDN (Software Defined Network) Infrastructure Processor product family of fully programmable network accelerators. Built on TSMC's advanced 5 nm process technology, the E1-SoC will begin shipping to customers and ecosystem partners.

Although Synology already announced its first plus series NAS in its 2025 range a month ago with the DS925+ and its accompanying expansion unit, the company had no less than six new devices on display at Computex. We also talked at length with the company and got an explanation as to why the company decided to move to supporting its own brand drives only and it turns out the situation isn't quite what Synology's press release made it seem like, but more on that after we go over the new devices.

The new range starts with the DS225+ and the DS425+, where the DS225+ is the new base model of the plus series. Both models are built around an Intel Celeron J4125—a chip that launched at the end of 2019—which is paired with 2 GB of DDR4 which can be expanded to 6 GB in total. Both models come with one 2.5 Gbps and one 1 Gbps Ethernet port, two 5 Gbps USB 3.2 Gen 1 ports and two or four drive bays. The DS425+ also gets a pair of M.2 2280 NVMe SSD slots, but unless the CPU information provided is wrong, these will only be PCIe 2.0 and will most likely not sport more than one or two lanes.

As previously promised, Dr. Rick Tsai took to the Computex 2025 stage earlier today. The MediaTek CEO's keynote speech included a teaser for next-gen. Currently, the fabless chip design firm's best offerings are manufactured at TSMC foundries—utilizing 3 nm node processes. According to inside track knowledge, the forthcoming Dimensity 9500 mobile chipset will be based on "N3P." During today's important presentation, Tsai announced his company's next major leap—with "2 nm silicon innovation." According to a presentation slide, a tape-out phase is anticipated by this September. Industry experts reckon that a futuristic flagship—perhaps "Dimensity 9600"—SoC will benefit from this generational jump. Finalized products could arrive around late 2026; with MediaTek reportedly being on TSMC's 2 nm (N2) mass production order books. Officially, MediaTek's shift from 3 nm into 2 nm is expected to improve chip performance—with an estimated 15% uplift—while reducing power consumption (by ~25%).

There's no shortage of AI products at Computex this year, but MaxLinear had a demo of a router with AI support that kind of makes sense. The company has developed what it simply calls MaxAI, which allows their customers to build their own smartphone all, which is represented by the the left hand side of the screen below. This allows the owner of a router with support for Max AI to give it voice commands, but as the software is aware of the features of the router, it's possible to use it for things like QoS optimisation, speed tests and even for sending system logs to your ISP during a support call. MaxAI is also multilingual, the demo we were shown started out in Mandarin, but was switched to English for the demo and then in the end switched to Japanese.

This might seem like something of a gimmicky feature, but keep in mind that most people don't know how to use a router, from setting it up, to changing any kind of settings. The potential of MaxAI is to allow users to set up their router via voice commands, which to many would be a lot easier, than using an app or logging in to a web interface. However, MaxAI isn't just about controlling your router via voice commands, as MaxLinear has also worked on a new type of QoS, where they don't do deep packet inspection, but instead have trained that AI model to detect patterns of different software. The demo was showing two video streams, one was used to simulate a teams call and by just telling the MaxAI to optimise teams, the video stream went from jerky to smooth. Obviously this assumes that the internet connection is fast enough and it's still just prioritisation, but it works much better compared to traditional QoS.

Yesterday, Lei Jun—the CEO of Xiaomi—finally introduced his firm's proprietary XRING 01 mobile chipset, via a couple of Weibo posts. In an initial afternoon short blog entry, the executive informed his followers with a happy unveiling: "I would like to share with you a piece of news: Xiaomi's self-developed and designed mobile phone SoC chip, named XRING 01, will be released in late May. Thank you for your support!" About a month ago, the company's oft-rumored return to in-house chip efforts was linked to a major corporate offshoot. The speculated "chip platform department" was likely established a while ago, given early May reports of the division's staff headcount exceeding 1000+. At the time, an "Xring" codename was mentioned by industry tipsters (in China).

In a follow-up "Weibo Text" bulletin, Xiaomi's head honcho recalled older project timelines and technological attempts: "even drinking ice for ten years can't cool your blood! Xiaomi's journey to making chips began in September 2014. Time flies, and more than ten years have passed in the blink of an eye...Figures 2 and 3 are photos of Xiaomi's first chip launch conference in February 2017." Jun's did not provide any hints about the XRING 01 chip's underpinnings. Late 2024 leaks alluded to a reportedly troubled prototype—insiders connected this design to fairly new Arm Cortex architecture, and a TSMC 4 nm "N4P" node process. The vast majority of Xiaomi's modern flagship smartphone devices utilize top-end Qualcomm Snapdragon chipsets. For example, the brand's latest Xiaomi Ultra 15 model is powered by the ubiquitous Snapdragon 8 Elite (Gen 4) platform.

Late last month, data miners unearthed a wide variety of unannounced AMD Ryzen processor IPs. A "Sound Wave" product category received less attention, but Team Red's curious codename has reemerged in the middle of May. Thanks to fresh Kepler L2 theorizations, this mysterious mobile APU family has a potential end destination. Leaks from 2024 suggested that company engineers were working on an unusual Arm-based processor branch. AMD is cozily well-versed in all things x86, but an alleged present day diversification—into Arm (x64) territories—has confounded a fair few industry watchdogs.

In a tangential conversation—forking off from speculative "Zen 6" and PlayStation 6 APU chatter—Kepler L2 reckons that Team Red "Sound Wave" chips will be deployed in 2026, possibly within a refreshed Microsoft Surface lineup. Current-gen Arm-based offerings—leveraging Qualcomm Snapdragon X processors—have generated mixed user impressions (press and public alike). Microsoft and Qualcomm's "Windows on Arm" (WoA) platform partnership was elevated earlier on in May (with cheaper options), but troublesome hardware-to-software compatibility issues have reportedly caused some rifts in this relationship. As of last week, evaluators seemed to be poking around with NVIDIA's rumored Arm-based "N1" chip series on Windows. In theory, AMD's futuristic "Sound Wave" designs could do battle with (claimed) Team Green and MediaTek collaborative efforts.

With the launch scheduled for June 5, Nintendo has quietly confirmed the final technical details for its next-generation hybrid console, the Switch 2, clarifying the specifications of the "custom NVIDIA processor" at its core and specifying exactly how much horsepower developers can access. The Switch 2's SoC is officially labeled the NVIDIA T239, a custom iteration of the Ampere architecture rather than a repurposed Tegra. It contains eight Arm Cortex‑A78C cores running a 64‑bit ARMv8 instruction set, with cryptography extensions enabled and no support for 32‑bit code. Each core features 64 KB of L1 instruction cache and 64 KB of L1 data cache. Six cores are available for game development, while two are reserved for system tasks. Clock speeds reach 998 MHz in handheld mode and 1,101 MHz when docked, and the CPU can theoretically burst to 1,700 MHz for demanding operations or future updates.

Graphics are powered by a full Ampere‑based GPU with 1,536 CUDA cores. Clock speeds top out at 1,007 MHz in docked mode and 561 MHz in handheld mode, delivering approximately 3.07 TeraFLOPS when docked and 1.71 TeraFLOPS in portable use. As with the CPU, a portion of GPU resources is allocated to operating system functions, slightly reducing the amount available for applications. Memory capacity has increased from 4 GB of LPDDR4 in the original Switch to 12 GB of LPDDR5X in the new model, split across two 6 GB modules. Peak bandwidth measures 102 GB/s docked and 68 GB/s handheld. Of the total, 3 GB are reserved for system functions and 9 GB are dedicated to games and applications. Nintendo has also introduced a dedicated File Decompression Engine for LZ4‑compressed data, offloading asset unpacking from the CPU to improve loading times without overheating the chipset. The console ships with 256 GB of UFS storage, expandable via microSD Express up to 2 TB, and features a 7.9‑inch, 1080p LCD that supports HDR10 and up to 120 Hz variable refresh rate in handheld mode. Although HDMI VRR is not yet available, the internal display fully supports it.