Apple recently launched the iPhone 16 Pro and Pro Max with the company's new A18 Pro SoC, and in its presentation, Apple claimed the new SoC offered up to 20% faster gaming performance than the previous generation. While this may be true in certain scenarios, recent testing in Alien Isolation has revealed that the A18 Pro's GPU still has some shortcomings when it comes to gaming.

According to the tests run by MrMacRightPlus, the Apple iPhone 16 Pro Max is barely able to maintain 30 FPS in Alien Isolation when running at its native 2868×1320 pixel resolution. While Alien Isolation is a AAA title that was ported to the iPhone, it is still a 10-year-old game, meaning it should be fairly easy to run. Lowering the in-game resolution, however, results in a substantial improvement to the A18 Pro's performance, with the game reaching 60 FPS after the change. This 30 FPS limitation may not all be down to a lack of performance from the A18 Pro SoC, though.

Mobilint, an edge AI chip company led by CEO Dongjoo Shin, is set to make waves at the upcoming AI Hardware & Edge AI Summit 2024 in Silicon Valley. The three-day event, starting on September 10th, will showcase Mobilint's latest innovations in AI chip technology. The company will demonstrate live demos of its high-efficiency SoC 'REGULUS' for on-device AI and high-performance acceleration chip 'ARIES' for on-premises AI.

The AI Hardware Summit is an annual event where global IT giants such as Microsoft, NVIDIA, Google, Meta, and AMD, along with prominent startups, gather to share their developments in AI and machine learning. This year's summit features world-renowned AI experts as speakers, including Andrew Ng, CEO of Landing AI, and Mark Russinovich, CTO of Microsoft Azure.

During the Semicon Taiwan 2024 summit event, TSMC VP of Advanced Packaging Technology, Jun He, spoke about the importance of merging AI chip memory and logic chips using 3D IC technology. He predicted that by 2030 the worldwide semiconductor industry would hit the $1 trillion milestone with HPC and AI leading 40 percent of the market share. In 2027, TSMC will introduce the 2.5D CoWoS technology that includes eight A16 process chipsets and 12 HBM4. AI processors that use this technology will not only be much cheaper to produce but will also provide engineers with a greater level of convenience. Engineers will have the option to write new codes into them instead. Manufacturers are cutting the SoC and HBM architectural conversion and mass production costs down to nearly one-fourth.

Nevertheless, the increasing production capacities of 3D IC technology remain the main challenge, as the size of chips and the complexity of manufacturing are decisive factors. However, the higher the size of the chips, the more chiplets are added, and thus the performance is improved, but this now makes the process even more complicated and is associated with more risks of misalignment, breakage, and extraction failure.

Microsoft provided a detailed view of Maia 100 at Hot Chips 2024, their initial specialized AI chip. This new system is designed to work seamlessly from start to finish, with the goal of improving performance and reducing expenses. It includes specially made server boards, unique racks, and a software system focused on increasing the effectiveness and strength of sophisticated AI services, such as Azure OpenAI. Microsoft introduced Maia at Ignite 2023, sharing that they had created their own AI accelerator chip. More information was provided earlier this year at the Build developer event. The Maia 100 is one of the biggest processors made using TSMC's 5 nm technology, designed for handling extensive AI tasks on Azure platform.

Maia 100 SoC architecture features:

• A high-speed tensor unit (16xRx16) offers rapid processing for training and inferencing while supporting a wide range of data types, including low precision data types such as the MX data format, first introduced by Microsoft through the MX Consortium in 2023.
• The vector processor is a loosely coupled superscalar engine built with custom instruction set architecture (ISA) to support a wide range of data types, including FP32 and BF16.
• A Direct Memory Access (DMA) engine supports different tensor sharding schemes.
• Hardware semaphores enable asynchronous programming on the Maia system.

This could very well be what the elusive new PlayStation 5 console looks like. DeaLabs illustrated its design as part of its article compiling all rumored tech specs of the console. The console's body retains the essential design of the digital-only variant of PlayStation 5, and its refresh. The disc variant of PlayStation 5 has a crease accent running along its side panels, toward the top one-quarter. The PS5 Pro possibly has more crease accents in its place, possibly even serving as a set of air vents. This is only a 2-color illustration, which means the console could have a unique body color scheme, too.

The PlayStation 5 Pro is being designed for a nearly 2-3 times performance uplift over the original PlayStation 5, and its 6 nm mid-lifecycle refresh. AMD remains the SoC supplier for the PS5 Pro, and its chip is codenamed "Viola." This chip could be built on a more advanced foundry node than even the 6 nm "Oberon Plus" powering the PS5 (refresh). It is a semi-custom chip in the true sense, as it has a unique mix of AMD IP blocks from several generations.

Today SiFive, Inc., the gold standard for RISC-V computing, announced its new SiFive Performance P870-D datacenter processor to meet customer requirements for highly parallelizable infrastructure workloads including video streaming, storage, and web appliances. When used in combination with products from the SiFive Intelligence product family, datacenter architects can also build an extremely high-performance, energy efficient compute subsystem for AI-powered applications.

Building on the success of the P870, the P870-D supports the open AMBA CHI protocol so customers have more flexibility to scale the number of clusters. This scalability allows customers to boost performance while minimizing power consumption. By harnessing a standard CHI bus, the P870-D enables SiFive's customers to scale up to 256 cores while harnessing industry-standard protocols, including Compute Express Link (CXL) and CHI chip to chip (C2C), to enable coherent high core count heterogeneous SoCs and chiplet configurations.

In a strategic move to empower automakers with groundbreaking opportunities, Intel unveiled its first discrete graphics processing unit (dGPU), the Intel Arc Graphics for Automotive, at its AI Cockpit Innovation Experience event. To advance automotive AI, the product will be commercially deployed in vehicles as soon as 2025, accelerating automobile technology and unlocking a new era of AI-driven cockpit experiences and enhanced personalization for manufacturers and drivers alike.

Intel's entry into automotive discrete GPUs addresses growing demand for compute power in increasingly sophisticated vehicle cockpits. By adding the Intel Arc graphics for Automotive to its existing portfolio of AI-enhanced software-defined vehicle (SDV) system-on-chips (SoCs), Intel offers automakers an open, flexible and scalable platform solution that brings next-level, high-fidelity experiences to the vehicle.

VIA Technologies, Inc., a leading innovator in the development of embedded platforms and systems, today announced the launch of three new high-performance edge AI solutions: the SOM-5000, VAB-5000, and ARTiGO A5000. These platforms are designed to meet the growing demand for intelligent edge computing across a wide range of industrial, commercial, and consumer applications.

"These new platforms represent a significant leap forward in edge AI technology," said Epan Wu, General Manager, VIA Intelligent Solutions. "With their advanced processing capabilities and versatile connectivity options, the SOM-5000, VAB-5000, and ARTiGO A5000 enable our customers to develop innovative and efficient edge AI applications."

Weebit Nano Limited, a leading developer and licensor of advanced memory technologies for the global semiconductor industry, and tier-1 semiconductor foundry DB HiTek have taped-out (released to manufacturing) a demonstration chip integrating Weebit's embedded Resistive Random-Access Memory (ReRAM or RRAM) module in DB HiTek's 130 nm Bipolar-CMOS-DMOS (BCD) process. The highly integrated demo chips will be used for testing and qualification ahead of customer production, while demonstrating the performance and robustness of Weebit's technology.

This important milestone in the collaboration between Weebit and DB HiTek (previously announced on 19 October 2023) was completed on-schedule as part of the technology transfer process. The companies are working to make Weebit ReRAM available to DB HiTek customers for integration in their systems on chips (SoCs) as embedded non-volatile memory (NVM), and aim to have the technology qualified and ready for production in the second quarter of the 2025 calendar year. Weebit ReRAM is available now to select DB HiTek customers for design prototyping ahead of production.

Samsung Electronics today reported financial results for the second quarter ended June 30, 2024. The Company posted KRW 74.07 trillion in consolidated revenue and operating profit of KRW 10.44 trillion as favorable memory market conditions drove higher average sales price (ASP), while robust sales of OLED panels also contributed to the results.

Memory Market Continues To Recover; Solid Second Half Outlook Centered on Server Demand
The DS Division posted KRW 28.56 trillion in consolidated revenue and KRW 6.45 trillion in operating profit for the second quarter. Driven by strong demand for HBM as well as conventional DRAM and server SSDs, the memory market as a whole continued its recovery. This increased demand is a result of the continued AI investments by cloud service providers and growing demand for AI from businesses for their on-premise servers.

Since its reveal last week, we got a slightly more technical deep-dive from AMD on its two upcoming processors—the "Strix Point" silicon powering its Ryzen AI 300 series mobile processors; and the "Granite Ridge" chiplet MCM powering its Ryzen 9000 desktop processors. We present a closer look into the "Strix Point" SoC in this article. It turns out that "Strix Point" takes a significantly different approach to heterogeneous multicore than "Phoenix 2." AMD gave us a close look at how this works. AMD built the "Strix Point" monolithic silicon on the TSMC N4P foundry node, with a die-area of around 232 mm².

The "Strix Point" silicon sees the company's Infinity Fabric interconnect as its omnipresent ether. This is a point-to-point interconnect, unlike the ringbus on some Intel processors. The main compute machinery on the "Strix Point" SoC are its two CPU compute complexes (CCX), each with a 32b (read)/16b (write) per cycle data-path to the fabric. The concept of CCX makes a comeback with "Strix Point" after nearly two generations of "Zen." The first CCX contains the chip's four full-sized "Zen 5" CPU cores, which share a 16 MB L3 cache among themselves. The second CCX contains the chip's eight "Zen 5c" cores that share a smaller 8 MB L3 cache. Each of the 12 cores has a 1 MB dedicated L2 cache.

AMD in its architecture deep-dive Q&A session with the press, confirmed that the "Zen 5" and "Zen 5c" cores on the "Strix Point" silicon only feature 256-bit wide FPU data-paths, unlike the "Zen 5" cores in the "Granite Ridge" Ryzen 9000 desktop processors. "The Zen 5c used in Strix has a 256-bit data-path, and so does the Zen 5 used inside of Strix," said Mike Clark, AMD corporate fellow and chief architecture of the "Zen" CPU cores. "So there's no delta as you move back and forth [thread migration between the Zen 5 and Zen 5c complexes] in vector throughput," he added.

It doesn't seem like AMD disabled a physically available feature, but rather, the company developed a variant of both the "Zen 5" and "Zen 5c" cores that physically lack the 512-bit data-paths. "And you get the area advantage to be able to scale out a little bit more," Clark continued. This suggests that the "Zen 5" and "Zen 5c" cores on "Strix Point" are physically smaller than the ones on the 4 nm "Eldora" 8-core CCD that is featured in "Granite Ridge" and some of the key models of the upcoming 5th Gen EPYC "Turin" server processors.

AMD "Granite Ridge" is codename for the four new Ryzen 9000 series desktop processors the company plans to launch on July 31, 2024. The processor is built in the Socket AM5 package, and is meant to be backwards compatible with AMD 600-series chipset motherboards, besides the new 800-series chipset ones that will launch alongside. "Granite Ridge" is a chiplet-based processor, much like the Ryzen 7000 "Raphael," Ryzen 5000 "Vermeer," and Ryzen 3000 "Matisse." AMD is carrying over the 6 nm client I/O die over from "Raphael" in an effort to minimize development costs, much in the same way it carried over the 12 nm cIOD for "Vermeer" from "Matisse."

The SoC I/O features of "Granite Ridge" are contemporary, with its awesome 28-lane PCI-Express Gen 5 root complex that allows a PCI-Express 5.0 x16, two CPU-attached M.2 Gen 5 slots, and a Gen 5 x4 chipset bus. There's also a basic integrated graphics solution based on the older RDNA 2 graphics architecture; which should make these processors fit for all use-cases that don't need discrete graphics. The iGPU even has multimedia accelerators, an audio coprocessor, a display controller, and USB 3.2 interfaces from the processor.

Avnet ASIC, a division of Avnet Silica, an Avnet company, today announced that it has launched its new ultra-low-power design services for TSMC's cutting-edge 4 nm and below process technologies. These services are designed to enable customers to achieve exceptional power efficiency and performance in their high-performance applications, such as blockchain and AI edge computing. TSMC is the world's leading silicon foundry and Avnet ASIC division is a leading provider of ASIC and SoC full turnkey solutions.

The new design services leverage a comprehensive approach to address the challenges of operating at extreme low-voltage conditions in the 4 nm and below nodes. This includes recharacterizing standard cells for lower voltages, performing early RTL exploration to optimize power, performance, and area (PPA) tradeoffs, implementing an optimized clock tree, and utilizing transistor-level simulations to enhance the power optimization process.

New insights from Omdia's Desktop Monitor Intelligence Service show the gaming monitor market, featuring refresh rates over 120 Hz, is expected to grow by 9% YoY to 24.7 million units in 2024. Meanwhile, the smart monitor market, equipped with operating systems and streaming service portals, is projected to expand by 63% YoY to 1.2 million units.

In 1Q24, desktop monitor shipments hit 30.7 million units, a 5% increase year-on-year (YoY). The industry has been growing steadily since 3Q23, overcoming post-pandemic logistical disruptions. Notably, the gaming monitor market and smart monitors are expanding rapidly. This growth is driven by added value and high functionality, particularly in both monitor categories.

Samsung Electronics, the world leader in advanced memory technology, today announced it has successfully completed verification of the industry's fastest 10.7 gigabit-per-second (Gbps) Low Power Double Data Rate 5X (LPDDR5X) DRAM for use on MediaTek's next-generation Dimensity platform.

The 10.7 Gbps operation speed verification was carried out using Samsung's LPDDR5X 16-gigabyte (GB) package on MediaTek's upcoming flagship Dimensity 9400 System on Chip (SoC), scheduled to be released in the second half of this year. The two companies have closely collaborated to complete the verification within just three months.

Intel Corporation has achieved a revolutionary milestone in integrated photonics technology for high-speed data transmission. At the Optical Fiber Communication Conference (OFC) 2024, Intel's Integrated Photonics Solutions (IPS) Group demonstrated the industry's most advanced and first-ever fully integrated optical compute interconnect (OCI) chiplet co-packaged with an Intel CPU and running live data. Intel's OCI chiplet represents a leap forward in high-bandwidth interconnect by enabling co-packaged optical input/output (I/O) in emerging AI infrastructure for data centers and high performance computing (HPC) applications.

"The ever-increasing movement of data from server to server is straining the capabilities of today's data center infrastructure, and current solutions are rapidly approaching the practical limits of electrical I/O performance. However, Intel's groundbreaking achievement empowers customers to seamlessly integrate co-packaged silicon photonics interconnect solutions into next-generation compute systems. Our OCI chiplet boosts bandwidth, reduces power consumption and increases reach, enabling ML workload acceleration that promises to revolutionize high-performance AI infrastructure," said Thomas Liljeberg, senior director, Product Management and Strategy, Integrated Photonics Solutions (IPS) Group.

TrendForce has observed that in 2024, major CSPs such as Microsoft, Google, Meta, and AWS will continue to be the primary buyers of high-end AI servers, which are crucial for LLM and AI modeling. Following establishing a significant AI training server infrastructure in 2024, these CSPs are expected to actively expand into edge AI in 2025. This expansion will include the development of smaller LLM models and setting up edge AI servers to facilitate AI applications across various sectors, such as manufacturing, finance, healthcare, and business.

Moreover, AI PCs or notebooks share a similar architecture to AI servers, offering substantial computational power and the ability to run smaller LLM and generative AI applications. These devices are anticipated to serve as the final bridge between cloud AI infrastructure and edge AI for small-scale training or inference applications.

TSMC has commenced mass-production of chips for Intel on its 3 nm EUV FinFET foundry node, according to a report by Taiwan industry observer DigiTimes. Intel is using the TSMC 3 nm node for the compute tile of its upcoming Core Ultra 300 "Lunar Lake" processor. The company went into depth about "Lunar Lake" in its Computex 2024 presentation. While a disaggregated chiplet-based processor like "Meteor Lake," the new "Lunar Lake" chip sees the CPU cores, iGPU, NPU, and memory controllers sit on a single chiplet called the compute tile, built on the 3 nm node; while the SoC and I/O components are disaggregated the chip's only other chiplet, the SoC tile, which is built on the TSMC 6 nm node.

Intel hasn't gone into the nuts and bolts of "Arrow Lake," besides mentioning that the processor will feature the same "Lion Cove" P-cores and "Skymont" E-cores as "Lunar Lake," albeit arranged in a more familiar ringbus configuration, where the E-core clusters share L3 cache with the P-cores (something that doesn't happen on "Lunar Lake"). "Arrow Lake" also features a iGPU based on the same Xe2 graphics architecture as "Lunar Lake," and will feature an NPU that meets Microsoft Copilot+ AI PC requirements. What remains a mystery about "Arrow Lake" is the way Intel will go about organizing the various chiplets or tiles. Reports from February 2024 mentioned Intel tapping into TSMC 3 nm for just the disaggregated graphics tile of "Arrow Lake," but we now know from "Lunar Lake" that Intel doesn't shy away from letting TSMC fabricate its CPU cores. The first notebooks powered by "Lunar Lake" are expected to hit shelves within Q3-2024, with "Arrow Lake" following on in Q4.

AMD late Tuesday released the latest version of its Chipset Software. This is an important piece of software that, besides providing drivers for the various onboard SoC interfaces of the processor and chipset, provides your Windows operating system with software-side processor power-management (PPM) awareness. Version 6.05.28.016 is the latest version of it, supporting AMD 300-series, 400-series, 500-series, and 600-series chipsets. Version 6.05.28.016 adds support for the new Windows 11 24H2 Update. Support is added for a new program (possibly the latest version of Ryzen Master). The release also adds a few unspecified bug-fixes.

DOWNLOAD: AMD Chipset Software 6.05.28.016The change-log follows.

The high purchase price of an electric vehicle (EV) remains one of the biggest barriers for potential buyers on a global scale. EVs are currently more expensive to build than traditional gasoline-powered cars, primarily because of the high costs associated with advanced battery and e-motor technology. The near-term solution is to enhance the efficiency of the existing battery technology through energy savings at the vehicle level, including improved integration with EV station infrastructure. This is exactly the challenge that Silicon Mobility, an Intel Company, has now solved with today's launch of the new OLEA U310 system-on-chip (SoC). This next-gen technology promises to significantly improve the overall performance of electric vehicles (EVs), streamline design and production processes, and expand SoC services to ensure seamless operation across various EV station platforms.

Representing a first for the industry, the new SoC is the only complete solution that combines hardware and software in one and is engineered to match the need for powertrain domain control in electrical architectures with distributed software. Built with a unique hybrid and heterogeneous architecture, a single OLEA 310 FPCU can replace as many as six standard microcontrollers in a system combination in which it controls an inverter, a motor, a gearbox, a DC-DC converter and an on-board-charger. Using the 310 FPCU, original equipment manufacturers (OEMs) and Tier 1 suppliers can control multiple and diverse power and energy functions simultaneously in real time.

Arm CEO Rene Haas predicts that SoCs based on the Arm CPU machine architecture will beat x86 in the Windows PC space in the next 5 years (by 2029). Haas is bullish about the current crop of Arm SoCs striking the right balance of performance and power efficiency, along with just the right blend of on-chip acceleration for AI and graphics, to make serious gains in this market, which has traditionally been dominated by the x86 machine architecture, with chips from just two manufacturers—Intel and AMD. On the other hand, Arm has a vibrant ecosystem of SoC vendors. "Arm's market share in Windows - I think, truly, in the next five years, it could be better than 50%." Haas said, in an interview with Reuters.

Currently, Microsoft has an exclusive deal with Qualcomm to power Windows-on-Arm (WoA) Copilot+ AI PCs. Qualcomm's chip lineup spans the Snapdragon Elite X and Snapdragon Elite Plus. This exclusivity, however, could change, with a recent interview of Michael Dell and Jensen Huang hinting at NVIDIA working on a chip for the AI PC market. The writing is on the wall for Intel and AMD—they need to compete with Arm on its terms: to make leaner PC processors with the kinds of performance/Watt and chip costs that Arm SoCs offer to PC OEMs. Intel has taken a big step in this direction with its "Lunar Lake" processor, you can read all about the architecture here.

MediaTek announced today at COMPUTEX 2024 that the company has joined Arm Total Design, a fast-growing ecosystem that aims to accelerate and simplify the development of products based on Arm Neoverse Compute Subsystems (CSS). Arm Neoverse CSS is designed to meet the performance and efficiency needs of AI applications in the data center, infrastructure systems, telecommunications, and beyond.

"Together with Arm, we're enabling our customers' designs to meet the most challenging workloads for AI applications, maximizing performance per watt," said Vince Hu, Corporate Vice President at MediaTek. "We will be working closely with Arm as we expand our footprint into data centers, utilizing our expertise in hybrid computing, AI, SerDes and chiplets, and advance packaging technologies to accelerate AI innovation from the edge to the cloud."

Silicon Motion Technology Corporation, a global leader in designing and marketing controller solutions for display interface and NAND storage, today announced the launch of the SM770 USB display interface SoC for USB docking stations to simplify connectivity for multiple 4K Ultra-High Definition Displays, with low latency and low power consumption.

The new SM770 is a high-performance USB Display interface SoC that supports up to three concurrent 4K UHD (3840x2160@60p) displays, leveraging Silicon Motion's innovative CAT (Content Adaptive Technology) and employs multiple image and video processing algorithms to compress display data and minimize bandwidth usage to deliver ultra-low latency from the computer to the monitors. By transferring most of the compression work to a hardware accelerator, CAT technology operates more efficiently and reduces the CPU load.

At COMPUTEX 2024, MediaTek will showcase new products and technology demonstrations, featuring highlights in AI, Smart TVs, Chromebooks, IoT and more, in addition to a keynote by Vice Chairman and CEO Dr. Rick Tsai about how MediaTek can enable ubiquitous AI.

At this year's show, MediaTek will debut two new chipsets with powerful performance and support for the latest AI enhancements across multiple verticals: the Kompanio 838 SoC for premium Chromebooks, and the Pentonic 800 SoC for 4K premium smart TVs and displays.