Monday, July 22nd 2024
Avnet ASIC Team Launches Ultra-Low-Power Design Services for TSMC's 4nm Process Nodes
Avnet ASIC, a division of Avnet Silica, an Avnet company, today announced that it has launched its new ultra-low-power design services for TSMC's cutting-edge 4 nm and below process technologies. These services are designed to enable customers to achieve exceptional power efficiency and performance in their high-performance applications, such as blockchain and AI edge computing. TSMC is the world's leading silicon foundry and Avnet ASIC division is a leading provider of ASIC and SoC full turnkey solutions.
The new design services leverage a comprehensive approach to address the challenges of operating at extreme low-voltage conditions in the 4 nm and below nodes. This includes recharacterizing standard cells for lower voltages, performing early RTL exploration to optimize power, performance, and area (PPA) tradeoffs, implementing an optimized clock tree, and utilizing transistor-level simulations to enhance the power optimization process.
The Avnet ASIC team built a full-scale technical A-Z approach to enable PPA optimization of high-performance chips working at extremely low voltage and proved it in TSMC's 4 nm process. Performance, dynamic and leakage power estimations have been confirmed by post-silicon validation.
The customer defined the board solution and chip implementation concept, requirements, and executed front-end design based on library characterization for near-threshold voltage operation. Avnet ASIC then executed this design to meet aggressive market targets, enabling the ultra-low-power performance of the customer's application.
"One of the industry challenges today is to optimize application performance by choosing the correct technology to meet customer needs," said Pavel Vilk, GM and Head of Engineering at Avnet ASIC.
"TSMC's 4 nm process provides a great opportunity to save power and area without compromising target performance. However, operating at low voltages puts a lot of effort on voltage drop, which needs to be optimized through a holistic solution of board-package-chip design. Being a TSMC Value Chain Aggregator and a full turnkey partner to customers, we believe this new achievement could bring great value in helping our customers deliver their products to market competitively."
The new announcement follows the announcement of the Avnet ASIC team from February that it has been appointed as a Value Chain Aggregator (VCA) by TSMC. The appointment positions the Avnet ASIC team as a channel for TSMC ASIC customers, offering a full turnkey solution from design inception to layout and mass production, implemented in TSMC's most advanced silicon processes.
The collaboration signifies a landmark agreement within Avnet, enhancing the offerings by combining the strong technology of TSMC with the ASIC design and manufacturing capabilities of Avnet ASIC. This initiative enables access to TSMC's most advanced silicon processes for customers, establishing Avnet ASIC as a channel partner of TSMC for comprehensive ASIC SoC solutions.
Source:
Avnet ASIC
The new design services leverage a comprehensive approach to address the challenges of operating at extreme low-voltage conditions in the 4 nm and below nodes. This includes recharacterizing standard cells for lower voltages, performing early RTL exploration to optimize power, performance, and area (PPA) tradeoffs, implementing an optimized clock tree, and utilizing transistor-level simulations to enhance the power optimization process.
The customer defined the board solution and chip implementation concept, requirements, and executed front-end design based on library characterization for near-threshold voltage operation. Avnet ASIC then executed this design to meet aggressive market targets, enabling the ultra-low-power performance of the customer's application.
"One of the industry challenges today is to optimize application performance by choosing the correct technology to meet customer needs," said Pavel Vilk, GM and Head of Engineering at Avnet ASIC.
"TSMC's 4 nm process provides a great opportunity to save power and area without compromising target performance. However, operating at low voltages puts a lot of effort on voltage drop, which needs to be optimized through a holistic solution of board-package-chip design. Being a TSMC Value Chain Aggregator and a full turnkey partner to customers, we believe this new achievement could bring great value in helping our customers deliver their products to market competitively."
The new announcement follows the announcement of the Avnet ASIC team from February that it has been appointed as a Value Chain Aggregator (VCA) by TSMC. The appointment positions the Avnet ASIC team as a channel for TSMC ASIC customers, offering a full turnkey solution from design inception to layout and mass production, implemented in TSMC's most advanced silicon processes.
The collaboration signifies a landmark agreement within Avnet, enhancing the offerings by combining the strong technology of TSMC with the ASIC design and manufacturing capabilities of Avnet ASIC. This initiative enables access to TSMC's most advanced silicon processes for customers, establishing Avnet ASIC as a channel partner of TSMC for comprehensive ASIC SoC solutions.
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