AMD reportedly plans to incorporate glass substrates into its high-performance system-in-packages (SiPs) sometimes between 2025 and 2026. Glass substrates offer several advantages over traditional organic substrates, including superior flatness, thermal properties, and mechanical strength. These characteristics make them well-suited for advanced SiPs containing multiple chiplets, especially in data center applications where performance and durability are critical. The adoption of glass substrates aligns with the industry's broader trend towards more complex chip designs. As leading-edge process technologies become increasingly expensive and yield gains diminish, manufacturers turn to multi-chiplet designs to improve performance. AMD's current EPYC server processors already incorporate up to 13 chiplets, while its Instinct AI accelerators feature 22 pieces of silicon. A more extreme testament is Intel's Ponte Vecchio, which utilized 63 tiles in a single package.

Glass substrates could enable AMD to create even more complex designs without relying on costly interposers, potentially reducing overall production expenses. This technology could further boost the performance of AI and HPC accelerators, which are a growing market and require constant innovation. The glass substrate market is heating up, with major players like Intel, Samsung, and LG Innotek also investing heavily in this technology. Market projections suggest explosive growth, from $23 million in 2024 to $4.2 billion by 2034. Last year, Intel committed to investing up to 1.3 trillion Won (almost one billion USD) to start applying glass substrates to its processors by 2028. Everything suggests that glass substrates are the future of chip design, and we await to see first high-volume production designs.

Applied Materials, Inc. today introduced materials engineering innovations designed to increase the performance-per-watt of computer systems by enabling copper wiring to scale to the 2 nm logic node and beyond. "The AI era needs more energy-efficient computing, and chip wiring and stacking are critical to performance and power consumption," said Dr. Prabu Raja, President of the Semiconductor Products Group at Applied Materials. "Applied's newest integrated materials solution enables the industry to scale low-resistance copper wiring to the emerging angstrom nodes, while our latest low-k dielectric material simultaneously reduces capacitance and strengthens chips to take 3D stacking to new heights."

Overcoming the Physics Challenges of Classic Moore's Law Scaling
Today's most advanced logic chips can contain tens of billions of transistors connected by more than 60 miles of microscopic copper wiring. Each layer of a chip's wiring begins with a thin film of dielectric material, which is etched to create channels that are filled with copper. Low-k dielectrics and copper have been the industry's workhorse wiring combination for decades, allowing chipmakers to deliver improvements in scaling, performance and power-efficiency with each generation.

Samsung Electronics, a world leader in advanced semiconductor technology, today announced that it will provide turnkey semiconductor solutions using the 2-nanometer (nm) foundry process and the advanced 2.5D packaging technology Interposer-Cube S (I-Cube S) to Preferred Networks, a leading Japanese AI company.

By leveraging Samsung's leading-edge foundry and advanced packaging products, Preferred Networks aims to develop powerful AI accelerators that meet the ever-growing demand for computing power driven by generative AI.

In 2016, TSMC developed and named its InFO FOWLP technology, and applied it to the A10 processor used in the iPhone 7. TrendForce points out that since then, OSAT providers have been striving to develop FOWLP and FOPLP technologies to offer more cost-effective packaging solutions.

Starting in the second quarter, chip companies like AMD have actively engaged with TSMC and OSAT providers to explore the use of FOPLP technology for chip packaging and helping drive industry interest in FOPLP. TrendForce observes that there are three main models for introducing FOPLP packaging technology: Firstly, OSAT providers transitioning from traditional methods of consumer IC packaging to FOPLP. Secondly, foundries and OSAT providers packaging AI GPUs that are transitioning 2.5D packaging from wafer level to panel level. Thirdly, panel makers who are packaging consumer ICs.

Ansys power integrity solutions have been certified by Samsung Foundry for use with Samsung's new SF2Z 2 nm gate-all-around manufacturing technology. SF2Z includes advanced technology that moves the power distribution network to the backside of the chip — saving space, lowering costs, and improving performance. Ansys solutions enable early adopters of Samsung's technology to design leading-edge semiconductor products for HPC, smartphones, AI, data center communication, and graphics processors.

The certification includes RedHawk-SC, which provides predictively accurate signoff verification for electromigration and voltage drop (IR drop) on power distribution networks for digital designs. In addition, the Totem power integrity platform provides comprehensive evaluation for analog and mixed-signal designs. Both RedHawk-SC and Totem signoff capabilities can reduce project risk, improve reliability, and extend the longevity of chips.

TrendForce has observed that in 2024, major CSPs such as Microsoft, Google, Meta, and AWS will continue to be the primary buyers of high-end AI servers, which are crucial for LLM and AI modeling. Following establishing a significant AI training server infrastructure in 2024, these CSPs are expected to actively expand into edge AI in 2025. This expansion will include the development of smaller LLM models and setting up edge AI servers to facilitate AI applications across various sectors, such as manufacturing, finance, healthcare, and business.

Moreover, AI PCs or notebooks share a similar architecture to AI servers, offering substantial computational power and the ability to run smaller LLM and generative AI applications. These devices are anticipated to serve as the final bridge between cloud AI infrastructure and edge AI for small-scale training or inference applications.

A Finnish company called Flow Computing is making some very bold claims when it comes to its new IP. The company has developed what it calls a Parallel Processing Unit or a PPU, which the company claims can boost the performance of any CPU by a hundred times its current performance. Furthermore, the company claims that its PPU can double the performance of any current code execution, with no need for any kind of optimisation for its PPU. The PPU can be integrated into new processors, but it can also be designed as a discrete chip that can be added to any current hardware and Flow Computing claims the performance benefits will be the same in both instances.

Flow Computing is a spinoff from the VTT Technical Research Centre of Finland and the company emerged from stealth mode last week with around €4 million in funding. Flow Computing doesn't intend to make its PPU by itself, but instead, the company wants to licence its tech to third parties, to give everyone an equal opportunity to take advantage of what's on offer. At this point in time, Flow Computing hasn't made any custom silicon, instead the company has validated its PPU using an FPGA tested against various Intel CPUs. As such, there are numbers to back up its claims and we've provided links below to a whitepaper and an FAQ for those that are interested in doing a deep dive into its claims. Flow Computing appears to have a few different implementations of its PPU, ranging from 16 to 256 cores, with the latter being for high-end computers, but the basic is said to be suitable for something as basic as a smartwatch. Time will tell if Flow Computing will be able to deliver on its claims and it'll be an interesting company to follow.

MediaTek announced today at COMPUTEX 2024 that the company has joined Arm Total Design, a fast-growing ecosystem that aims to accelerate and simplify the development of products based on Arm Neoverse Compute Subsystems (CSS). Arm Neoverse CSS is designed to meet the performance and efficiency needs of AI applications in the data center, infrastructure systems, telecommunications, and beyond.

"Together with Arm, we're enabling our customers' designs to meet the most challenging workloads for AI applications, maximizing performance per watt," said Vince Hu, Corporate Vice President at MediaTek. "We will be working closely with Arm as we expand our footprint into data centers, utilizing our expertise in hybrid computing, AI, SerDes and chiplets, and advance packaging technologies to accelerate AI innovation from the edge to the cloud."

South Korea's stock of semiconductor chips dropped more than it has since 2014. This big decrease shows that customers are buying chips faster than companies can make them, as they need more equipment for developing artificial intelligence (AI) technology. Official data released on May 31 revealed that in April, chip inventories fell by 33.7% compared to a year earlier - the largest drop since late 2014. This is the fourth month in a row that inventories have declined, while at the same time South Korea's exports of semiconductors have gone up again. Additionally, South Korea's production of chips rose 22.3% in April, which is less than the 30.2% increase from the previous month. Shipments from factories grew 18.6%, also lower than March's 16.4% growth.

South Korea is home to the two biggest memory chipmakers in the world (Samsung and SK Hynix), and they are competing to supply chips to NVIDIA, the latest having an insatiable appetite for more and more chips. These two Korean companies are in a race to develop a more advanced and more profitable version of high-bandwidth memory, or HBM. During the memory chip boom from 2013-2015, inventories didn't increase for about a year and a half. In the 2016-2017 cycle, inventory declines lasted nearly a year. A report from South Korea's central bank expects the latest surge in chip demand to continue at least until the first half of next year. This is because the "artificial intelligence boom" is driving up demand similarly to how cloud servers caused an expansion in 2016, and now mostly forgotten crypto-mining fever. South Korea will release its latest export data on June 1.

According to a report by KED Global, Korean chipmaking giant Samsung is ramping up its efforts to compete with global giants like TSMC and Intel. The latest partnership on the horizon is AMD's collaboration with Samsung. AMD is planning to utilize Samsung's cutting-edge 3 nm technology for its future chips. More specifically, AMD wants to utilize Samsung's gate-all-around FETs (GAAFETs). During ITF World 2024, AMD CEO Lisa Su noted that the company intends to use 3 nm GAA transistors for its future products. The only company offering GAAFETs on a 3 nm process is Samsung. Hence, this report from KED gains more credibility.

While we don't have any official information, AMD's utilization of a second foundry as a manufacturing partner would be a first for the company in years. This strategic move signifies a shift towards dual-sourcing, aiming to diversify its supply chain and reduce dependency on a single manufacturer, previously TSMC. We still don't know what specific AMD products will use GAAFETs. AMD could use them for CPUs, GPUs, DPUs, FPGAs, and even data center accelerators like Instinct MI series.

Silicon Motion Technology Corporation ("Silicon Motion"), a global leader in designing and marketing NAND flash controllers for solid-state storage devices, today launched the SM2322, the industry's fastest single-chip high-performance, low-power, and cost-effective solution for external portable SSDs, supporting up to 8 TB of storage and achieves unparalleled data transfer rates of 20 Gbps for storing and accessing large amounts of content seamlessly from AI smartphones, high-performance multimedia devices, and game consoles.

With the increase of AI-capable devices, high density and high-performance storage solutions are becoming more critical to consumers. Portable SSDs powered by the new SM2322 controller are the only solution that offers low-cost, high-density and high-performance, making it the ideal solution for these applications. Equipped with a USB 3.2 Gen 2x2 interface with 20 Gb/s bandwidth and fully integrated hardware and software solution delivering peak sequential read and write transfer speeds of 2,100 MB/s and 2,000 MB/s, respectively, with up to 8 TB capacity, SM2322 powered high-performance portable SSDs enable an ultra-compact and lightweight form factor. The SM2322 supports the ProRes format and MFi specification for iPhone users while also being compatible with Windows, Android OS, and macOS, making it an ideal high-density, high-performance portable storage solution for AI smartphones, HD content creators, and gaming enthusiasts who require high-density, high-performance portable storage.

According to the Taiwan Central News Agency AMD is considering opening up an R&D center in Taiwan. AMD is said to have applied with the Ministry of Economic Affairs (MOEA) as part of Taiwan's "A+ global R&D and innovation partnership program" to set up a new R&D facility. The government partnership program covers three types of fields, namely AI, new-generation semiconductors including high-power and high-frequency ICs, and new 5G network structures and it's aiming for both local and international businesses to set up new R&D centers. AMD has yet to announce any plans about the potential R&D center and the MOEA has declined to share any details with local media in Taiwan.

However, an unnamed source with inside knowledge in the matter has revealed that AMD is looking at investing around NT$5 billion (~US$155 million), based on the application. The same source also mentioned that the MOEA has stipulated conditions that AMD has to meet, which among other things involves working with local IC design companies to help further develop Taiwan's IC design industry, working with local companies to produce servers with AI chips and working with local universities to cultivate talent. Furthermore, the MOEA is said to have asked AMD to recruit at least 20 percent of its R&D centre workforce from outside of Taiwan, to avoid competing with local companies for staff. AMD could be making an announcement about the R&D center at Computex, but it's worth keeping in mind that these things take time. Back in 2021, NVIDIA announced that it would set up an R&D center in Taiwan, but with a much bigger budget of NT$24.3 billion plus a government subsidy of a further NT$6.7 billion. NVIDIA has as yet to announce the opening of its Taiwan R&D center.

During the European Technology Symposium 2024, TSMC has announced its readiness to manufacture next-generation HBM4 base dies using both 12 nm and 5 nm nodes. This significant development is expected to substantially improve the performance, power consumption, and logic density of HBM4 memory, catering to the demands of high-performance computing (HPC) and artificial intelligence (AI) applications. The shift from a traditional 1024-bit interface to an ultra-wide 2048-bit interface is a key aspect of the new HBM4 standard. This change will enable the integration of more logic and higher performance while reducing power consumption. TSMC's N12FFC+ and N5 processes will be used to produce these base dies, with the N12FFC+ process offering a cost-effective solution for achieving HBM4 performance and the N5 process providing even more logic and lower power consumption at HBM4 speeds.

The company is collaborating with major HBM memory partners, including Micron, Samsung, and SK Hynix, to integrate advanced nodes for HBM4 full-stack integration. TSMC's base die, fabricated using the N12FFC+ process, will be used to install HBM4 memory stacks on a silicon interposer alongside system-on-chips (SoCs). This setup will enable the creation of 12-Hi (48 GB) and 16-Hi (64 GB) stacks with per-stack bandwidth exceeding 2 TB/s. TSMC's collaboration with EDA partners like Cadence, Synopsys, and Ansys ensures the integrity of HBM4 channel signals, thermal accuracy, and electromagnetic interference (EMI) in the new HBM4 base dies. TSMC is also optimizing CoWoS-L and CoWoS-R for HBM4 integration, meaning that massive high-performance chips are already utilizing this technology and getting ready for volume manufacturing.

NEO Semiconductor, a leading developer of innovative technologies for 3D NAND flash and DRAM memory, today announced a performance boosting Floating Body Cell Mechanism for 3D X-DRAM. Andy Hsu, Founder & CEO presented groundbreaking Technology CAD (TCAD) simulation results for NEO's 3D X-DRAM during the 16th IEEE International Memory Workshop (IMW) 2024 in Seoul, Republic of Korea.

Neo Semiconductor reveals a unique performance boosting mechanism called Back-gate Channel-depth Modulation (BCM) for Floating Body Cell that can increase data retention by 40,000X and sensing window by 20X.

United Microelectronics Corporation ("UMC"), a leading global semiconductor foundry, today announced the industry's first 3D IC solution for RFSOI technology. Available on UMC's 55 nm RFSOI platform, the stacked silicon technology reduces die size by more than 45% without any degradation of radio frequency (RF) performance, enabling customers to efficiently integrate more RF components to address the greater bandwidth requirements of 5G.

As mobile device manufacturers pack more frequency bands in newer generations of smartphones, the company's 3D IC solution for RFSOI addresses the challenge of integrating more RF front-end modules (RF-FEM) - critical components in devices to transmit and receive data - in a device by vertically stacking dies to reduce surface area. RFSOI is the foundry process used for RF chips such as low noise amplifiers, switches, and antenna tuners. Utilizing wafer-to-wafer bonding technology, UMC's 3D IC solution for RFSOI resolves the common issue of RF interference between stacked dies. The company has received multiple patents for this process, which is now ready for production.

A couple of weeks ago, we reported on NVIDIA directing users of Intel's 13th Generation Raptor Lake and 14th Generation Raptor Lake Refresh CPUs to consult Intel for any issues with system stability. Motherboard makers, by default, often run the CPU outside of Intel's recommended specifications, overvolting the CPU through modifying voltage curves, automatic overclocks, and removing power limits.

Today, we learned that Igor's Lab has obtained a statement from Intel that the company prepared for motherboard OEMs regarding the issues multiple users report. Intel CPUs come pre-programmed with a stock voltage curve. When motherboard makers remove power limits and automatically adjust voltage curves and frequency targets, the CPU can be pushed outside its safe operating range, possibly causing system instability. Intel has set up a dedicated website for users to report their issues and offer support. Manufacturers like GIGABYTE have already issued new BIOS updates for users to achieve maximum stability, which incidentally has recent user reports of still being outside Intel spec, setting PL2 to 188 W, loadlines to 1.7/1.7 and current limit to 249 A. While MSI provided a blog post tutorial for stability. ASUS has published updated BIOS for its motherboards to reflect on this Intel baseline spec as well. Surprisingly, not all the revised BIOS values match up with the Intel Baseline Profile spec for these various new BIOS updates from different vendors. You can read the statement from Intel in the quote below.

Micron Technology, Inc., one of the world's largest semiconductor companies and the only U.S.-based manufacturer of memory, and the Biden-Harris Administration today announced that they have signed a non-binding Preliminary Memorandum of Terms (PMT) for $6.1 billion in funding under the CHIPS and Science Act to support planned leading-edge memory manufacturing in Idaho and New York.

The CHIPS and Science Act grants of $6.1 billion will support Micron's plans to invest approximately $50 billion in gross capex for U.S. domestic leading-edge memory manufacturing through 2030. These grants and additional state and local incentives will support the construction of one leading-edge memory manufacturing fab to be co-located with the company's existing leading-edge R&D facility in Boise, Idaho and the construction of two leading-edge memory fabs in Clay, New York.

TSMC today unveiled its newest semiconductor process, advanced packaging, and 3D IC technologies for powering the next generation of AI innovations with silicon leadership at the Company's 2024 North America Technology Symposium. TSMC debuted the TSMC A16 technology, featuring leading nanosheet transistors with innovative backside power rail solution for production in 2026, bringing greatly improved logic density and performance. TSMC also introduced its System-on-Wafer (TSMC-SoW) technology, an innovative solution to bring revolutionary performance to the wafer level in addressing the future AI requirements for hyperscaler datacenters.

This year marks the 30th anniversary of TSMC's North America Technology Symposium, and more than 2,000 attended the event, growing from less than 100 attendees 30 years ago. The North America Technology Symposium in Santa Clara, California kicks off TSMC Technology Symposiums around the world in the coming months. The symposium also features an "Innovation Zone," designed to highlight the technology achievements of our emerging start-up customers.

Global PC shipments grew around 3% YoY in Q1 2024 after eight consecutive quarters of declines due to demand slowdown and inventory correction, according to the latest data from Counterpoint Research. The shipment growth in Q1 2024 came on a relatively low base in Q1 2023. The coming quarters of 2024 will see sequential shipment growth, resulting in 3% YoY growth for the full year, largely driven by AI PC momentum, shipment recovery across different sectors, and a fresh replacement cycle.

Lenovo's PC shipments were up 8% in Q1 2024 off an easy comparison from last year. The brand managed to reclaim its 24% share in the market, compared to 23% in Q1 2023. HP and Dell, with market shares of 21% and 16% respectively, remained flattish, waiting for North America to drive shipment growth in the coming quarters. Apple's shipment performance was also resilient, with the 2% growth mainly supported by M3 base models.

Meta has announced the next generation of its Meta Training and Inference Accelerator (MTIA) chip, which is designed to train and infer AI models at scale. The newest MTIA chip is a second-generation design of Meta's custom silicon for AI, and it is being built on TSMC's 5 nm technology. Running at the frequency of 1.35 GHz, the new chip is getting a boost to 90 Watts of TDP per package compared to just 25 Watts for the first-generation design. Basic Linear Algebra Subprograms (BLAS) processing is where the chip shines, and it includes matrix multiplication and vector/SIMD processing. At GEMM matrix processing, each chip can process 708 TeraFLOPS at INT8 (presumably meant FP8 in the spec) with sparsity, 354 TeraFLOPS without, 354 TeraFLOPS at FP16/BF16 with sparsity, and 177 TeraFLOPS without.

Classical vector and processing is a bit slower at 11.06 TeraFLOPS at INT8 (FP8), 5.53 TeraFLOPS at FP16/BF16, and 2.76 TFLOPS single-precision FP32. The MTIA chip is specifically designed to run AI training and inference on Meta's PyTorch AI framework, with an open-source Triton backend that produces compiler code for optimal performance. Meta uses this for all its Llama models, and with Llama3 just around the corner, it could be trained on these chips. To package it into a system, Meta puts two of these chips onto a board and pairs them with 128 GB of LPDDR5 memory. The board is connected via PCIe Gen 5 to a system where 12 boards are stacked densely. This process is repeated six times in a single rack for 72 boards and 144 chips in a single rack for a total of 101.95 PetaFLOPS, assuming linear scaling at INT8 (FP8) precision. Of course, linear scaling is not quite possible in scale-out systems, which could bring it down to under 100 PetaFLOPS per rack.Below, you can see images of the chip floorplan, specifications compared to the prior version, as well as the system.

At the Intel Vision 2024 customer and partner conference, Intel introduced the Intel Gaudi 3 accelerator to bring performance, openness and choice to enterprise generative AI (GenAI), and unveiled a suite of new open scalable systems, next-gen products and strategic collaborations to accelerate GenAI adoption. With only 10% of enterprises successfully moving GenAI projects into production last year, Intel's latest offerings address the challenges businesses face in scaling AI initiatives.

"Innovation is advancing at an unprecedented pace, all enabled by silicon - and every company is quickly becoming an AI company," said Intel CEO Pat Gelsinger. "Intel is bringing AI everywhere across the enterprise, from the PC to the data center to the edge. Our latest Gaudi, Xeon and Core Ultra platforms are delivering a cohesive set of flexible solutions tailored to meet the changing needs of our customers and partners and capitalize on the immense opportunities ahead."

According to the latest report from Bloomberg, the US government under Joe Biden's administration has announced plans to provide Taiwan Semiconductor Manufacturing Company (TSMC) with a substantial financial support package worth $11.6 billion. The package is composed of $6.6 billion in grants and up to $5 billion in loans. This represents the most significant financial assistance approved under the CHIPS and Science Act, a key initiative to resurrect the US chip industry. The funding will aid TSMC in establishing three cutting-edge semiconductor production facilities in Arizona, with the company's total investment in the state expected to exceed an impressive $65 billion. TSMC's multi-phase Arizona project will commence with the construction of a fab module near its existing Fab 21 facility. Production using 4 nm and 5 nm process nodes is slated to begin by early 2025. The second phase, scheduled for 2028, will focus on even more advanced 2 nm and 3 nm technologies.

TSMC has kept details about the third facility's production timeline and process node under wraps. The company's massive investment in Arizona is expected to profoundly impact the local economy, creating 6,000 high-tech manufacturing jobs and over 20,000 construction positions. Moreover, $50 million has been earmarked for training local workers, which aligns with President Joe Biden's goal of bolstering domestic manufacturing and technological independence. However, TSMC's Arizona projects have encountered obstacles, including labor disputes and uncertainties regarding government support, resulting in delays for the second facility's production timeline. Additionally, reports suggest that at least one TSMC supplier has abandoned plans to set up operations in Arizona due to workforce-related challenges.

Imagination Technologies today unveils the next product in the Catapult CPU IP range, the Imagination APXM-6200 CPU: a RISC-V application processor with compelling performance density, seamless security and the artificial intelligence capabilities needed to support the compute and intuitive user experience needs for next generation consumer and industrial devices.

"The number of RISC-V based devices is skyrocketing with over 16Bn units forecast by 2030, and the consumer market is behind much of this growth" says Rich Wawrzyniak, Principal Analyst at SHD Group. "One fifth of all consumer devices will have a RISC-V based CPU by the end of this decade. Imagination is set to be a force in RISC-V with a strategy that prioritises quality and ease of adoption. Products like APXM-6200 are exactly what will help RISC-V achieve the promised success."

Earlier today, Dutch Prime Minister Mark Rutte met with China's President Xi Jinping—fresh reportage has focused on their discussion of technological trade restrictions. Holland's premier had to carefully navigate the conversation around recent global tensions, most notably the prevention of fancy ASML chipmaking equipment reaching the Chinese mainland. CCTV (China's state broadcaster) selected a couple of choice quotes for inclusion in an online report—Xi remarked that: "the Chinese people also have the right to legitimate development, and no force can stop the pace of China's scientific and technological development and progress." Specific manufacturers and types of machinery were not mentioned during the meeting between state leaders, but media interpretations point to recent ASML debacles being entirely relevant, given the context of international relationships.

ASML is keen to keep Chinese firms on its order books—according to AP News: "China became ASML's second-largest market, accounting for 29% of its revenue as firms bought up equipment before the licensing requirement took effect." Revised licensing agreements have stymied the supply of ASML most advanced chipmaking tools—Chinese foundries have resorted to upgrading existing/older equipment (backed by government funding) in efforts to stay competitive with international producers. Semiconductor Manufacturing International Corporation (SMIC) is reportedly racing to get natively designed EUV machines patented (in co-operation with Huawei). Post-meeting, Rutte commented (to press) on the ongoing technology restrictions: "what I can tell you is that... when we have to take measures, that they are never aimed at one country specifically, that we always try to make sure that the impact is limited, is not impacting the supply chain, and therefore is not impacting the overall economic relationship."

Samsung debuted its Mach-1 generation of AI processors during a recent shareholder meeting—the South Korean megacorp anticipates an early 2025 launch window. Their application-specific integrated circuit (ASIC) design is expected to "excel in edge computing applications," with a focus on low power and efficiency-oriented operating environments. Naver Corporation was a key NVIDIA high-end AI customer in South Korea (and Japan), but the leading search platform firm and creator of HyperCLOVA X LLM (reportedly) deliberated on an adoption alternative hardware last October. The Korea Economic Daily believes that Naver's relationship with Samsung is set to grow, courtesy of a proposed $752 million investment: "the world's top memory chipmaker, will supply its next-generation Mach-1 artificial intelligence chips to Naver Corp. by the end of this year."

Reports from last December indicated that the two companies were deep into the process of co-designing power-efficient AI accelerators—Naver's main goal is to finalize a product that will offer eight times more energy efficiency than NVIDIA's H100 AI accelerator. Naver's alleged bulk order—of roughly 150,000 to 200,000 Samsung Mach-1 AI chips—appears to be a stopgap. Industry insiders reckon that Samsung's first-gen AI accelerator is much cheaper when compared to NVIDIA H100 GPU price points—a per-unit figure of $3756 is mentioned in the KED Global article. Samsung is speculated to be shopping its fledgling AI tech to Microsoft and Meta.