Marvell Technology, Inc., a leader in data infrastructure semiconductor solutions, has demonstrated its first 2 nm silicon IP for next-generation AI and cloud infrastructure. Produced on TSMC's 2 nm process, the working silicon is part of the Marvell platform for developing custom XPUs, switches and other technology to help cloud service providers elevate the performance, efficiency, and economic potential of their worldwide operations.

Given a projected 45% TAM growth annually, custom silicon is expected to account for approximately 25% of the market for accelerated compute by 20281.

On February 27-28, the 2025 China RISC-V Ecosystem Conference was grandly held at the Zhongguancun International Innovation Center in Beijing. As a core promoter in the RISC-V field, SOPHGO was invited to deliver a speech and prominently launch a series of new products based on the SG2044 chip, sharing the company's cutting-edge practices in the heterogeneous fusion of AI and RISC-V, and contributing to the vigorous development of the global open-source instruction set ecosystem. During the conference, SOPHGO set up a distinctive exhibition area that attracted many attendees from the industry to stop and watch.

Focusing on AI Integration, Leading Breakthroughs in RISC-V Technology
At the main forum of the conference, the Vice President of SOPHGO RISC-V delivered a speech titled "RISC-V Breakthroughs Driven by AI: Integration + Heterogeneous Innovation," where he elaborated on SOPHGO's innovative achievements in the deep integration of RISC-V architecture and artificial intelligence technology. He pointed out that current AI technological innovations are driving market changes, and the emergence of DeepSeek has ignited a trillion-level computing power market. The innovation of technical paradigms and the penetration of large models into various sectors will lead to an explosive growth in inference demand, resulting in changes in the structure of computing power demand. This will also reshape the landscape of the computing power market, bringing significant business opportunities to domestic computing power enterprises, while RISC-V high-performance computing is entering a fast track of development driven by AI.

GlobalFoundries (GF) and the Massachusetts Institute of Technology (MIT) today announced a new master research agreement to jointly pursue advancements and innovations for enhancing the performance and efficiency of critical semiconductor technologies. The collaboration will be led by MIT's Microsystems Technology Laboratories (MTL) and GF's research and development team, GF Labs.

With an initial research focus on AI and other applications, the first projects are expected to leverage GF's differentiated silicon photonics technology, which monolithically integrates RF SOI, CMOS and optical features on a single chip to realize power efficiencies for datacenters, and GF's 22FDX platform, which delivers ultra-low power consumption for intelligent devices at the edge.

Today, Amazon Web Services (AWS) announced Ocelot, a new quantum computing chip that can reduce the costs of implementing quantum error correction by up to 90%, compared to current approaches. Developed by the team at the AWS Center for Quantum Computing at the California Institute of Technology, Ocelot represents a breakthrough in the pursuit to build fault-tolerant quantum computers capable of solving problems of commercial and scientific importance that are beyond the reach of today's conventional computers.

AWS used a novel design for Ocelot's architecture, building error correction in from the ground up and using the 'cat qubit'. Cat qubits-named after the famous Schrödinger's cat thought experiment-intrinsically suppress certain forms of errors, reducing the resources required for quantum error correction. Through this new approach with Ocelot, AWS researchers have, for the first time, combined cat qubit technology and additional quantum error correction components onto a microchip that can be manufactured in a scalable fashion using processes borrowed from the microelectronics industry.

Today, the Open Compute Project Foundation (OCP), the nonprofit organization bringing hyperscale innovations to all, and JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, announce the availability of new Chiplet Design Kits for use with today's EDA tools covering Assembly, Substrate, Material and Test developed in collaboration within the OCP Open Chiplet Economy Project. Leveraging the alliance between OCP and JEDEC, these design kits are now part of the Global Worldwide Standard JEDEC JEP30: Part Model Guidelines.

The release of the Assembly, Substrate, Material, and Test Design Kits build on earlier joint efforts between the OCP and JEDEC integrating OCP Chiplet Data Extensible Markup Language (CDXML) specification into JEDEC JEP30: Part Model Guidelines, enabling Chiplet builders to provide electronically a standardized Chiplet part description to their customers, paving the way for automating System-in-Package (SiP) design and build using Chiplets.

Baya Systems, a leader in system IP technology that empowers the acceleration of intelligent compute, and Semidynamics, a provider of fully customizable high-bandwidth and high-performance RISC-V processor IP, today announced a collaboration to boost innovation in development of hyper-efficient, next-generation platforms for artificial intelligence (AI), machine learning (ML) and high-performance computing (HPC) applications.

The collaboration integrates Semidynamics' family of 64-bit RISC-V processor IP cores, known for their exceptional memory bandwidth and configurability, with Baya Systems' innovative WeaveIP Network on Chip (NoC) system IP. WeaveIP is engineered for ultra-efficient, high-bandwidth, and low-latency data transport, crucial for the demands of modern workloads. Complementing this is Baya Systems' software-driven WeaverPro platform, which enables rapid system-level optimization, ensuring that key performance indicators (KPIs) are met based on real-world workloads while providing unparalleled design flexibility for future advancements.

Apple today announced its largest-ever spend commitment, with plans to spend and invest more than $500 billion in the U.S. over the next four years. This new pledge builds on Apple's long history of investing in American innovation and advanced high-skilled manufacturing, and will support a wide range of initiatives that focus on artificial intelligence, silicon engineering, and skills development for students and workers across the country.

"We are bullish on the future of American innovation, and we're proud to build on our long-standing U.S. investments with this $500 billion commitment to our country's future," said Tim Cook, Apple's CEO. "From doubling our Advanced Manufacturing Fund, to building advanced technology in Texas, we're thrilled to expand our support for American manufacturing. And we'll keep working with people and companies across this country to help write an extraordinary new chapter in the history of American innovation."

The global semiconductor manufacturing industry closed 2024 with strong fourth quarter results and solid year-on-year (YoY) growth across most of the key industry segments, SEMI announced today in its Q4 2024 publication of the Semiconductor Manufacturing Monitor (SMM) Report, prepared in partnership with TechInsights. The industry outlook is cautiously optimistic at the start of 2025 as seasonality and macroeconomic uncertainty may impede near-term growth despite momentum from strong investments related to AI applications.

After declining in the first half of 2024, electronics sales bounced back later in the year resulting in a 2% annual increase. Electronics sales grew 4% YoY in Q4 2024 and are expected to see a 1% YoY increase in Q1 2025 impacted by seasonality. Integrated circuit (IC) sales rose by 29% YoY in Q4 2024 and continued growth is expected in Q1 2025 with a 23% increase YoY as AI-fueled demand continues boosting shipments of high-performance computing (HPC) and datacenter memory chips.

Reports from Financial Times suggest Arm has plans to create its own CPU, set to hit the market in 2025 with Meta Platforms said to be one of the first customers. The chip is said to be a CPU for data center servers, with TSMC handling the manufacturing. However, when the Financial Times asked about this, SoftBank (the majority owner of Arm) and Meta stayed quiet, while Arm didn't give a statement. A Nikkei report from May 2024 suggested that a prototype AI processor chip would be completed by spring 2025 and available for sale by fall 2025, so the latest information from the Financial Times report feels like a confirmation of previous rumors.

Right now, Arm makes money by letting others use its instruction set and core designs to make their own chips. This new move could mean Arm will compete with its current customers. Sources in the industry say Arm is trying to win business from Qualcomm, with rumors that Arm has been bringing in executives from companies it works with to help develop this chip. While Qualcomm had talked in the past about giving Meta a data center CPU using Arm's design, it looks like Arm has won at least some of that deal. However, no technical or specification details are available currently for Arm's 1st in-house server CPU.

China's dominance in semiconductor equipment procurement is expected to face its first setback since 2021, with spending projected to decrease from $41 billion to $38 billion in 2025, according to semiconductor research firm TechInsights. This 6% decline marks a significant shift for the world's largest buyer of wafer fabrication equipment, whose purchases represented 40% of global sales in 2024. The downturn reflects mounting pressures from both market dynamics and geopolitical constraints. US export controls targeting advanced semiconductor capabilities have intensified while domestic chipmakers grapple with overcapacity in mature node segments. SMIC, China's leading foundry, has already signaled concerns about oversupply risks in this sector, where Chinese manufacturers have rapidly expanded their market share against Taiwanese competitors.

Despite these headwinds, Chinese equipment manufacturers have notably advanced domestic capability development. Naura Technology Group has emerged as the seventh-largest global equipment manufacturer, while AMEC continues to expand its international presence. However, critical gaps persist in China's semiconductor equipment ecosystem, particularly in lithography systems, where dependence on foreign suppliers like ASML remains high. TechInsights data reveals that Chinese companies supplied only 17% of testing tools and 10% of domestic assembly equipment in 2023. The spending reduction comes after a period of aggressive stockpiling prompted by US sanctions to limit Beijing's access to advanced chipmaking capabilities, especially those applicable to artificial intelligence and military applications. However, Chinese manufacturers have demonstrated resilience, with SMIC and Huawei successfully producing advanced chips through alternative, albeit more costly, manufacturing methods.

Going back a year, we started hearing about an OpenAI proprietary AI chip project—this (allegedly) highly ambitious endeavor included grand plans for a dedicated fabrication network. TSMC was reportedly in the equation, but indirectly laughed at the AI research organization's ardent requests. Fast-forward to the present day; OpenAI appears to be actively pursuing a proprietary GPU design through traditional means. A Reuters exclusive report points to 2025 being an important year for the company's aforementioned "in-house" AI chip—the publication believes that OpenAI's debut silicon design has reached the finalization stage. Insiders have divulged that the project is only months away from being submitted to TSMC for "taping out." The foundry's advanced 3-nanometer process technology is reported to be on the cards. A Reuters source reckons that the unnamed chip features: "a commonly used systolic array architecture with high-bandwidth memory (HBM)...and extensive networking capabilities."

Broadcom is reportedly assisting with the development of OpenAI's in-house design—we heard about rumored negotiations taking place last summer. Jim Keller's tempting offer—of creating an AI chip for less than $1 trillion—was ignored early last year; OpenAI has instead assembled its own internal team of industry veterans. The October 2024 news cycle posited that former Google TPU engineers were drafted in as team leaders, with a targeted mass production window scheduled for 2026. The latest Reuters news article reiterates this projected timeframe, albeit dependent on the initial tape going "smoothly." OpenAI's chip department has grown to around forty individuals with recent months, according to industry moles—a small number relative to the headcounts at "Google or Amazon's AI chip program."

Intel shared some news and updates about its upcoming CPU architectures during the Q4 earnings call. Intel confirmed that "Panther Lake", its next major CPU, is set to be released in late 2025. "Panther Lake" will use Intel's latest 18A manufacturing process and might be part of the Core Ultra 300 series. "Panther Lake" is rumored to combine next-generation "Cougar Cove" P-cores with existing "Skymont" E-cores both in the Compute complex, and in the SoC tile as low-power island E-cores. However, Intel hasn't confirmed if it will be available for desktop systems.

The following CPU architecture, "Nova Lake", is set to debut in 2026. Unlike "Panther Lake", we know "Nova Lake" will work on desktop computers. This suggests desktop users might need to wait until 2026 for an upgrade unless Intel surprises us with a desktop version of "Panther Lake" or an alternative option.

New technology from Chalmers University of Technology and the University of Gothenburg, Sweden, is helping the EU establish its own competitive computer manufacturing industry. Researchers have developed components critical for optimising on-chip memory, a key factor in enhancing the performance of next-generation computers.

The research leader, Professor Per Stenström, along with colleagues, has discovered new ways to make cache memory work smarter. A cache is a local memory that temporarily stores frequently accessed data, improving a computer's speed and performance. "Our solution enables computers to retrieve data significantly faster than before, as the cache can manage far more processing elements (PEs) than most existing systems. This makes it possible to meet the demands of tomorrow's powerful computers," says Per Stenström, Professor at the Department of Computer Science and Engineering at Chalmers University of Technology and the University of Gothenburg.

In the design of wearable devices, every millimeter matters. As AI technology becomes deeply integrated, wearable devices demand not only enhanced performance but also the ability to deliver more functionalities within highly limited spaces. Recently, Longsys introduced a 7.2 mm × 7.2 mm subsize eMMC, providing a groundbreaking memory solution for optimizing the physical space of AI wearables.

Ultra-Compact: Unlocking New Possibilities for Wearable Design
7.2 mm × 7.2 mm is one of the smallest subsize eMMCs currently available on the market, achieving maximum space efficiency. Its 153 solder balls nearly cover the entire panel, pushing the design to the very edge of physical limits. Compared to the standard 11.5 mm × 13 mm eMMC, its surface area is reduced by approximately 65%, with a thickness of just 0.8 mm. Featuring a lightweight design, it weighs only 0.1 g (approx.), nearly 67% lighter than the standard 0.3 g eMMC. This ultra-compact design frees up additional space for other internal components, enabling wearable devices to maintain a sleek and lightweight form while integrating more functional modules to meet diverse user demands.

Cadence today announced that MediaTek has adopted the AI-driven Cadence Virtuoso Studio and Spectre X Simulator on the NVIDIA accelerated computing platform for its 2 nm development. As design size and complexity continue to escalate, advanced-node technology development has become increasingly challenging for SoC providers. To meet the aggressive performance and turnaround time (TAT) requirements for its 2 nm high-speed analog IP, MediaTek is leveraging Cadence's proven custom/analog design solutions, enhanced by AI, to achieve a 30% productivity gain.

"As MediaTek continues to push technology boundaries for 2 nm development, we need a trusted design solution with strong AI-powered tools to achieve our goals," said Ching San Wu, corporate vice president at MediaTek. "Closely collaborating with Cadence, we have adopted the Cadence Virtuoso Studio and Spectre X Simulator, which deliver the performance and accuracy necessary to achieve our tight design turnaround time requirements. Cadence's comprehensive automation features enhance our throughput and efficiency, enabling our designers to be 30% more productive."

Montage Technology today announced the customer sampling of its PCIe 6.x/CXL 3.x Retimer -- M88RT61632, which is designed to enhance connectivity performance for demanding high-bandwidth applications such as AI and cloud computing. This milestone extends the company's PCIe product portfolio, building upon its successful PCIe 4.0 and PCIe 5.0/CXL 2.0 Retimer solutions.

The PCIe 6.x/CXL 3.x Retimer delivers excellent performance with data rates up to 64 GT/s, twice that of PCIe 5.0. Powered by Montage Technology's proprietary PAM4 SerDes IP, the chip achieves superior signal integrity with link budget up to 43dB while maintaining low latency. Its innovative DSP architecture effectively addresses PCIe 6.x system design challenges including crosstalk and signal reflection. In addition, the chip features advanced link training and enhanced telemetry, enabling comprehensive link monitoring and fault diagnostics for high-reliability AI cluster deployments.

Today, the U.S. Department of Commerce has announced that CHIPS National Advanced Packaging Manufacturing Program (NAPMP) has finalized $1.4 billion in award funding to bolster U.S. leadership in advanced packaging and enable new technologies to be validated and transitioned at scale to U.S. manufacturing. These awards will help establish a self-sustaining, high-volume, domestic, advanced packaging industry where advanced node chips are both manufactured and packaged in the United States.

These awards include:

• A total of $300 million under the CHIPS NAPMP's first Notice of Funding Opportunity (NOFO) for advanced substrates and material research to Absolics Inc., Applied Materials Inc., and Arizona State University. This follows the previously announced intent to enter negotiations on November 21, 2024
• $1.1 billion to Natcast to operate the advanced packaging capabilities of the CHIPS for America NSTC Prototyping and NAPMP Advanced Packaging Piloting Facility (PPF). This follows the previously announced CHIPS R&D Facilities Model on July 12, 2024, and planned site selection for the PPF on January 6, 2025

Digital Enhancement (Hangzhou) Co., Ltd (hereafter referred to as "Digital Enhancement") is set to unveil the world's first commercial-grade Radio Processing Unit (RPU) designed for Wi-Fi wireless access at the CES International Consumer Electronics Show in Las Vegas, USA.

This groundbreaking RPU and solution leverage Digital Enhancement's innovative "Digital RF" technology, delivering a 10x performance boost in Wi-Fi high-speed coverage. The innovation promises to redefine the wireless connectivity experience for consumer electronics, paving the way for a new era of seamless and high-performance wireless connections.

TSMC is making progress with its most advanced 2 nm (N2) node, a recent report from MoneyDJ quoting industry sources indicates that the company is setting up a test production line at the Hsinchu Baoshan fab (Fab 20) in Taiwan. In the early stages, TSMC aims for small monthly outputs with about 3,000-3,500 wafers. However, the company has big plans to combine production from two factories in Hsinchu and Kaohsiung, TSMC expects to deliver more than 50,000 wafers monthly by the end of 2025 and by the end of 2026 projecting a production of around 125,000 wafers per month. Breaking it down by location, the Hsinchu factory should reach 20,000-25,000 wafers monthly by late 2025, growing to about 60,000-65,000 by early 2027. Meanwhile, the Kaohsiung factory is expected to produce 25,000-30,000 wafers monthly by late 2025, also increasing to 60,000-65,000 by early 2027.

TSMC's chairman C.C. Wei says there's more demand for these 2 nm chips than there was for the 3 nm. This increased "appetite" for 2 nm chips is likely due to the significant improvements this technology brings: it uses 24-35% less power, can run 15% faster at the same power level, and can fit 15% more transistors in the same space compared to the 3 nm chips. Apple will be the first company to use these chips, followed by other major tech companies like MediaTek, Qualcomm, Intel, NVIDIA, AMD, and Broadcom.

Intel and AMD are both widely expected to hit the market with new high-performance mobile chips at CES 2025. We expect Team Blue to lift the curtains on its Core Ultra 200H and 200HX lineup, whereas Team Red will strike back with its Strix Halo products, a few of which were leaked recently with promising performance. However, that's not all that we expect from the x86 behemoths, as both are poised to introduce mid-range and budget offerings as well.

Interestingly, it appears that Intel has already pulled back the veil on its Raptor Lake-H Refresh-based Core 200H lineup, which has been revealed as the Core Processor series. The lineup consists of mostly rebadged Raptor Lake-H chips, with some confusing choices. The products, based on the Intel 7 node, are as follows.

The pilot line for "Advanced Packaging and Heterogeneous Integration for Electronic Components and Systems" (APECS) marks a major leap forward in strengthening Europe's semiconductor manufacturing capabilities and chiplet innovation as part of the EU Chips Act. By providing large industry players, SMEs, and start-ups with a facilitated access to cutting-edge technology, the APECS pilot line will establish a strong foundation for resilient and robust European semiconductor supply chains. Within APECS, the institutes collaborating in the Research Fab Microelectronics Germany (FMD) will work closely with European partners, to make a significant contribution to the European Union's goals of increasing technological resilience, strengthening cross-border collaboration and enhancing its global competitiveness in semiconductor technologies. APECS is co-funded by the Chips Joint Undertaking and national funding authorities of Austria, Belgium, Finland, France, Germany, Greece, Portugal, Spain, through the "Chips for Europe" initiative. The overall funding for APECS amounts to €730 million over 4.5 years.

Europe is home to a vibrant ecosystem of (hidden) champions, from traditional enterprises in vertical markets, to SMEs and start-ups the competitive advantages of which lie in superior semiconductor-based solutions. Nevertheless, many of these companies are currently confronted with limited access to advanced semiconductor technologies, while at the same time these technologies are increasingly becoming the most important factor for innovation and market growth.

China has announced the development of its latest quantum system, combining the Xiaohong-504, a 504-qubit superconducting quantum chip, with the Tianyan-504 quantum computer. The breakthrough comes from China Telecom Quantum Group (CTQG), which will use the new supercomputer to boost national telecommunications security. The Xiaohong-504 chip reportedly demonstrates impressive specifications in critical areas including qubit lifetime, gate fidelity, and circuit depth, comparable with established quantum platforms such as IBM. The first Xiaohong-504 processor is scheduled for delivery to QuantumCTek, a quantum technology company based in Anhui Province, where it will begin extensive testing of kilo-qubit measurement and control systems.

While the Tianyan-504 represents a major achievement, it currently ranks behind some international competitors in terms of qubit count. Atom Computing's 1,180-qubit prototype was revealed in late 2023, and IBM's 1,121-qubit Condor processor maintains the lead in raw qubit numbers. The development of the Tianyan-504 was a collaborative effort between CTQG, the Chinese Academy of Sciences, and QuantumCTek. The system will be integrated into the Tianyan quantum cloud platform, which has already demonstrated significant international reach since its launch in November 2023, attracting more than 12 million visits from users across over 50 countries. Rather than focusing solely on achieving quantum supremacy, the Tianyan-504 project aim is developing infrastructure for large-scale quantum systems.

AMD today announced the expansion of the AMD Versal adaptive system-on-chip (SoC) portfolio with the introduction of the Versal RF Series that includes the industry's highest compute performance in a single-chip device with integrated direct radio frequency (RF)-sampling data converters.

Versal RF Series offers precise, wideband-spectrum observability and up to 80 TOPS of digital signal processing (DSP) performance in a size, weight, and power (SWaP)-optimized design, targeting RF systems and test equipment applications in the aerospace and defense (A&D) and test and measurement (T&M) markets, respectively.

Today at the IEEE International Electron Devices Meeting (IEDM) 2024, Intel Foundry unveiled new breakthroughs to help drive the semiconductor industry forward into the next decade and beyond. Intel Foundry showcased new material advancements that help improve interconnections within a chip, resulting in up to 25% capacitance by using subtractive ruthenium. Intel Foundry also was first to report a 100x throughput improvement using a heterogeneous integration solution for advanced packaging to enable ultra-fast chip-to-chip assembly. And to further drive gate-all-around (GAA) scaling, Intel Foundry demonstrated work with silicon RibbonFET CMOS and with gate oxide module for scaled 2D FETs for improved device performance.

"Intel Foundry continues to help define and shape the roadmap for the semiconductor industry. Our latest breakthroughs underscore the company's commitment to delivering cutting-edge technology developed in the U.S., positioning us well to help balance the global supply chain and restore domestic manufacturing and technology leadership with the support of the U.S. CHIPS Act," says Sanjay Natarajan, Intel senior vice president and general manager of Intel Foundry Technology Research.

Broadcom Inc. today announced the availability of its 3.5D eXtreme Dimension System in Package (XDSiP) platform technology, enabling consumer AI customers to develop next-generation custom accelerators (XPUs). The 3.5D XDSiP integrates more than 6000 mm² of silicon and up to 12 high bandwidth memory (HBM) stacks in one packaged device to enable high-efficiency, low-power computing for AI at scale. Broadcom has achieved a significant milestone by developing and launching the industry's first Face-to-Face (F2F) 3.5D XPU.

The immense computational power required for training generative AI models relies on massive clusters of 100,000 growing to 1 million XPUs. These XPUs demand increasingly sophisticated integration of compute, memory, and I/O capabilities to achieve the necessary performance while minimizing power consumption and cost. Traditional methods like Moore's Law and process scaling are struggling to keep up with these demands. Therefore, advanced system-in-package (SiP) integration is becoming crucial for next-generation XPUs. Over the past decade, 2.5D integration, which involves integrating multiple chiplets up to 2500 mm² of silicon and HBM modules up to 8 HBMs on an interposer, has proven valuable for XPU development. However, as new and increasingly complex LLMs are introduced, their training necessitates 3D silicon stacking for better size, power, and cost. Consequently, 3.5D integration, which combines 3D silicon stacking with 2.5D packaging, is poised to become the technology of choice for next-generation XPUs in the coming decade.