Intel and AMD are both widely expected to hit the market with new high-performance mobile chips at CES 2025. We expect Team Blue to lift the curtains on its Core Ultra 200H and 200HX lineup, whereas Team Red will strike back with its Strix Halo products, a few of which were leaked recently with promising performance. However, that's not all that we expect from the x86 behemoths, as both are poised to introduce mid-range and budget offerings as well.

Interestingly, it appears that Intel has already pulled back the veil on its Raptor Lake-H Refresh-based Core 200H lineup, which has been revealed as the Core Processor series. The lineup consists of mostly rebadged Raptor Lake-H chips, with some confusing choices. The products, based on the Intel 7 node, are as follows.

The pilot line for "Advanced Packaging and Heterogeneous Integration for Electronic Components and Systems" (APECS) marks a major leap forward in strengthening Europe's semiconductor manufacturing capabilities and chiplet innovation as part of the EU Chips Act. By providing large industry players, SMEs, and start-ups with a facilitated access to cutting-edge technology, the APECS pilot line will establish a strong foundation for resilient and robust European semiconductor supply chains. Within APECS, the institutes collaborating in the Research Fab Microelectronics Germany (FMD) will work closely with European partners, to make a significant contribution to the European Union's goals of increasing technological resilience, strengthening cross-border collaboration and enhancing its global competitiveness in semiconductor technologies. APECS is co-funded by the Chips Joint Undertaking and national funding authorities of Austria, Belgium, Finland, France, Germany, Greece, Portugal, Spain, through the "Chips for Europe" initiative. The overall funding for APECS amounts to €730 million over 4.5 years.

Europe is home to a vibrant ecosystem of (hidden) champions, from traditional enterprises in vertical markets, to SMEs and start-ups the competitive advantages of which lie in superior semiconductor-based solutions. Nevertheless, many of these companies are currently confronted with limited access to advanced semiconductor technologies, while at the same time these technologies are increasingly becoming the most important factor for innovation and market growth.

China has announced the development of its latest quantum system, combining the Xiaohong-504, a 504-qubit superconducting quantum chip, with the Tianyan-504 quantum computer. The breakthrough comes from China Telecom Quantum Group (CTQG), which will use the new supercomputer to boost national telecommunications security. The Xiaohong-504 chip reportedly demonstrates impressive specifications in critical areas including qubit lifetime, gate fidelity, and circuit depth, comparable with established quantum platforms such as IBM. The first Xiaohong-504 processor is scheduled for delivery to QuantumCTek, a quantum technology company based in Anhui Province, where it will begin extensive testing of kilo-qubit measurement and control systems.

While the Tianyan-504 represents a major achievement, it currently ranks behind some international competitors in terms of qubit count. Atom Computing's 1,180-qubit prototype was revealed in late 2023, and IBM's 1,121-qubit Condor processor maintains the lead in raw qubit numbers. The development of the Tianyan-504 was a collaborative effort between CTQG, the Chinese Academy of Sciences, and QuantumCTek. The system will be integrated into the Tianyan quantum cloud platform, which has already demonstrated significant international reach since its launch in November 2023, attracting more than 12 million visits from users across over 50 countries. Rather than focusing solely on achieving quantum supremacy, the Tianyan-504 project aim is developing infrastructure for large-scale quantum systems.

AMD today announced the expansion of the AMD Versal adaptive system-on-chip (SoC) portfolio with the introduction of the Versal RF Series that includes the industry's highest compute performance in a single-chip device with integrated direct radio frequency (RF)-sampling data converters.

Versal RF Series offers precise, wideband-spectrum observability and up to 80 TOPS of digital signal processing (DSP) performance in a size, weight, and power (SWaP)-optimized design, targeting RF systems and test equipment applications in the aerospace and defense (A&D) and test and measurement (T&M) markets, respectively.

Today at the IEEE International Electron Devices Meeting (IEDM) 2024, Intel Foundry unveiled new breakthroughs to help drive the semiconductor industry forward into the next decade and beyond. Intel Foundry showcased new material advancements that help improve interconnections within a chip, resulting in up to 25% capacitance by using subtractive ruthenium. Intel Foundry also was first to report a 100x throughput improvement using a heterogeneous integration solution for advanced packaging to enable ultra-fast chip-to-chip assembly. And to further drive gate-all-around (GAA) scaling, Intel Foundry demonstrated work with silicon RibbonFET CMOS and with gate oxide module for scaled 2D FETs for improved device performance.

"Intel Foundry continues to help define and shape the roadmap for the semiconductor industry. Our latest breakthroughs underscore the company's commitment to delivering cutting-edge technology developed in the U.S., positioning us well to help balance the global supply chain and restore domestic manufacturing and technology leadership with the support of the U.S. CHIPS Act," says Sanjay Natarajan, Intel senior vice president and general manager of Intel Foundry Technology Research.

Broadcom Inc. today announced the availability of its 3.5D eXtreme Dimension System in Package (XDSiP) platform technology, enabling consumer AI customers to develop next-generation custom accelerators (XPUs). The 3.5D XDSiP integrates more than 6000 mm² of silicon and up to 12 high bandwidth memory (HBM) stacks in one packaged device to enable high-efficiency, low-power computing for AI at scale. Broadcom has achieved a significant milestone by developing and launching the industry's first Face-to-Face (F2F) 3.5D XPU.

The immense computational power required for training generative AI models relies on massive clusters of 100,000 growing to 1 million XPUs. These XPUs demand increasingly sophisticated integration of compute, memory, and I/O capabilities to achieve the necessary performance while minimizing power consumption and cost. Traditional methods like Moore's Law and process scaling are struggling to keep up with these demands. Therefore, advanced system-in-package (SiP) integration is becoming crucial for next-generation XPUs. Over the past decade, 2.5D integration, which involves integrating multiple chiplets up to 2500 mm² of silicon and HBM modules up to 8 HBMs on an interposer, has proven valuable for XPU development. However, as new and increasingly complex LLMs are introduced, their training necessitates 3D silicon stacking for better size, power, and cost. Consequently, 3.5D integration, which combines 3D silicon stacking with 2.5D packaging, is poised to become the technology of choice for next-generation XPUs in the coming decade.

Intel Corporation today announced that Eric Meurice, former president, chief executive officer and chairman of ASML Holding N.V., and Steve Sanghi, chairman and interim chief executive officer of Microchip Technology Inc., have been appointed to Intel's board of directors, effective immediately. Both will serve as independent directors.

"Eric and Steve are highly respected leaders in the semiconductor industry whose deep technical expertise, executive experience and operational rigor make them great additions to the Intel board," said Frank D. Yeary, interim executive chair of the Intel board. "As successful CEOs with proven track records of creating shareholder value, they will bring valuable perspectives to the board as the company delivers on its priorities for customers in Intel Products and Intel Foundry, while driving greater efficiency and improving profitability."

SK Hynix plans to produce its 6th generation high-bandwidth memory chips (HBM4) using TSMC's 3 nm process, a change from initial plans to use the 5 nm technology. The Korea Economic Daily reports that these chips will be delivered to NVIDIA in the second half of 2025. NVIDIA's GPU products are currently based on 4 nm HBM chips. The HBM4 prototype chip launched in March by SK Hynix features vertical stacking on a 3 nm die., compared to a 5 nm base die, the new 3 nm-based HBM chip is expected to offer a 20-30% performance improvement. However, SK Hynix's general-purpose HBM4 and HBM4E chips will continue to use the 12 nm process in collaboration with TSMC.

While SK Hynix's fifth-generation HBM3E chips used its own base die technology, the company has chosen TSMC's 3 nm technology for HBM4. This decision is anticipated to significantly widen the performance gap with competitor Samsung Electronics, which plans to manufacture its HBM4 chips using the 4 nm process. SK hynix is currently leading the global HBM market with almost 50% of market share, most of its HBM products been delivered to NVIDIA.

Germany is set to invest €2 billion in the semiconductor industry after recent setbacks, according to TrendForce via Liberty Times citing Bloomberg. The German government's new funding is in response to the chip sector's problems, including Intel's delay of the Magdeburg factory and global disruptions in the semiconductor supply chain. The investment will support 10 to 15 projects from wafer production to microchip assembly to strengthen Germany's and Europe's microelectronics ecosystem. This is in line with the European Chips Act which aims to increase the EU's global production capacity to 20% by 2030.

Intel's €30 billion Magdeburg factory delay and other cancelled chip projects from Wolfspeed and ZF Friedrichshafen AG have created uncertainty in the German market. The Ministry of Economic Affairs is now calling for new applications for funding, with up to €3 billion available. The timing of the semiconductor investment follows the global supply chain disruptions caused by the pandemic and the increasing geopolitical tensions between the US, China and Taiwan. Germany is following a broader trend of governments investing in local semiconductor production to increase technological independence and economic resilience. The funding is subject to budget reallocation with the new government after February 2025 elections. In the first round of subsidies from the European Chips Act, Germany allocated resources to two key initiatives: Intel's investment and a collaborative project between Infineon and TSMC in Dresden.

AMD has recently filed a patent revealing plans to implement "multi-chip stacking" in future Ryzen SoCs, as Wccftech reports, quoting a post on X from @coreteks: "New patent from AMD shows how future Zen SoCs could look. Basically a novel packaging design that enables compact chip stacking and interconnection by having them partially overlap, as in this figure. The dotted line is a larger die stacked on top of those smaller ones". The patent details a new approach where smaller chiplets partially overlap with a larger die, creating space for additional components and functions on the same die. This strategy aims to improve the efficiency of the contact area, thus making room for higher core counts, larger caches, and increased memory bandwidth within the same die size. The proposed stacking will reduce the physical distance between components through overlapping chiplets, thus minimizing interconnect latency and achieving faster communication between different chip parts. The design will also improve power management, as the segregated chiplets allow for better control of each unit through power gating.

Even if long-time rival Intel has lost some of its momentum (and market share) this year, AMD's chance to push ahead with its intention to become number one in the market is to continue to innovate. In the same way that its 3D V-Cache technology made the X3D processor lineup so successful, this chip stacking approach could play a major role in future AMD Ryzen SoCs. It seems that AMD is committed to moving away from the monolithic design era and taking the road of multi-chiplet; however, it can be a long wait until (and if) this chip stacking will complete the journey from patents to design, production, and final product.

For over half a century, general-purpose processors have been built on the Tomasulo algorithm, developed by IBM engineer Robert Tomasulo in 1967. It's a $500B industry built on specialized CPU, GPU and other chips for different computing tasks. Hardware startup Ubitium has shattered this paradigm with a breakthrough universal processor that handles all computing workloads on a single, efficient chip - unlocking simpler, smarter, and more cost-effective devices across industries - while revolutionizing a 57-year-old industry standard.

Alongside this, Ubitium is announcing a $3.7 million in seed funding round, co-led by Runa Capital, Inflection, and KBC Focus Fund. The investment will be used to develop the first prototypes and prepare initial development kits for customers, with the first chips planned for 2026.

Renesas Electronics Corporation, a premier supplier of advanced semiconductor solutions, today announced that it has delivered the industry's first complete memory interface chipset solutions for the second-generation DDR5 Multi-Capacity Rank Dual In-Line Memory Modules (MRDIMMs).

The new DDR5 MRDIMMs are needed to keep pace with the ever-increasing memory bandwidth demands of Artificial Intelligence (AI), High-Performance Compute (HPC) and other data center applications. They deliver operating speeds up to 12,800 Mega Transfers Per Second (MT/s), a 1.35x improvement in memory bandwidth over first-generation solutions. Renesas has been instrumental in the design, development and deployment of the new MRDIMMs, collaborating with industry leaders including CPU and memory providers, along with end customers.

d-Matrix today unveiled Corsair, an entirely new computing paradigm designed from the ground-up for the next era of AI inference in modern datacenters. Corsair leverages d-Matrix's innovative Digital In-Memory Compute architecture (DIMC), an industry first, to accelerate AI inference workloads with industry-leading real-time performance, energy efficiency, and cost savings as compared to GPUs and other alternatives.

The emergence of reasoning agents and interactive video generation represents the next level of AI capabilities. These leverage more inference computing power to enable models to "think" more and produce higher quality outputs. Corsair is the ideal inference compute solution with which enterprises can unlock new levels of automation and intelligence without compromising on performance, cost or power.

Q.ANT, the leading startup for photonic computing, today announced the launch of its first commercial product - a photonics-based Native Processing Unit (NPU) built on the company's compute architecture LENA - Light Empowered Native Arithmetics. The product is fully compatible with today's existing computing ecosystem as it comes on the industry-standard PCI-Express. The Q.ANT NPU executes complex, non-linear mathematics natively using light instead of electrons, promising to deliver at least 30 times greater energy efficiency and significant computational speed improvements over traditional CMOS technology. Designed for compute-intensive applications such as AI Inference, machine learning, and physics simulation, the Q.ANT NPU has been proven to solve real-world challenges, including number recognition for deep neural network inference (see the recent press release regarding Cloud Access to NPU).

"With our photonic chip technology now available on the standard PCIe interface, we're bringing the incredible power of photonics directly into real-world applications. For us, this is not just a processor—it's a statement of intent: Sustainability and performance can go hand in hand," said Dr. Michael Förtsch, CEO of Q.ANT. "For the first time, developers can create AI applications and explore the capabilities of photonic computing, particularly for complex, nonlinear calculations. For example, experts calculated that one GPT-4 query today uses 10 times more electricity than a regular internet search request. Our photonic computing chips offer the potential to reduce the energy consumption for that query by a factor of 30."

Japan has proposed a $65 billion (or more) plan to strengthen the semiconductor and AI industries in the country through grants and financial support by fiscal year 2030. The government plans to present this proposal at the next parliamentary session. The draft includes support for mass production of next-generation chips, focusing on AI chipmakers such as Rapidus, the government estimates an economic impact of about 160 trillion yen from this investment. Rapidus plans to start mass production of advanced chips in Hokkaido from 2027 and will work with IBM and Belgian research organization Imec.

According to the report from Reuters, Prime Minister Shigeru Ishiba said the government would not issue deficit-financing bonds to fund the support plan, although specific financial details are not yet known. The new initiative builds on last year's 2 trillion yen investment in the chip industry, and it is part of a broader economic package. Expected to be approved by the Cabinet on November 22, the plan calls for combined public and private investment in the semiconductor industry of more than 50 trillion yen over the next decade.

LG Electronics (LG) and Tenstorrent are pleased to announce an expanded collaboration, building on their initial chiplet project to develop System-on-Chips (SoCs) and systems for the global market. Through this partnership, LG aims to enhance its design and development capabilities for AI chips tailored to its products and services, aligning with its vision of "Affectionate Intelligence." LG is dedicated to advancing AI-driven innovation, with a focus on enhancing its AI-powered home appliances and smart home solutions, as well as expanding its capabilities in future mobility and commercial applications.

Recognizing the critical role of high-performance AI semiconductors in implementing AI technology, LG plans to strengthen its in-house development capabilities while collaborating with leading global companies, including Tenstorrent, to boost its AI competitiveness.

Both pictures and videos of a partial teardown of Apple's recently launched Mac mini with the M4 SoC have appeared online courtesy of various Chinese sources. There are at least two interesting parts to these partial teardowns and they're related to storage and WiFi. On the storage front, Apple has moved away from having soldered NAND chips straight on the main PCB of the Mac mini, to instead having them on a custom PCB which is similar to M.2, but a custom Apple design. The PCB pictured contained a pair of 128 GB NAND chips and with the source of the teardown being from China, there's also a video showing a repair shop desoldering the two chips and replacing them with two 1 TB chips, or in other words, the SSD was upgraded from 256 GB to 2 TB.

The upgrade brought with it some extra performance as well, even if the write speed remained at a comparatively slow 2900 MB/s, the read speed went up from 2000 MB/s to 3300 MB/s which is a significant gain in performance. This is obviously not a consumer friendly upgrade path, but we'd expect to see third party upgrade options at some point in the future, assuming there's no black listing of third party storage modules. The NAND controller is still likely to be integrated into Apple's SoC, but the PCB that the NAND flash chips are mounted onto appears to have some kind of SPI flash on it as well, which might make third party upgrades a lot harder.

The 8th edition of the Samsung AI Forum was held on November 4th and 5th in Seoul, and among all the presentations and keynote speeches, one piece of information caught our attention. As reported by The Chosun Daily, Samsung is (again) turning its attention to Processing-in-Memory (PIM) technology, in what appears to be the company's latest attempt to keep up with its rival SK Hynix in this area. In 2021, Samsung introduced the world's first HBM-PIM, the chips showing impressive gains in performance (nearly double) while reducing energy consumption by almost 50% on average. PIM technology basically adds the processor functions necessary for computational tasks, reducing data transfer between the CPU and memory.

Now, the company hopes that PIM memory chips could replace HBM in the future, based on the advantages this next-generation memory technology possesses, mainly for artificial intelligence (AI) applications. "AI is transforming our lives at an unprecedented rate, and the question of how to use AI more responsibly is becoming increasingly important," said Samsung Electronics CEO Han Jong-hee in his opening remarks. "Samsung Electronics is committed to fostering a more efficient and sustainable AI ecosystem." During the event, Samsung also highlighted its partnership with AMD, which reportedly supplies AMD with its fifth-generation HBM, the HBM3E.

SK hynix announced the first 48 GB 16-high HBM3E in the industry at the SK AI Summit in Seoul today. During the event, news came out about newer plans to develop their next-gen memory tech. Reuters and ZDNet Korea reported that NVIDIA CEO Jensen Huang asked SK hynix to speed up their HBM4 delivery by six months. SK Group Chairman Chey Tae-won shared this info at the Summit. The company had earlier said they would give HBM4 chips to customers in the second half of 2025.

When ZDNet asked about this sped-up plan, SK hynix President Kwak Noh-Jung gave a careful answer saying "We will give it a try." A company spokesperson told Reuters that this new schedule would be quicker than first planned, but they didn't share more details. In a video interview shown at the Summit, NVIDIA's Jensen Huang pointed out the strong team-up between the companies. He said working with SK hynix has helped NVIDIA go beyond Moore's Law performance gains. He stressed that NVIDIA will keep needing SK hynix's HBM tech for future products. SK hynix plans to supply the latest 12-layer HBM3E to an undisclosed customer this year, and will start sampling of the 16-layer HBM3E early next year.

Today, the Department of Commerce and Natcast, the operator of the National Semiconductor Technology Center (NSTC), announced the expected location for the first CHIPS for America research and development (R&D) flagship facility. The CHIPS for America Extreme Ultraviolet (EUV) Accelerator, an NSTC facility (EUV Accelerator), is expected to operate within NY CREATES' Albany NanoTech Complex in Albany, New York, supported by a proposed federal investment of an estimated $825 million. The EUV Accelerator will focus on advancing state of the art EUV technology and the R&D that relies on it.

As a key part of President Biden's Investing in America agenda, CHIPS for America is driven by the growing need to bolster the U.S. semiconductor supply chain, accelerate U.S. leading-edge R&D, and create good quality jobs around the country. This proposed facility will bring together NSTC members from across the ecosystem to accelerate semiconductor R&D and innovation by providing NSTC members access to technologies, capabilities, and critical resources.

Today, AMD unveiled new desktop computing products, delivering enhanced performance for gamers. The lineup features the new AMD Ryzen 7 9800X3D Desktop processor, based on the "Zen 5" architecture and utilizing 2nd Gen AMD 3D V-Cache technology.

With the AMD Ryzen 7 9800X3D processor, AMD has re-engineered its cutting-edge on-chip memory solution with 2nd Gen AMD 3D V-Cache technology. The 64 MB cache memory has been relocated below the processor, which puts the core complex die (CCD) closer to the cooling solution to help keep the "Zen 5" cores cooler, delivering high clock rates and providing up to an average 8% gaming performance improvement compared to our last-gen generation and up to an average 20% faster than the competition. This revolutionary change in placement allows for extreme overclocking of the processor. It's the first X3D processor to be fully unlocked, empowering enthusiasts and gamers to push its performance to new limits.

Today, Cisco announced new additions to its data center infrastructure portfolio: an AI server family purpose-built for GPU-intensive AI workloads with NVIDIA accelerated computing, and AI PODs to simplify and de-risk AI infrastructure investment. They give organizations an adaptable and scalable path to AI, supported by Cisco's industry-leading networking capabilities.

"Enterprise customers are under pressure to deploy AI workloads, especially as we move toward agentic workflows and AI begins solving problems on its own," said Jeetu Patel, Chief Product Officer, Cisco. "Cisco innovations like AI PODs and the GPU server strengthen the security, compliance, and processing power of those workloads as customers navigate their AI journeys from inferencing to training."

Samsung is currently mass-producing its 9th generation V-NAND flash memory chips with 286 layers unveiled this April. According to the Korean Economic Daily, the company targets V-NAND memory chips with at least 400 stacked layers by 2026. In 2013, Samsung became the first company to introduce V-NAND chips with vertically stacked memory cells to maximize capacity. However, stacking beyond 300 levels proved to be a real challenge with the memory chips getting frequently damaged. To address this problem, Samsung is reportedly developing an improved 10th-generation V-NAND that is going to use the Bonding Vertical (BV) NAND technology. The idea is to manufacture the storage and peripheral circuits on separate layers before bonding them vertically. This is a major shift from the current Co-Packaged (CoP) technology. Samsung stated that the new method will increase the density of bits per unit area by 1.6 times (60%), thus leading to increased data speeds.

Samsung's roadmap is truly ambitious, with plans to launch the 11th generation of NAND in 2027 with an estimated 50% improvement in I/O rates, followed by 1,000-layer NAND chips by 2030. Its competitor, SK hynix, is also working on 400-layer NAND aiming to have the technology ready for mass production by the end of 2025, as we previously mentioned in August. Samsung, the current HBM market leader with a 36.9% market share have also plans for its DRAM sector intending to introduce the sixth-generation 10 nm DRAM, or 1c DRAM by the first half of 2025. Then we can expect to see Samsung's seventh-generation 1d nm (still on 10 nm) in 2026, and by 2027 the company hopes to release its first generation sub-10 nm DRAM, or 0a DRAM memory that will use a Vertical Channel Transistor (VCT) 3D structure similar to what NAND flash utilizes.

Intel has plans to expands its chip packaging and testing operations in Chengdu, China. The company will put $300 million into Intel Products (Chengdu), as stated in a WeChat post by Chengdu's Reform and Development Commission, and reported by TrendForce. Intel announced its Chengdu plant in August 2003 as a semiconductor chip packaging and testing facility in the Chengdu Hi-Tech West Zone. The first phase began in February 2004 with the construction of a chipset factory, which was completed and put into production by the end of 2005. The second phase commenced in August 2005 and was completed in October 2006. By 2007, the packaging and testing facility was fully operational, handling Intel's most advanced processors.

Since its launch in 2003, Intel's Chengdu plant has handled over half of the packaging and testing for Intel's laptop processors. Even with rising US-China tensions, China remains Intel's biggest market making up 27 percent of its total income last year. The announced expansion will increase the packaging and testing ability of server chips and will add a new "customer solutions center." This center aims to make the supply chain more effective, give more support to Chinese customers, and speed up response times. Intel's Chengdu site plays a key role in the company's global supply chain, benefiting from the area's "favorable" business climate, CEO Patrick Gelsinger said during his visit last year.

G.SKILL International Enterprise Co., Ltd., the world's leading brand of performance overclock memory and PC components, is excited to announce the launch of Trident Z5 CK and Trident Z5 CK RGB series extreme overclock DDR5 CU-DIMM memory, featuring a built-in clock driver (CKD) and available up to a blistering overclock speed of DDR5-9600. Designed for use with the latest Intel Core Ultra 200 K-series desktop processors and Intel Z890 chipset motherboards, the Trident Z5 CK and Trident Z5 CK RGB series comes with mirrored black finish heatspreaders and pushes the boundaries of memory overclock to new heights. The Trident Z5 CK and Trident Z5 CK RGB series DDR5-9600 memory kits are currently listed on Newegg.com.

DDR5 CU-DIMM - The New Generation of DDR5 Memory
The Trident Z5 CK and Trident Z5 CK RGB series is built on the new CU-DIMM standard, which introduces a built-in clock driver (CKD) chip on the memory module. Designed to strengthen signals between the CPU and memory IC chips, the CKD helps in improving stability in high-speed memory operations.