Intel shared some news and updates about its upcoming CPU architectures during the Q4 earnings call. Intel confirmed that "Panther Lake", its next major CPU, is set to be released in late 2025. "Panther Lake" will use Intel's latest 18A manufacturing process and might be part of the Core Ultra 300 series. "Panther Lake" is rumored to combine next-generation "Cougar Cove" P-cores with existing "Skymont" E-cores both in the Compute complex, and in the SoC tile as low-power island E-cores. However, Intel hasn't confirmed if it will be available for desktop systems.

The following CPU architecture, "Nova Lake", is set to debut in 2026. Unlike "Panther Lake", we know "Nova Lake" will work on desktop computers. This suggests desktop users might need to wait until 2026 for an upgrade unless Intel surprises us with a desktop version of "Panther Lake" or an alternative option.

New technology from Chalmers University of Technology and the University of Gothenburg, Sweden, is helping the EU establish its own competitive computer manufacturing industry. Researchers have developed components critical for optimising on-chip memory, a key factor in enhancing the performance of next-generation computers.

The research leader, Professor Per Stenström, along with colleagues, has discovered new ways to make cache memory work smarter. A cache is a local memory that temporarily stores frequently accessed data, improving a computer's speed and performance. "Our solution enables computers to retrieve data significantly faster than before, as the cache can manage far more processing elements (PEs) than most existing systems. This makes it possible to meet the demands of tomorrow's powerful computers," says Per Stenström, Professor at the Department of Computer Science and Engineering at Chalmers University of Technology and the University of Gothenburg.

In the design of wearable devices, every millimeter matters. As AI technology becomes deeply integrated, wearable devices demand not only enhanced performance but also the ability to deliver more functionalities within highly limited spaces. Recently, Longsys introduced a 7.2 mm × 7.2 mm subsize eMMC, providing a groundbreaking memory solution for optimizing the physical space of AI wearables.

Ultra-Compact: Unlocking New Possibilities for Wearable Design
7.2 mm × 7.2 mm is one of the smallest subsize eMMCs currently available on the market, achieving maximum space efficiency. Its 153 solder balls nearly cover the entire panel, pushing the design to the very edge of physical limits. Compared to the standard 11.5 mm × 13 mm eMMC, its surface area is reduced by approximately 65%, with a thickness of just 0.8 mm. Featuring a lightweight design, it weighs only 0.1 g (approx.), nearly 67% lighter than the standard 0.3 g eMMC. This ultra-compact design frees up additional space for other internal components, enabling wearable devices to maintain a sleek and lightweight form while integrating more functional modules to meet diverse user demands.

Cadence today announced that MediaTek has adopted the AI-driven Cadence Virtuoso Studio and Spectre X Simulator on the NVIDIA accelerated computing platform for its 2 nm development. As design size and complexity continue to escalate, advanced-node technology development has become increasingly challenging for SoC providers. To meet the aggressive performance and turnaround time (TAT) requirements for its 2 nm high-speed analog IP, MediaTek is leveraging Cadence's proven custom/analog design solutions, enhanced by AI, to achieve a 30% productivity gain.

"As MediaTek continues to push technology boundaries for 2 nm development, we need a trusted design solution with strong AI-powered tools to achieve our goals," said Ching San Wu, corporate vice president at MediaTek. "Closely collaborating with Cadence, we have adopted the Cadence Virtuoso Studio and Spectre X Simulator, which deliver the performance and accuracy necessary to achieve our tight design turnaround time requirements. Cadence's comprehensive automation features enhance our throughput and efficiency, enabling our designers to be 30% more productive."

Montage Technology today announced the customer sampling of its PCIe 6.x/CXL 3.x Retimer -- M88RT61632, which is designed to enhance connectivity performance for demanding high-bandwidth applications such as AI and cloud computing. This milestone extends the company's PCIe product portfolio, building upon its successful PCIe 4.0 and PCIe 5.0/CXL 2.0 Retimer solutions.

The PCIe 6.x/CXL 3.x Retimer delivers excellent performance with data rates up to 64 GT/s, twice that of PCIe 5.0. Powered by Montage Technology's proprietary PAM4 SerDes IP, the chip achieves superior signal integrity with link budget up to 43dB while maintaining low latency. Its innovative DSP architecture effectively addresses PCIe 6.x system design challenges including crosstalk and signal reflection. In addition, the chip features advanced link training and enhanced telemetry, enabling comprehensive link monitoring and fault diagnostics for high-reliability AI cluster deployments.

Today, the U.S. Department of Commerce has announced that CHIPS National Advanced Packaging Manufacturing Program (NAPMP) has finalized $1.4 billion in award funding to bolster U.S. leadership in advanced packaging and enable new technologies to be validated and transitioned at scale to U.S. manufacturing. These awards will help establish a self-sustaining, high-volume, domestic, advanced packaging industry where advanced node chips are both manufactured and packaged in the United States.

These awards include:

• A total of $300 million under the CHIPS NAPMP's first Notice of Funding Opportunity (NOFO) for advanced substrates and material research to Absolics Inc., Applied Materials Inc., and Arizona State University. This follows the previously announced intent to enter negotiations on November 21, 2024
• $1.1 billion to Natcast to operate the advanced packaging capabilities of the CHIPS for America NSTC Prototyping and NAPMP Advanced Packaging Piloting Facility (PPF). This follows the previously announced CHIPS R&D Facilities Model on July 12, 2024, and planned site selection for the PPF on January 6, 2025

Digital Enhancement (Hangzhou) Co., Ltd (hereafter referred to as "Digital Enhancement") is set to unveil the world's first commercial-grade Radio Processing Unit (RPU) designed for Wi-Fi wireless access at the CES International Consumer Electronics Show in Las Vegas, USA.

This groundbreaking RPU and solution leverage Digital Enhancement's innovative "Digital RF" technology, delivering a 10x performance boost in Wi-Fi high-speed coverage. The innovation promises to redefine the wireless connectivity experience for consumer electronics, paving the way for a new era of seamless and high-performance wireless connections.

TSMC is making progress with its most advanced 2 nm (N2) node, a recent report from MoneyDJ quoting industry sources indicates that the company is setting up a test production line at the Hsinchu Baoshan fab (Fab 20) in Taiwan. In the early stages, TSMC aims for small monthly outputs with about 3,000-3,500 wafers. However, the company has big plans to combine production from two factories in Hsinchu and Kaohsiung, TSMC expects to deliver more than 50,000 wafers monthly by the end of 2025 and by the end of 2026 projecting a production of around 125,000 wafers per month. Breaking it down by location, the Hsinchu factory should reach 20,000-25,000 wafers monthly by late 2025, growing to about 60,000-65,000 by early 2027. Meanwhile, the Kaohsiung factory is expected to produce 25,000-30,000 wafers monthly by late 2025, also increasing to 60,000-65,000 by early 2027.

TSMC's chairman C.C. Wei says there's more demand for these 2 nm chips than there was for the 3 nm. This increased "appetite" for 2 nm chips is likely due to the significant improvements this technology brings: it uses 24-35% less power, can run 15% faster at the same power level, and can fit 15% more transistors in the same space compared to the 3 nm chips. Apple will be the first company to use these chips, followed by other major tech companies like MediaTek, Qualcomm, Intel, NVIDIA, AMD, and Broadcom.

Intel and AMD are both widely expected to hit the market with new high-performance mobile chips at CES 2025. We expect Team Blue to lift the curtains on its Core Ultra 200H and 200HX lineup, whereas Team Red will strike back with its Strix Halo products, a few of which were leaked recently with promising performance. However, that's not all that we expect from the x86 behemoths, as both are poised to introduce mid-range and budget offerings as well.

Interestingly, it appears that Intel has already pulled back the veil on its Raptor Lake-H Refresh-based Core 200H lineup, which has been revealed as the Core Processor series. The lineup consists of mostly rebadged Raptor Lake-H chips, with some confusing choices. The products, based on the Intel 7 node, are as follows.

The pilot line for "Advanced Packaging and Heterogeneous Integration for Electronic Components and Systems" (APECS) marks a major leap forward in strengthening Europe's semiconductor manufacturing capabilities and chiplet innovation as part of the EU Chips Act. By providing large industry players, SMEs, and start-ups with a facilitated access to cutting-edge technology, the APECS pilot line will establish a strong foundation for resilient and robust European semiconductor supply chains. Within APECS, the institutes collaborating in the Research Fab Microelectronics Germany (FMD) will work closely with European partners, to make a significant contribution to the European Union's goals of increasing technological resilience, strengthening cross-border collaboration and enhancing its global competitiveness in semiconductor technologies. APECS is co-funded by the Chips Joint Undertaking and national funding authorities of Austria, Belgium, Finland, France, Germany, Greece, Portugal, Spain, through the "Chips for Europe" initiative. The overall funding for APECS amounts to €730 million over 4.5 years.

Europe is home to a vibrant ecosystem of (hidden) champions, from traditional enterprises in vertical markets, to SMEs and start-ups the competitive advantages of which lie in superior semiconductor-based solutions. Nevertheless, many of these companies are currently confronted with limited access to advanced semiconductor technologies, while at the same time these technologies are increasingly becoming the most important factor for innovation and market growth.

China has announced the development of its latest quantum system, combining the Xiaohong-504, a 504-qubit superconducting quantum chip, with the Tianyan-504 quantum computer. The breakthrough comes from China Telecom Quantum Group (CTQG), which will use the new supercomputer to boost national telecommunications security. The Xiaohong-504 chip reportedly demonstrates impressive specifications in critical areas including qubit lifetime, gate fidelity, and circuit depth, comparable with established quantum platforms such as IBM. The first Xiaohong-504 processor is scheduled for delivery to QuantumCTek, a quantum technology company based in Anhui Province, where it will begin extensive testing of kilo-qubit measurement and control systems.

While the Tianyan-504 represents a major achievement, it currently ranks behind some international competitors in terms of qubit count. Atom Computing's 1,180-qubit prototype was revealed in late 2023, and IBM's 1,121-qubit Condor processor maintains the lead in raw qubit numbers. The development of the Tianyan-504 was a collaborative effort between CTQG, the Chinese Academy of Sciences, and QuantumCTek. The system will be integrated into the Tianyan quantum cloud platform, which has already demonstrated significant international reach since its launch in November 2023, attracting more than 12 million visits from users across over 50 countries. Rather than focusing solely on achieving quantum supremacy, the Tianyan-504 project aim is developing infrastructure for large-scale quantum systems.

AMD today announced the expansion of the AMD Versal adaptive system-on-chip (SoC) portfolio with the introduction of the Versal RF Series that includes the industry's highest compute performance in a single-chip device with integrated direct radio frequency (RF)-sampling data converters.

Versal RF Series offers precise, wideband-spectrum observability and up to 80 TOPS of digital signal processing (DSP) performance in a size, weight, and power (SWaP)-optimized design, targeting RF systems and test equipment applications in the aerospace and defense (A&D) and test and measurement (T&M) markets, respectively.

Today at the IEEE International Electron Devices Meeting (IEDM) 2024, Intel Foundry unveiled new breakthroughs to help drive the semiconductor industry forward into the next decade and beyond. Intel Foundry showcased new material advancements that help improve interconnections within a chip, resulting in up to 25% capacitance by using subtractive ruthenium. Intel Foundry also was first to report a 100x throughput improvement using a heterogeneous integration solution for advanced packaging to enable ultra-fast chip-to-chip assembly. And to further drive gate-all-around (GAA) scaling, Intel Foundry demonstrated work with silicon RibbonFET CMOS and with gate oxide module for scaled 2D FETs for improved device performance.

"Intel Foundry continues to help define and shape the roadmap for the semiconductor industry. Our latest breakthroughs underscore the company's commitment to delivering cutting-edge technology developed in the U.S., positioning us well to help balance the global supply chain and restore domestic manufacturing and technology leadership with the support of the U.S. CHIPS Act," says Sanjay Natarajan, Intel senior vice president and general manager of Intel Foundry Technology Research.

Broadcom Inc. today announced the availability of its 3.5D eXtreme Dimension System in Package (XDSiP) platform technology, enabling consumer AI customers to develop next-generation custom accelerators (XPUs). The 3.5D XDSiP integrates more than 6000 mm² of silicon and up to 12 high bandwidth memory (HBM) stacks in one packaged device to enable high-efficiency, low-power computing for AI at scale. Broadcom has achieved a significant milestone by developing and launching the industry's first Face-to-Face (F2F) 3.5D XPU.

The immense computational power required for training generative AI models relies on massive clusters of 100,000 growing to 1 million XPUs. These XPUs demand increasingly sophisticated integration of compute, memory, and I/O capabilities to achieve the necessary performance while minimizing power consumption and cost. Traditional methods like Moore's Law and process scaling are struggling to keep up with these demands. Therefore, advanced system-in-package (SiP) integration is becoming crucial for next-generation XPUs. Over the past decade, 2.5D integration, which involves integrating multiple chiplets up to 2500 mm² of silicon and HBM modules up to 8 HBMs on an interposer, has proven valuable for XPU development. However, as new and increasingly complex LLMs are introduced, their training necessitates 3D silicon stacking for better size, power, and cost. Consequently, 3.5D integration, which combines 3D silicon stacking with 2.5D packaging, is poised to become the technology of choice for next-generation XPUs in the coming decade.

Intel Corporation today announced that Eric Meurice, former president, chief executive officer and chairman of ASML Holding N.V., and Steve Sanghi, chairman and interim chief executive officer of Microchip Technology Inc., have been appointed to Intel's board of directors, effective immediately. Both will serve as independent directors.

"Eric and Steve are highly respected leaders in the semiconductor industry whose deep technical expertise, executive experience and operational rigor make them great additions to the Intel board," said Frank D. Yeary, interim executive chair of the Intel board. "As successful CEOs with proven track records of creating shareholder value, they will bring valuable perspectives to the board as the company delivers on its priorities for customers in Intel Products and Intel Foundry, while driving greater efficiency and improving profitability."

SK Hynix plans to produce its 6th generation high-bandwidth memory chips (HBM4) using TSMC's 3 nm process, a change from initial plans to use the 5 nm technology. The Korea Economic Daily reports that these chips will be delivered to NVIDIA in the second half of 2025. NVIDIA's GPU products are currently based on 4 nm HBM chips. The HBM4 prototype chip launched in March by SK Hynix features vertical stacking on a 3 nm die., compared to a 5 nm base die, the new 3 nm-based HBM chip is expected to offer a 20-30% performance improvement. However, SK Hynix's general-purpose HBM4 and HBM4E chips will continue to use the 12 nm process in collaboration with TSMC.

While SK Hynix's fifth-generation HBM3E chips used its own base die technology, the company has chosen TSMC's 3 nm technology for HBM4. This decision is anticipated to significantly widen the performance gap with competitor Samsung Electronics, which plans to manufacture its HBM4 chips using the 4 nm process. SK hynix is currently leading the global HBM market with almost 50% of market share, most of its HBM products been delivered to NVIDIA.

Germany is set to invest €2 billion in the semiconductor industry after recent setbacks, according to TrendForce via Liberty Times citing Bloomberg. The German government's new funding is in response to the chip sector's problems, including Intel's delay of the Magdeburg factory and global disruptions in the semiconductor supply chain. The investment will support 10 to 15 projects from wafer production to microchip assembly to strengthen Germany's and Europe's microelectronics ecosystem. This is in line with the European Chips Act which aims to increase the EU's global production capacity to 20% by 2030.

Intel's €30 billion Magdeburg factory delay and other cancelled chip projects from Wolfspeed and ZF Friedrichshafen AG have created uncertainty in the German market. The Ministry of Economic Affairs is now calling for new applications for funding, with up to €3 billion available. The timing of the semiconductor investment follows the global supply chain disruptions caused by the pandemic and the increasing geopolitical tensions between the US, China and Taiwan. Germany is following a broader trend of governments investing in local semiconductor production to increase technological independence and economic resilience. The funding is subject to budget reallocation with the new government after February 2025 elections. In the first round of subsidies from the European Chips Act, Germany allocated resources to two key initiatives: Intel's investment and a collaborative project between Infineon and TSMC in Dresden.

AMD has recently filed a patent revealing plans to implement "multi-chip stacking" in future Ryzen SoCs, as Wccftech reports, quoting a post on X from @coreteks: "New patent from AMD shows how future Zen SoCs could look. Basically a novel packaging design that enables compact chip stacking and interconnection by having them partially overlap, as in this figure. The dotted line is a larger die stacked on top of those smaller ones". The patent details a new approach where smaller chiplets partially overlap with a larger die, creating space for additional components and functions on the same die. This strategy aims to improve the efficiency of the contact area, thus making room for higher core counts, larger caches, and increased memory bandwidth within the same die size. The proposed stacking will reduce the physical distance between components through overlapping chiplets, thus minimizing interconnect latency and achieving faster communication between different chip parts. The design will also improve power management, as the segregated chiplets allow for better control of each unit through power gating.

Even if long-time rival Intel has lost some of its momentum (and market share) this year, AMD's chance to push ahead with its intention to become number one in the market is to continue to innovate. In the same way that its 3D V-Cache technology made the X3D processor lineup so successful, this chip stacking approach could play a major role in future AMD Ryzen SoCs. It seems that AMD is committed to moving away from the monolithic design era and taking the road of multi-chiplet; however, it can be a long wait until (and if) this chip stacking will complete the journey from patents to design, production, and final product.

For over half a century, general-purpose processors have been built on the Tomasulo algorithm, developed by IBM engineer Robert Tomasulo in 1967. It's a $500B industry built on specialized CPU, GPU and other chips for different computing tasks. Hardware startup Ubitium has shattered this paradigm with a breakthrough universal processor that handles all computing workloads on a single, efficient chip - unlocking simpler, smarter, and more cost-effective devices across industries - while revolutionizing a 57-year-old industry standard.

Alongside this, Ubitium is announcing a $3.7 million in seed funding round, co-led by Runa Capital, Inflection, and KBC Focus Fund. The investment will be used to develop the first prototypes and prepare initial development kits for customers, with the first chips planned for 2026.

Renesas Electronics Corporation, a premier supplier of advanced semiconductor solutions, today announced that it has delivered the industry's first complete memory interface chipset solutions for the second-generation DDR5 Multi-Capacity Rank Dual In-Line Memory Modules (MRDIMMs).

The new DDR5 MRDIMMs are needed to keep pace with the ever-increasing memory bandwidth demands of Artificial Intelligence (AI), High-Performance Compute (HPC) and other data center applications. They deliver operating speeds up to 12,800 Mega Transfers Per Second (MT/s), a 1.35x improvement in memory bandwidth over first-generation solutions. Renesas has been instrumental in the design, development and deployment of the new MRDIMMs, collaborating with industry leaders including CPU and memory providers, along with end customers.

d-Matrix today unveiled Corsair, an entirely new computing paradigm designed from the ground-up for the next era of AI inference in modern datacenters. Corsair leverages d-Matrix's innovative Digital In-Memory Compute architecture (DIMC), an industry first, to accelerate AI inference workloads with industry-leading real-time performance, energy efficiency, and cost savings as compared to GPUs and other alternatives.

The emergence of reasoning agents and interactive video generation represents the next level of AI capabilities. These leverage more inference computing power to enable models to "think" more and produce higher quality outputs. Corsair is the ideal inference compute solution with which enterprises can unlock new levels of automation and intelligence without compromising on performance, cost or power.

Q.ANT, the leading startup for photonic computing, today announced the launch of its first commercial product - a photonics-based Native Processing Unit (NPU) built on the company's compute architecture LENA - Light Empowered Native Arithmetics. The product is fully compatible with today's existing computing ecosystem as it comes on the industry-standard PCI-Express. The Q.ANT NPU executes complex, non-linear mathematics natively using light instead of electrons, promising to deliver at least 30 times greater energy efficiency and significant computational speed improvements over traditional CMOS technology. Designed for compute-intensive applications such as AI Inference, machine learning, and physics simulation, the Q.ANT NPU has been proven to solve real-world challenges, including number recognition for deep neural network inference (see the recent press release regarding Cloud Access to NPU).

"With our photonic chip technology now available on the standard PCIe interface, we're bringing the incredible power of photonics directly into real-world applications. For us, this is not just a processor—it's a statement of intent: Sustainability and performance can go hand in hand," said Dr. Michael Förtsch, CEO of Q.ANT. "For the first time, developers can create AI applications and explore the capabilities of photonic computing, particularly for complex, nonlinear calculations. For example, experts calculated that one GPT-4 query today uses 10 times more electricity than a regular internet search request. Our photonic computing chips offer the potential to reduce the energy consumption for that query by a factor of 30."

Japan has proposed a $65 billion (or more) plan to strengthen the semiconductor and AI industries in the country through grants and financial support by fiscal year 2030. The government plans to present this proposal at the next parliamentary session. The draft includes support for mass production of next-generation chips, focusing on AI chipmakers such as Rapidus, the government estimates an economic impact of about 160 trillion yen from this investment. Rapidus plans to start mass production of advanced chips in Hokkaido from 2027 and will work with IBM and Belgian research organization Imec.

According to the report from Reuters, Prime Minister Shigeru Ishiba said the government would not issue deficit-financing bonds to fund the support plan, although specific financial details are not yet known. The new initiative builds on last year's 2 trillion yen investment in the chip industry, and it is part of a broader economic package. Expected to be approved by the Cabinet on November 22, the plan calls for combined public and private investment in the semiconductor industry of more than 50 trillion yen over the next decade.

LG Electronics (LG) and Tenstorrent are pleased to announce an expanded collaboration, building on their initial chiplet project to develop System-on-Chips (SoCs) and systems for the global market. Through this partnership, LG aims to enhance its design and development capabilities for AI chips tailored to its products and services, aligning with its vision of "Affectionate Intelligence." LG is dedicated to advancing AI-driven innovation, with a focus on enhancing its AI-powered home appliances and smart home solutions, as well as expanding its capabilities in future mobility and commercial applications.

Recognizing the critical role of high-performance AI semiconductors in implementing AI technology, LG plans to strengthen its in-house development capabilities while collaborating with leading global companies, including Tenstorrent, to boost its AI competitiveness.

Both pictures and videos of a partial teardown of Apple's recently launched Mac mini with the M4 SoC have appeared online courtesy of various Chinese sources. There are at least two interesting parts to these partial teardowns and they're related to storage and WiFi. On the storage front, Apple has moved away from having soldered NAND chips straight on the main PCB of the Mac mini, to instead having them on a custom PCB which is similar to M.2, but a custom Apple design. The PCB pictured contained a pair of 128 GB NAND chips and with the source of the teardown being from China, there's also a video showing a repair shop desoldering the two chips and replacing them with two 1 TB chips, or in other words, the SSD was upgraded from 256 GB to 2 TB.

The upgrade brought with it some extra performance as well, even if the write speed remained at a comparatively slow 2900 MB/s, the read speed went up from 2000 MB/s to 3300 MB/s which is a significant gain in performance. This is obviously not a consumer friendly upgrade path, but we'd expect to see third party upgrade options at some point in the future, assuming there's no black listing of third party storage modules. The NAND controller is still likely to be integrated into Apple's SoC, but the PCB that the NAND flash chips are mounted onto appears to have some kind of SPI flash on it as well, which might make third party upgrades a lot harder.