The artificial intelligence boom is driving a sharp rise in electricity use across the United States, catching utilities and regulators off guard. In northern Virginia's "data center alley," demand is so high that the local utility temporarily halted new data center connections in 2022. Nation-wide, electricity consumption at data centers alone could triple by 2030 to 390 TeraWatt Hours. Add in new electric vehicle battery factories, chip plants, and other clean tech manufacturing spurred by federal incentives, and demand over the next five years is forecast to rise at 1.5%—the fastest rate since the 1990s. Unable to keep pace, some utilities are scrambling to revise projections and reconsider previous plans of closing fossil fuel plants even as the Biden administration pushes for more renewable energy. Some older coal power plans will stay online, until the grid adds more power production capacity. The result could be increased emissions in the near term and risks of rolling blackouts if infrastructure continues lagging behind demand.

The situation is especially dire in Virginia, the world's largest data center hub. The state's largest utility, Dominion Energy, was forced to pause new data center connections for three months last year due to surging demand in Loudoun County. Though connections have resumed, Dominion expects load growth to almost double over the next 15 years. With data centers, EV factories, and other power-hungry tech continuing rapid expansion, experts warn the US national electricity grid is poorly equipped to handle the spike. Substantial investments in new transmission lines and generation are urgently needed to avoid businesses being turned away or blackouts in some regions. Though many tech companies aim to power operations with clean energy, factories are increasingly open to any available power source.

According to new data from Chinese Customs, China's imports of integrated circuits suffered their steepest annual drop on record in 2023, falling 15.4% to $349.4 billion. The decline marks the second straight year of falling chip imports and can be attributed to economic uncertainty and US export controls on advanced semiconductors. Shipment volumes of imported chips also saw a substantial 10.8% year-over-year decrease as demand within China stagnated. The country's important tech manufacturing sector has struggled under strict zero-Covid policies and a lackluster recovery post-pandemic. Flagship manufacturing companies like TSMC recorded modest declines in 2023 sales, though TSMC still forecasts overall growth this year.

Sentiment plunged further when the Biden administration heightened restrictions on China's access to cutting-edge AI-capable chips from NVIDIA and other top American suppliers. The escalating US export controls have choked off China's pipeline to advanced semiconductors needed for AI and supercomputing applications. However, early positive signs for global semiconductor demand have emerged, with worldwide chip sales rising for the first time in over a year this past November. The increase was driven by growing demand for AI and other emerging technologies that rely on advanced computing chips. While the US seeks to limit China's progress in this key strategic area, an inflection point for the battered global chip sector may be nearing.

Wi-Fi CERTIFIED 7 is here, introducing powerful new features that boost Wi-Fi performance and improve connectivity across a variety of environments. Cutting-edge capabilities in Wi-Fi CERTIFIED 7 enable innovations that rely on high throughput, deterministic latency, and greater reliability for critical traffic. New use cases - including multi-user AR/VR/XR, immersive 3-D training, electronic gaming, hybrid work, industrial IoT, and automotive - will advance as a result of the latest Wi-Fi generation. Wi-Fi CERTIFIED 7 represents the culmination of extensive collaboration and innovation within Wi-Fi Alliance, facilitating worldwide product interoperability and a robust, sophisticated device ecosystem.

Wi-Fi 7 will see rapid adoption across a broad ecosystem with more than 233 million devices expected to enter the market in 2024, growing to 2.1 billion devices by 2028. Smartphones, PCs, tablets, and access points (APs) will be the earliest adopters of Wi-Fi 7, and customer premises equipment (CPE) and augmented and virtual reality (AR/VR) equipment will continue to gain early market traction. Wi-Fi CERTIFIED 7 pushes the boundaries of today's wireless connectivity, and Wi-Fi CERTIFIED helps ensure advanced features are deployed in a consistent way to deliver high-quality user experiences.

MaxLinear, Inc., a global leader in broadband access and gateway solutions, today announced its Wi-Fi 7 chipsets and Tri-band Access Point were certified by Wi-Fi Alliance and selected as one of the Wi-Fi CERTIFIED 7 test bed devices. Wi-Fi Alliance's Wi-Fi 7 certification helps verify that upcoming Wi-Fi 7 devices can seamlessly interoperate and deliver the high-performance promises of the new standard. The inclusion of MaxLinear's innovative, single-chip Wi-Fi 7 solution in the verification process exemplifies its continuing commitment to pushing the boundaries of in-home communications and reshaping the way service providers build access and connectivity networks.

"At MaxLinear, we're not just leading the pack with Wi-Fi 7 technology; we're redefining it. Our single-chip tri-band device is an industry first, symbolizing a giant leap in wireless communication," said Will Torgerson, VP/GM Broadband Group. "With our focus on power efficiency and peak performance, we're at the forefront of the Wi-Fi 7 revolution, offering blazing-fast speeds, reduced latency, and robust connectivity. As part of the Wi-Fi Alliance, we celebrate 25 years of Wi-Fi innovation and remain committed to advancing a connected world where our groundbreaking solutions enable seamless, multi-gigabit broadband access."

According to the report from a journal called Fundamental Research, researchers from the Institute of Computing Technology at the Chinese Academy of Sciences have developed a 256-core multi-chiplet processor called Zhejiang Big Chip, with plans to scale up to 1,600 cores by utilizing an entire wafer. As transistor density gains slow, alternatives like multi-chiplet architectures become crucial for continued performance growth. The Zhejiang chip combines 16 chiplets, each holding 16 RISC-V cores, interconnected via network-on-chip. This design can theoretically expand to 100 chiplets and 1,600 cores on an advanced 2.5D packaging interposer. While multi-chiplet is common today, using the whole wafer for one system would match Cerebras' breakthrough approach. Built on 22 nm process technology, the researchers cite exascale supercomputing as an ideal application for massively parallel multi-chiplet architectures.

Careful software optimization is required to balance workloads across the system hierarchy. Integrating near-memory processing and 3D stacking could further optimize efficiency. The paper explores lithography and packaging limits, proposing hierarchical chiplet systems as a flexible path to future computing scale. While yield and cooling challenges need further work, the 256-core foundation demonstrates the potential of modular designs as an alternative to monolithic integration. China's focus mirrors multiple initiatives from American giants like AMD and Intel for data center CPUs. But national semiconductor ambitions add urgency to prove domestically designed solutions can rival foreign innovation. Although performance details are unclear, the rapid progress shows promise in mastering modular chip integration. Combined with improving domestic nodes like the 7 nm one from SMIC, China could easily create a viable Exascale system in-house.

Global semiconductor capacity is expected to increase 6.4% in 2024 to top the 30 million *wafers per month (wpm) mark for the first time after rising 5.5% to 29.6 wpm in 2023, SEMI announced today in its latest quarterly World Fab Forecast report.

The 2024 growth will be driven by capacity increases in leading-edge logic and foundry, applications including generative AI and high-performance computing (HPC), and the recovery in end-demand for chips. The capacity expansion slowed in 2023 due to softening semiconductor market demand and the resulting inventory correction.

Chinese x86 CPU developer Zhaoxin is working on adding support in the Linux kernel for scheduling optimization on its processors featuring "preferred cores." Similar to asymmetric core designs from Intel and AMD, Zhaoxin's chips may have specific higher-performance cores the OS scheduler should target for critical workloads. To enable this, Zhaoxin has proposed Linux patches leveraging existing ACPI functionality to indicate per-core differences in max frequency or capabilities. The CPUfreq driver is updated to reflect this, allowing the scheduler to favor the designated high-performance cores when assigning threads and processes. This ensures tasks can dynamically take advantage of the faster cores to maximize performance. The approach resembles tuned scheduling, aware of core topology and heterogeneity already found in Intel and AMD processors.

Zhaoxin's patches don't specify which existing or upcoming CPUs will expose preferred core hints. The company likely wants the functionality in place for future server-class products where asymmetric designs make sense for efficiency. The new code contribution reflects Zhaoxin's broader upstreaming effort around Linux kernel support for its Yongfeng server CPU family. Robust open-source foundations are crucial for gaining developer mindshare and data center adoption. Adding sophisticated features like preferred core scheduling indicates that Zhaoxin's chips are maturing from essential x86 compatibility to more refined performance optimization. While still trailing Intel and AMD in cores and clocks, closing the software ecosystem and efficiency gap remains key to competitiveness. Ongoing Linux enablement work is laying the groundwork for more capable Zhaoxin silicon.

During the recent IEDM conference, TSMC previewed its process roadmap for delivering next-generation chip packages packing over one trillion transistors by 2030. This aligns with similar long-term visions from Intel. Such enormous transistor counts will come through advanced 3D packaging of multiple chipsets. But TSMC also aims to push monolithic chip complexity higher, ultimately enabling 200 billion transistor designs on a single die. This requires steady enhancement of TSMC's planned N2, N2P, N1.4, and N1 nodes, which are slated to arrive between now and the end of the decade. While multi-chipset architectures are currently gaining favor, TSMC asserts both packaging density and raw transistor density must scale up in tandem. Some perspective on the magnitude of TSMC's goals include NVIDIA's 80 billion transistor GH100 GPU—among today's largest chips, excluding wafer-scale designs from Cerebras.

Yet TSMC's roadmap calls for more than doubling that, first with over 100 billion transistor monolithic designs, then eventually 200 billion. Of course, yields become more challenging as die sizes grow, which is where advanced packaging of smaller chiplets becomes crucial. Multi-chip module offerings like AMD's MI300X and Intel's Ponte Vecchio already integrate dozens of tiles, with PVC having 47 tiles. TSMC envisions this expansion to chip packages housing more than a trillion transistors via its CoWoS, InFO, 3D stacking, and many other technologies. While the scaling cadence has recently slowed, TSMC remains confident in achieving both packaging and process breakthroughs to meet future density demands. The foundry's continuous investment ensures progress in unlocking next-generation semiconductor capabilities. But physics ultimately dictates timelines, no matter how aggressive the roadmap.

Samsung Electronics, a world leader in advanced memory technology, today announced that for the first time in the industry, it has successfully verified Compute Express Link (CXL) memory operations in a real user environment with open-source software provider Red Hat, leading the expansion of its CXL ecosystem.

Due to the exponential growth of data throughput and memory requirements for emerging fields like generative AI, autonomous driving and in-memory databases (IMDBs), the demand for systems with greater memory bandwidth and capacity is also increasing. CXL is a unified interface standard that connects various processors, such as CPUs, GPUs and memory devices through a PCIe interface that can serve as a solution for limitations in existing systems in terms of speed, latency and expandability.

Semiconductor industry players Robert Bosch GmbH, Infineon Technologies AG, Nordic Semiconductor ASA, NXP Semiconductors, and Qualcomm Technologies, Inc., have formally established Quintauris GmbH. Headquartered in Munich, Germany, the company aims to advance the adoption of RISC-V globally by enabling next-generation hardware development.

The formation of Quintauris was formally announced in August, with the aim to be a single source to enable compatible RISC-V-based products, provide reference architectures, and help establish solutions to be widely used across various industries. The initial application focus will be automotive, but with an eventual expansion to include mobile and IoT.

Chinese company Sipeed has introduced the Lichee Pocket 4A, one of the first handheld gaming devices based on the RISC-V open-source instruction set architecture (ISA). Sipeed positions the device as a retro gaming platform capable of running simple titles via software rendering or GPU acceleration. At its core is Alibaba's T-Head TH1520 processor featuring four 2.50 GHz Xuantie C910 RISC-V general-purpose CPU cores and an unnamed Imagination GPU. The chip was originally aimed at laptop designs. Memory options include 8 GB or 16 GB LPDDR4X RAM and 32 GB or 128 GB of storage. The Lichee Pocket 4A has a 7-inch 1280x800 LCD touchscreen, Wi-Fi/Bluetooth connectivity, and an array of wired ports like USB and Ethernet. It weighs under 500 grams. The device can run Android or Linux distributions like Debian, Ubuntu, and others.

As an early RISC-V gaming entrant, performance expectations should be modest—the focus is retro gaming and small indie titles, not modern AAA games. Specific gaming capabilities remain to be fully tested. However, the release helps showcase RISC-V's potential for consumer electronics and competitive positioning against proprietary ISAs like ARM. Pricing is still undefined, but another Sipeed handheld console retails for around $250 currently. Reception from enthusiasts and developers will demonstrate whether there's a viable market for RISC-V gaming devices. Success could encourage additional hardware experimentation efforts across emerging open architectures. With a 6000 mAh battery, battery life should be decent. Other specifications can be seen in the table below, and the pre-order link is here.

TrendForce reports that 3Q23 has been a historic quarter for the world's leading IC design houses as total revenue soared 17.8% to reach a record-breaking US$44.7 billion. This remarkable growth is fueled by a robust season of stockpiling for smartphones and laptops, combined with a rapid acceleration in the shipment of generative AI chips and components. NVIDIA, capitalizing on the AI boom, emerged as the top performer in revenue and market share. Notably, analog IC supplier Cirrus Logic overtook US PMIC manufacturer MPS to snatch the tenth spot, driven by strong demand for smartphone stockpiling.

NVIDIA's revenue soared 45.7% to US$16.5 billion in the third quarter, bolstered by sustained demand for generative AI and LLMs. Its data center business—accounting for nearly 80% of its revenue—was a key driver in this exceptional growth.

Chinese chipmaker Moore Threads has launched its first domestically-produced 1000-card AI training cluster, dubbed the KUAE Intelligent Computing Center. A central part of the KUAE cluster is Moore Threads new MTT S4000 accelerator card with 48 GB VRAM utilizing the company's third-generation MUSA GPU architecture and 768 GB/s memory bandwidth. In FP32, the card can output 25 TeraFLOPS; in TF32, it can achieve 50 TeraFLOPS; and in FP16/BF16, up to 200 TeraFLOPS. Also supported is INT8 at 200 TOPS. The MTT S4000 focuses on both training and inference, leveraging Moore Thread's high-speed MTLink 1.0 intra-system interconnect to scale cards for distributed model parallel training of datasets with hundreds of billions of parameters. The card also provides graphics, video encoding/decoding, and 8K display capabilities for graphics workloads. Moore Thread's KUAE cluster combines the S4000 GPU hardware with RDMA networking, distributed storage, and integrated cluster management software. The KUAE Platform oversees multi-datacenter resource allocation and monitoring. KUAE ModelStudio hosts training frameworks and model repositories to streamline development.

With integrated solutions now proven at thousands of GPUs, Moore Thread is positioned to power ubiquitous intelligent applications - from scientific computing to the metaverse. The KUAE cluster reportedly achieves near-linear 91% scaling. Taking 200 billion training data as an example, Zhiyuan Research Institute's 70 billion parameter Aquila2 can complete training in 33 days; a model with 130 billion parameters can complete training in 56 days on the KUAE cluster. In addition, the Moore Threads KUAE killocard cluster supports long-term continuous and stable operation, supports breakpoint resume training, and has an asynchronous checkpoint that is less than 2 minutes. For software, Moore Threads also boasts full compatibility with NVIDIA's CUDA framework, where its MUSIFY tool translates CUDA code to MUSA GPU architecture at supposedly zero cost of migration, i.e., no performance penalty.

Chinese chipmaker Montage Technology has unveiled new data center processors under its Jintide brand based on Intel's latest Emerald Rapids Xeon architecture. The 5th generation Jintide lineup offers anywhere from 16-core to 48-core options for enterprise customers needing advanced security specific to China's government and enterprise requirements. Leveraging a long-running joint venture with Intel, Jintide combines standard high-performance Xeon microarchitectures with added on-die monitoring and encryption blocks, PrC (Pre-check) and DSC (Dynamic Security Check), which are security-hardened for sensitive Chinese use cases. The processors retain all core performance attributes of Intel's vanilla offerings thanks to IP access, only with extra protections mandated by national security interests. While missing the very highest core counts, the new Jintide chips otherwise deliver similar Emerald Rapids features like 8-channel DDR5-5600 memory, 80 lanes of speedy PCIe 5.0, and elevated clock speeds over 4.0 GHz at peak. The Jintide processors have 2S scaling, which allows for dual-socket systems with up to 96 cores and 192 threads.

Pricing remains unpublished but likely carries a premium over Intel list prices thanks to the localized security customization required. However, with Jintide uniquely meeting strict Chinese government and data regulations, cost becomes secondary for target customers needing compliant data center hardware. After matching lockstep with Intel's last several leading Xeon generations, Jintide's continued iteration highlights its strategic value in enabling high-performance domestic infrastructure as China eyes IT supply chain autonomy. Intel gets expanded access to the growing Chinese server market, while Chinese partners utilize Intel IP to strengthen localized offerings without foreign dependency. It manifests the delicate balance of advanced chip joint ventures between global tech giants and rising challengers. More details about the SKUs are listed in the table below.

According to Tom's Hardware, today we are finding out that AMD Ryzen Threadripper 7000 series processors, codenamed Storm Peak, including Pro and non-Pro SKUs, blow a fuse on the chip when overclocking is enabled. Modern microprocessors have dozens of fuses that are used to store information inside the chip. For example, the factory stores the per-processor default voltage information in the fuses. On downgraded graphics chips, the shaders get disabled through such fuses, too. These fuses are not like your household circuit breakers—they will blow only when a specific command is sent to the processor, there is no way for them to break accidentally through system crashes or power spikes. In the case of Ryzen Threadripper 7000, the BIOS code will blow a fuse when the user enables overclocking in the BIOS settings, it reacts only to the user-initiated UI change, not to any kind of measurement. Before that happens a warning is shown. AMD uses this mechanism to see any indications if any kind of overclocking has been done to the processor.

While the messaging might suggest otherwise, just enabling overclocking does not void all warranties. In a statement to Tom's Hardware an AMD representative confirmed: "Threadripper 7000 Series processors do contain a fuse that is blown when overclocking is enabled. To be clear, blowing this fuse does not void your warranty. Statements that enabling an overclocking/overvolting feature will "void" the processor warranty are not correct. Per AMD's standard Terms of Sale, the warranty excludes any damage that results from overclocking/overvolting the processor. However, other unrelated issues could still qualify for warranty repair/replacement," noted the spokesperson. Ultimately, overclocking and overvolting by themselves will not cause the owner of AMD's Ryzen Threadripper 7000 series CPU to lose the right to repair and seek AMD's help. Other factors, such as damages induced by overclocking, will be a warranty-voiding factor though. These can occur from constant overheating, which significantly lowers the life expectancy of the CPU.

After years of delays, Chinese chipmaker Zhaoxin has finally launched its long-awaited KX-7000 series consumer CPUs, only one of its kind in China, based on the licensed x86-64 ISA. Zhaoxin claims the new 8-core processors based on "Century Avenue" uArch deliver double the performance of previous generations. Leveraging architectural improvements and 4X more cache, the KX-7000 represents essential progress for China's domestic semiconductor industry. While still likely lagging behind rival AMD and Intel chips in raw speed, the KX-7000 matches competitive specs in areas like DDR5 memory, PCIe 4.0, and USB4 support. For Chinese efforts to attain technological independence, closing feature gaps with foreign processors is just as crucial as boosting performance. Manufactured on a 16 nm process, the KX-7000 does not use the best silicon node available.

Other chip details include out-of-order execution (OoOE), 24 PCIe 4.0 lanes, a 32 MB pool of L3 cache and 4 MB L2 cache, a base frequency of 3.2 GHz, and a boost clock of 3.7 GHz. Interestingly, the CPU also has VT-x, BT-d 2.5, SSE4.2/AVX/AVX2 support, most likely also licensed from the x86 makers Intel and/or AMD. Ultimately, surpassing Western processors is secondary for China next to attaining self-reliance. Instructions like SM encryption catering to domestic data protection priorities underscore how the KX-7000 advances strategic autonomy goals. With its x86 architecture license giving software compatibility and now a vastly upgraded platform, the KX-7000 will raise China's chip capabilities even if it is still trailing rivals' speeds. Ongoing progress closing that performance gap could position Zhaoxin as a mainstream alternative for local PC builders and buyers.

Intel's upcoming Sierra Forest Xeon server chip has debuted on Geekbench 6, showcasing its potential in multi-core performance. Slated for release in the first half of 2024, Sierra Forest is equipped with up to 288 Efficiency cores, positioning it to compete with AMD's Zen 4c Bergamo server CPUs and other ARM-based server chips like those from Ampere for the favor of cloud service providers (CSP). In the Geekbench 6 benchmark, a dual-socket configuration featuring two 144-core Sierra Forest CPUs was tested. The benchmark revealed a notable multi-core score of 7,770, surpassing most dual-socket systems powered by Intel's high-end Xeon Platinum 8480+, which typically scores between 6,500 and 7,500. However, Sierra Forest's single-core score of 855 points was considerably lower, not even reaching half of that of the 8480+, which manages 1,897 points.

The difference in single-core performance is a matter of choice, as Sierra Forest uses Crestmont-derived Sierra Glen E-cores, which are more power and area-efficient, unlike the Golden Cove P-cores in the Sapphire Rapids-based 8480+. This design choice is particularly advantageous for server environments where high-core counts are crucial, as CSPs usually partition their instances by the number of CPU cores. However, compared to AMD's Bergamo CPUs, which use Zen 4c cores, Sierra Forest lacks pure computing performance, especially in multi-core. The Sierra Forest lacks hyperthreading, while Bergaamo offers SMT with 256 threads on the 128-core SKU. Comparing the Geekbench 6 scores to AMD Bergamo EPYC 9754 and Sierra Forest results look a lot less impressive. Bergamo scored 1,597 points in single-core, almost double that of Sierra Forest, and 16,455 points in the multi-core benchmarks, which is more than double. This is a significant advantage of the Zen 4c core, which cuts down on caches instead of being an entirely different core, as Intel does with its P and E-cores. However, these are just preliminary numbers; we must wait for real-world benchmarks to see the actual performance.

Apple has announced a partnership deal with Amkor, one of the leading chip packaging and testing manufacturers, which will build a two billion US Dollar silicon packaging facility in Peoria, Arizona. Being the only US-based OSAT (outsourced semiconductor assembly and test) provider, Amkor has decided to invest its funds and apply for the CHIPS Act, hoping to get a part of the funding from the US government's grant budget. The state-of-the-art facility in Arizona will feature over 500,000 square feet (46,452 square meters) of cleanroom space for packaging and testing chips. Using Amkor's latest technologies, the plant will support advanced computing, automotive, and communications chip packaging. It is tailored to meet the capacity needs of major customer Apple starting in 2025-2026. Apple will be the largest customer, with the Amkor facility packaging Apple-designed chips produced at the nearby TSMC wafer fabrication plant.

Building a chip packaging facility in the US with advanced packaging types means that the domestic manufacturing of advanced silicon is now possible across almost the entire supply chain, with OSAT now being present on US soil as well. In the initial phase, this partnership will enable domestic advanced packaging capabilities for leading-edge chips down to 3 nm nodes, which Apple plans to utilize for its A and M series of processors. Along with the creation of an estimated 2,000 local jobs, the investment serves as a boost to the local economy as well. Additionally, Amkor is TSMC's strategic partner, meaning future designs and packaging will cooperate without any delays.

According to the latest Canalys forecasts, worldwide PC shipments are on the verge of recovery following seven consecutive quarters of decline. The market is expected to return to growth of 5% in Q4 2023, boosted by a strong holiday season and an improving macroeconomic environment. Looking ahead, full-year 2024 shipments are forecast to hit 267 million units, landing 8% higher than in 2023, helped by tailwinds including the Windows refresh cycle and emergence of AI-capable and Arm-based devices.

"The global PC market is on a recovery path and set to return to 2019 shipment levels by next year," said Canalys Analyst Ben Yeh. "The impact of AI on the PC industry will be profound, with leading players across OEMs, processor manufacturers, and operating system providers focused on delivering new AI-capable models in 2024. These initiatives will bolster refresh demand, particularly in the commercial sector. The total shipment share of AI-capable PCs is expected to be about 19% in 2024. This accounts for all M-series Mac products alongside the nascent offerings expected in the Windows ecosystem. However, as more compelling use-cases emerge and AI functionality becomes an expected feature, Canalys anticipates a fast ramp up in the development and adoption of AI-capable PCs."

Texas Instruments (TI) today broke ground on its new 300-mm semiconductor wafer fabrication plant (or "fab") in Lehi, Utah. Joined by Utah Governor Spencer Cox, state and local elected officials, as well as community leaders, TI President and Chief Executive Officer Haviv Ilan celebrated the first steps toward construction of the new fab, LFAB2, which will connect to the company's existing 300-mm wafer fab in Lehi. Once completed, TI's two Utah fabs will manufacture tens of millions of analog and embedded processing chips every day at full production.

"Today we take an important step in our company's journey to expand our manufacturing footprint in Utah. This new fab is part of our long-term, 300-mm manufacturing roadmap to build the capacity our customers will need for decades to come," said Ilan. "At TI, our passion is to create a better world by making electronics more affordable through semiconductors. We are proud to be a growing member of the Utah community, and to manufacture analog and embedded processing semiconductors that are vital for nearly every type of electronic system today."

Yangtze Memory Technologies Corp (YMTC), China's biggest NAND flash memory manufacturer, has successfully raised billions of US Dollars in new capital to adapt to challenging US restrictions. According to the report from Financial Times, YMTC, which was added to a trade blacklist in December and barred from procuring US equipment to manufacture chips, exceeded its funding target. However, the exact amount remains undisclosed. The capital increase became necessary due to YMTC's substantial spending on finding alternative equipment and developing new components and core chipmaking tools. This financing round was oversubscribed by domestic investors, reflecting support for YMTC amid tightening US restrictions.

Last year, YMTC managed to raise 50 billion Chinese Yuan or about 7 billion US Dollars for equipment. Spending it all on the supply chain, the company is now looking to bolster its offerings with additional equipment for its memory facilities. One of the investors in the funding rally for YMTC has made a statement for Finanical Times: "If Chinese companies have equipment that can be used, [YMTC] will use it. If not, it will see if countries other than the US can sell to it. If that doesn't work, YMTC will develop it together with the supplier." This statement indicates that the company is looking into several options, where one is simply developing its custom machinery with the suppliers.

The U.S. Commerce Department seems to have thrown a big spanner into the NVIDIA machinery, by informing the company that some US$5 billion worth of AI chip orders for China falls under the latest US export restrictions. The orders are said to have been heading for Alibaba, ByteDance and Baidu, as well as possibly other major tech companies in China. This made NVIDIA's shares drop sharply when the market opened in the US earlier today, by close to five percent, dropping NVIDIA's market cap below the US$1 Trillion mark. The share price recovered somewhat in the afternoon, putting NVIDIA back in the trillion dollar club.

Based on a statement to Reuters, NVIDIA doesn't seem overly concerned, despite what appears to be huge loss in sales, with a company spokesperson issuing the following statement "These new export controls will not have a meaningful impact in the near term". The US government will implement these new export restrictions from November, which obviously didn't give NVIDIA much of a chance to avoid them and it looks as if the company is going to have to find new customers for the AI chips. Considering the current demand for NVIDIA's chips, this might not be too much of a challenge for the company though.

According to a news post by Reuters, Vietnam is the latest nation that is trying to become a semiconductor manufacturing nation, albeit its plans are nothing like what China is doing, instead the nation is trying to woo existing semiconductor companies to build fabs in Vietnam. The nation has been building its high-tech industry over a few years now and although it's nowhere near some of its neighbouring nations, Vietnam is likely to become an important player when it comes to assembly in the not too distant future, alongside India. However, fabricating semiconductors is a big leap from assembling smartphones, computers and EVs and requires a highly skilled workforce, something which is already becoming an issue in nations like Taiwan and Singapore.

Reuters reports that Vietnam has approached both GlobalFoundries and Taiwanese Powerchip Semiconductor Manufacturing Corporation, or PSMC for short. PSMC is among the top 10 foundries in the world, despite only having a mere five fabs, all of which are located in Taiwan. PSMC's main focus is the automotive industry and might be the more likely candidate to consider Vietnam of the two. Neither company has made any kind of commitment to invest in Vietnam. However, building a fab in a nation that doesn't have a semiconductor industry brings with it several challenges, least not supply chain related ones. Reuters mentioned a speech by Synopsys VP Robert Li which he held at the Vietnam Semiconductor Summit, where he mentions that building a foundry in Vietnam might cost as much as US$50 billion, which doesn't seem like a very appealing proposal to any company considering opening up a foundry in the nation.

The Chinese semiconductor industry is advancing, and interestingly, it is growing rapidly under sanctions, even with the blacklisting of companies by the US government. China's semiconductor industry is mainly represented by companies like Semiconductor Manufacturing International Corp (SMIC) and Huawei Technologies, who are leading the investment and progress in both chip manufacturing and chip design. According to the latest interview with Bloomberg, former TSMC Vice President Burn J. Lin said that the US government and its sanctions can not stop the advancement of Chinese semiconductor companies. Currently, Lin notes that SMIC and Huawei can use older machinery to produce more advanced chips.

Even so, SMIC could progress to 5 nm technology using existing equipment, particularly with scanners and other machinery from ASML. Development under sanctions would also force China to experiment with new materials and other chip packaging techniques that yield higher performance targets. SMIC has already developed a 7 nm semiconductor manufacturing node, which Huawei used for its latest Mate 60 Pro smartphone, based on Huawei's custom HiSilicon Kirin 9000S chip. Similarly, the transition is expected to happen to the 5 nm node as well, and it is only a matter of time before we see other nodes appear. "It is just not possible for the US to completely prevent China from improving its chip technology," noted Burn J. Lin.

Thanks to the information from Windows Report, we have received numerous details regarding Qualcomm's upcoming Snapdragon Elite X chip for laptops. The Snapdragon Elite X SoC is built on top of Nuvia-derived Oryon cores, which Qualcomm put 12 off in the SoC. While we don't know their base frequencies, the all-core boost reaches 3.8 GHz. The SoC can reach up to 4.3 GHz on single and dual-core boosting. However, the slide notes that this is all pure "big" core configuration of the SoC, so no big.LITTLE design is done. The GPU part of Snapdragon Elite X is still based on Qualcomm's Adreno IP; however, the performance figures are up significantly to reach 4.6 TeraFLOPS of supposedly FP32 single-precision power. Accompanying the CPU and GPU, there are dedicated AI and image processing accelerators, like Hexagon Neural Processing Unit (NPU), which can process 45 trillion operations per second (TOPS). For the camera, the Spectra Image Sensor Processor (ISP) is there to support up to 4K HDR video capture on a dual 36 MP or a single 64 MP camera setup.

The SoC supports LPDDR5X memory running at 8533 MT/s and a maximum capacity of 64 GB. Apparently, the memory controller is an 8-channel one with a 16-bit width and a maximum bandwidth of 136 GB/s. Snapdragon Elite X has PCIe 4.0 and supports UFS 4.0 for outside connection. All of this is packed on a die manufactured by TSMC on a 4 nm node. In addition to marketing excellent performance compared to x86 solutions, Qualcomm also advertises the SoC as power efficient. The slide notes that it uses 1/3 of the power at the same peak PC performance of x86 offerings. It is also interesting to note that the package will support WiFi7 and Bluetooth 5.4. Officially coming in 2024, the Snapdragon Elite X will have to compete with Intel's Meteor Lake and/or Arrow Lake, in addition to AMD Strix Point.