Amidst escalating tensions in the U.S.-China semiconductor industry, Huawei is reportedly working on a new AI chip called the Ascend 910C. This development appears to be the Chinese tech giant's attempt to compete with NVIDIA's AI processors in the Chinese market. According to a Wall Street Journal report, Huawei has begun testing the Ascend 910C with various Chinese internet and telecom companies to evaluate its performance and capabilities. Notable firms such as ByteDance, Baidu, and China Mobile are said to have received samples of the chip.

Huawei has reportedly informed its clients that the Ascend 910C can match the performance of NVIDIA's H100 chip. The company has been conducting tests for several weeks, suggesting that the new processor is nearing completion. The Wall Street Journal indicates that Huawei could start shipping the chip as early as October 2024. The report also mentions that Huawei and potential customers have discussed orders for over 70,000 chips, potentially worth $2 billion.

Today SiFive, Inc., the gold standard for RISC-V computing, announced its new SiFive Performance P870-D datacenter processor to meet customer requirements for highly parallelizable infrastructure workloads including video streaming, storage, and web appliances. When used in combination with products from the SiFive Intelligence product family, datacenter architects can also build an extremely high-performance, energy efficient compute subsystem for AI-powered applications.

Building on the success of the P870, the P870-D supports the open AMBA CHI protocol so customers have more flexibility to scale the number of clusters. This scalability allows customers to boost performance while minimizing power consumption. By harnessing a standard CHI bus, the P870-D enables SiFive's customers to scale up to 256 cores while harnessing industry-standard protocols, including Compute Express Link (CXL) and CHI chip to chip (C2C), to enable coherent high core count heterogeneous SoCs and chiplet configurations.

Akeana, the company committed to driving dramatic change in semiconductor IP innovation and performance, has announced its official company launch approximately three years after its foundation, having raised over $100 million in capital, with support from A-list investors including Kleiner Perkins, Mayfield, and Fidelity. Today's launch marks the formal availability of the company's expansive line of IP solutions that are uniquely customizable for any workload or application.

Formed by the same team that designed Marvell's ThunderX2 server chips, Akeana offers a variety of IP solutions, including microcontrollers, Android clusters, AI vector cores and subsystems, and compute clusters for networking and data centers. Akeana moves the industry beyond the status quo of legacy vendors and architectures, like Arm, with equitable licensing options and processors that fill and exceed current performance gaps.

Samsung Electronics has achieved a significant milestone in its pursuit of supplying advanced memory chips for AI systems. Their latest fifth-generation high-bandwidth memory (HBM) chips, known as HBM3E, have finally passed all NVIDIA's tests. This approval will help Samsung in catching up with competitors SK Hynix and Micron in the race to provide HBM memory chips to NVIDIA. While a supply deal hasn't been finalized yet, deliveries are expected to start in late 2024.

However, it's worth noting that Samsung passed NVIDIA's tests for the eight-layer HBM3E chips while the more advanced twelve-layer version of the HBM3E chips is still struggling pass those tests. Both Samsung and NVIDIA declined to comment on these developments. Industry expert Dylan Patel notes that while Samsung is making progress, they're still behind SK Hynix, which is already preparing to ship its own twelve-layer HBM3E chips.

Silicon Motion Technology Corporation, a global leader in designing and marketing NAND flash controllers for solid-state storage devices, today announced SM2508, the best power efficiency PCIe Gen 5 NVMe 2.0 client SSD controller for AI PCs and gaming consoles. It's the world's first PCIe Gen 5 client SSD controller using TSMC's 6 nm EUV process, offering a 50% reduction in power consumption compared to competitive offerings in the 12 nm process. With less than 7 W power consumption for the entire SSD, it delivers 1.7x better power efficiency than PCIe Gen 4 SSDs and up to 70% better than current competitive PCIe Gen 5 offerings on the market. Silicon Motion will be showcasing its SM2508 based SSD design and other innovations during the Future of Memory and Storage event from Aug. 6 to 8 at booth #315:

Silicon Motion's SM2508 is a superior-performance, low-power PCIe Gen 5 x4 NVMe 2.0 SSD controller designed for AI-capable PC notebooks. It supports eight NAND channels with up to 3,600 MT/s per channel, delivering sequential performance speeds of up to 14.5 GB/s and 13.6 GB/s and random performance speeds of up to 2.5M IOPS, providing up to 2x higher performance than PCIe Gen 4 products. The SM2508 maximizes PCIe Gen 5 performance with an impressive power consumption of approximately 3 W. It features Silicon Motion's proprietary 8th-generation NANDXtend technology, which includes an on-disk training algorithm designed to reduce ECC timing. This enhancement boosts performance and maximizes power efficiency while ensuring compatibility with the latest 3D TLC/QLC NAND technologies, enabling higher data density and meeting the evolving demands of next-generation AI PCs.

Ampere has announced a significant update to its product roadmap, highlighting the upcoming 512-core AmpereOne Aurora processor. This new chip is specifically designed to address the growing demands of cloud-native AI computing.

The newly announced AmpereOne Aurora 512 cores processor integrates AI acceleration and on-chip High Bandwidth Memory (HBM), promising three times the performance per rack compared to current AmpereOne processors. Aurora is designed to handle both AI training and inference workloads, indicating Ampere's commitment to becoming a major player in the AI computing space.

Weebit Nano Limited, a leading developer and licensor of advanced memory technologies for the global semiconductor industry, and tier-1 semiconductor foundry DB HiTek have taped-out (released to manufacturing) a demonstration chip integrating Weebit's embedded Resistive Random-Access Memory (ReRAM or RRAM) module in DB HiTek's 130 nm Bipolar-CMOS-DMOS (BCD) process. The highly integrated demo chips will be used for testing and qualification ahead of customer production, while demonstrating the performance and robustness of Weebit's technology.

This important milestone in the collaboration between Weebit and DB HiTek (previously announced on 19 October 2023) was completed on-schedule as part of the technology transfer process. The companies are working to make Weebit ReRAM available to DB HiTek customers for integration in their systems on chips (SoCs) as embedded non-volatile memory (NVM), and aim to have the technology qualified and ready for production in the second quarter of the 2025 calendar year. Weebit ReRAM is available now to select DB HiTek customers for design prototyping ahead of production.

Samsung Electronics today reported financial results for the second quarter ended June 30, 2024. The Company posted KRW 74.07 trillion in consolidated revenue and operating profit of KRW 10.44 trillion as favorable memory market conditions drove higher average sales price (ASP), while robust sales of OLED panels also contributed to the results.

Memory Market Continues To Recover; Solid Second Half Outlook Centered on Server Demand
The DS Division posted KRW 28.56 trillion in consolidated revenue and KRW 6.45 trillion in operating profit for the second quarter. Driven by strong demand for HBM as well as conventional DRAM and server SSDs, the memory market as a whole continued its recovery. This increased demand is a result of the continued AI investments by cloud service providers and growing demand for AI from businesses for their on-premise servers.

Imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, today announced the demonstration of high quality 300 mm-Si-based quantum dot spin qubit processing with devices resulting in a statistically relevant, average charge noise of 0.6µeV/√ Hz at 1 Hz. In view of noise performance, the values obtained are the lowest charge noise values achieved on a 300 mm fab-compatible platform.

Such low noise values enable high-fidelity qubit control, as reducing the noise is critical for maintaining quantum coherence and high fidelity control. By demonstrating those values, repeatedly and reproducibly, on a 300 mm Si MOS quantum dot process, this work makes large-scale quantum computers based on Si quantum dots a realistic possibility.

Chinese memory manufacturer YMTC has filed a lawsuit against U.S.-based Micron in California, alleging infringement of 11 patents related to 3D NAND Flash and DRAM products. YMTC seeks to halt Micron's sales of the allegedly infringing products in the U.S. and demands royalty payments. Founded in Wuhan, China, in 2016, YMTC is a key player in China's efforts to develop a domestic chip industry. However, in October 2022, the U.S. government placed YMTC on its Entity List, restricting its access to advanced U.S. manufacturing equipment for 3D NAND chips with 128 layers or more.

Before these restrictions, YMTC had obtained certification from Apple for its 128-layer 3D NAND chips, with the US tech giant considering using YMTC chips to reduce costs and diversify its supply chain beyond Samsung, SK Hynix and Micron. The lawsuit specifically targets Micron's 3D NAND Flash products with 96, 128, 176, and 232 layers, as well as certain DDR5 SDRAM products. This legal action follows a similar suit filed by YMTC against Micron in November, alleging infringement of eight U.S. patents related to 3D NAND Flash. With government backing, Chinese firms are increasingly engaging in patent litigation both domestically and internationally. Last year alone, Chinese courts handled over 5,000 technical intellectual property and monopoly cases.

Avnet ASIC, a division of Avnet Silica, an Avnet company, today announced that it has launched its new ultra-low-power design services for TSMC's cutting-edge 4 nm and below process technologies. These services are designed to enable customers to achieve exceptional power efficiency and performance in their high-performance applications, such as blockchain and AI edge computing. TSMC is the world's leading silicon foundry and Avnet ASIC division is a leading provider of ASIC and SoC full turnkey solutions.

The new design services leverage a comprehensive approach to address the challenges of operating at extreme low-voltage conditions in the 4 nm and below nodes. This includes recharacterizing standard cells for lower voltages, performing early RTL exploration to optimize power, performance, and area (PPA) tradeoffs, implementing an optimized clock tree, and utilizing transistor-level simulations to enhance the power optimization process.

According to The Information, OpenAI is reportedly in talks with Broadcom about developing a custom AI accelerator to power OpenAI's growing demand for high-performance solutions. Broadcom is a fabless chip designer known for a wide range of silicon solutions spanning from networking, PCIe, SSD controllers, and PHYs all the way up to custom ASICs. The latter part is what OpenAI wants to focus on, but all the aforementioned IP developed by Broadcom is of use in a data center. Suppose OpenAI decides to use Broadcom's solutions. In that case, the fabless silicon designer offers a complete vertical stack of products for inter-system communication using various protocols such as PCIe, system-to-system communication using Ethernet networking with Broadcom Tomahawk 6 and future revisions, alongside storage solutions and many other complimentary elements of a data center.

As a company skilled in making various IPs, it also makes ASIC solutions for other companies and has assisted Google in the making of its Tensor Processing Unit (TPU), which is now in its sixth generation. Google TPUs are massively successful as Google deploys millions of them and provides AI solutions to billions of users across the globe. Now, OpenAI wants to be part of the AI chip game, and Broadcom could come to the rescue with its already-established AI success and various other data center componentry to help make a custom AI accelerator to power OpenAI's infrastructure needed for the next generation of AI models. With each new AI model released by OpenAI, compute demand spikes by several orders of magnitude, and having an AI accelerator that exactly matches their need will help the company move faster and run even bigger AI models.

New insights from Omdia's Desktop Monitor Intelligence Service show the gaming monitor market, featuring refresh rates over 120 Hz, is expected to grow by 9% YoY to 24.7 million units in 2024. Meanwhile, the smart monitor market, equipped with operating systems and streaming service portals, is projected to expand by 63% YoY to 1.2 million units.

In 1Q24, desktop monitor shipments hit 30.7 million units, a 5% increase year-on-year (YoY). The industry has been growing steadily since 3Q23, overcoming post-pandemic logistical disruptions. Notably, the gaming monitor market and smart monitors are expanding rapidly. This growth is driven by added value and high functionality, particularly in both monitor categories.

OPENEDGES Technology, Inc the leading provider of memory subsystem IP, is pleased to announce that its subsidiary, The Six Semiconductor Inc (TSS), has successfully brought-up and validated its HBM3 testchip in 7 nm process technology. The IP validation testchip and the HBM3 PHY were brought up within the first month to 6.4 Gbps, and further tuning has resulted in successful operation of the HBM3 memory subsystem overclocked to 7.2 Gbps.

To date, there are only a handful of IP vendors that have taped out and demonstrated HBM3 memory subsystems, as test shuttle and HBM3 DRAM die stack sample availability are both highly limited. OPENEDGES is thrilled to be amongst one of the few companies to have demonstrated an HBM3 memory subsystem in silicon.

AMD reportedly plans to incorporate glass substrates into its high-performance system-in-packages (SiPs) sometimes between 2025 and 2026. Glass substrates offer several advantages over traditional organic substrates, including superior flatness, thermal properties, and mechanical strength. These characteristics make them well-suited for advanced SiPs containing multiple chiplets, especially in data center applications where performance and durability are critical. The adoption of glass substrates aligns with the industry's broader trend towards more complex chip designs. As leading-edge process technologies become increasingly expensive and yield gains diminish, manufacturers turn to multi-chiplet designs to improve performance. AMD's current EPYC server processors already incorporate up to 13 chiplets, while its Instinct AI accelerators feature 22 pieces of silicon. A more extreme testament is Intel's Ponte Vecchio, which utilized 63 tiles in a single package.

Glass substrates could enable AMD to create even more complex designs without relying on costly interposers, potentially reducing overall production expenses. This technology could further boost the performance of AI and HPC accelerators, which are a growing market and require constant innovation. The glass substrate market is heating up, with major players like Intel, Samsung, and LG Innotek also investing heavily in this technology. Market projections suggest explosive growth, from $23 million in 2024 to $4.2 billion by 2034. Last year, Intel committed to investing up to 1.3 trillion Won (almost one billion USD) to start applying glass substrates to its processors by 2028. Everything suggests that glass substrates are the future of chip design, and we await to see first high-volume production designs.

Applied Materials, Inc. today introduced materials engineering innovations designed to increase the performance-per-watt of computer systems by enabling copper wiring to scale to the 2 nm logic node and beyond. "The AI era needs more energy-efficient computing, and chip wiring and stacking are critical to performance and power consumption," said Dr. Prabu Raja, President of the Semiconductor Products Group at Applied Materials. "Applied's newest integrated materials solution enables the industry to scale low-resistance copper wiring to the emerging angstrom nodes, while our latest low-k dielectric material simultaneously reduces capacitance and strengthens chips to take 3D stacking to new heights."

Overcoming the Physics Challenges of Classic Moore's Law Scaling
Today's most advanced logic chips can contain tens of billions of transistors connected by more than 60 miles of microscopic copper wiring. Each layer of a chip's wiring begins with a thin film of dielectric material, which is etched to create channels that are filled with copper. Low-k dielectrics and copper have been the industry's workhorse wiring combination for decades, allowing chipmakers to deliver improvements in scaling, performance and power-efficiency with each generation.

Samsung Electronics, a world leader in advanced semiconductor technology, today announced that it will provide turnkey semiconductor solutions using the 2-nanometer (nm) foundry process and the advanced 2.5D packaging technology Interposer-Cube S (I-Cube S) to Preferred Networks, a leading Japanese AI company.

By leveraging Samsung's leading-edge foundry and advanced packaging products, Preferred Networks aims to develop powerful AI accelerators that meet the ever-growing demand for computing power driven by generative AI.

In 2016, TSMC developed and named its InFO FOWLP technology, and applied it to the A10 processor used in the iPhone 7. TrendForce points out that since then, OSAT providers have been striving to develop FOWLP and FOPLP technologies to offer more cost-effective packaging solutions.

Starting in the second quarter, chip companies like AMD have actively engaged with TSMC and OSAT providers to explore the use of FOPLP technology for chip packaging and helping drive industry interest in FOPLP. TrendForce observes that there are three main models for introducing FOPLP packaging technology: Firstly, OSAT providers transitioning from traditional methods of consumer IC packaging to FOPLP. Secondly, foundries and OSAT providers packaging AI GPUs that are transitioning 2.5D packaging from wafer level to panel level. Thirdly, panel makers who are packaging consumer ICs.

Ansys power integrity solutions have been certified by Samsung Foundry for use with Samsung's new SF2Z 2 nm gate-all-around manufacturing technology. SF2Z includes advanced technology that moves the power distribution network to the backside of the chip — saving space, lowering costs, and improving performance. Ansys solutions enable early adopters of Samsung's technology to design leading-edge semiconductor products for HPC, smartphones, AI, data center communication, and graphics processors.

The certification includes RedHawk-SC, which provides predictively accurate signoff verification for electromigration and voltage drop (IR drop) on power distribution networks for digital designs. In addition, the Totem power integrity platform provides comprehensive evaluation for analog and mixed-signal designs. Both RedHawk-SC and Totem signoff capabilities can reduce project risk, improve reliability, and extend the longevity of chips.

TrendForce has observed that in 2024, major CSPs such as Microsoft, Google, Meta, and AWS will continue to be the primary buyers of high-end AI servers, which are crucial for LLM and AI modeling. Following establishing a significant AI training server infrastructure in 2024, these CSPs are expected to actively expand into edge AI in 2025. This expansion will include the development of smaller LLM models and setting up edge AI servers to facilitate AI applications across various sectors, such as manufacturing, finance, healthcare, and business.

Moreover, AI PCs or notebooks share a similar architecture to AI servers, offering substantial computational power and the ability to run smaller LLM and generative AI applications. These devices are anticipated to serve as the final bridge between cloud AI infrastructure and edge AI for small-scale training or inference applications.

A Finnish company called Flow Computing is making some very bold claims when it comes to its new IP. The company has developed what it calls a Parallel Processing Unit or a PPU, which the company claims can boost the performance of any CPU by a hundred times its current performance. Furthermore, the company claims that its PPU can double the performance of any current code execution, with no need for any kind of optimisation for its PPU. The PPU can be integrated into new processors, but it can also be designed as a discrete chip that can be added to any current hardware and Flow Computing claims the performance benefits will be the same in both instances.

Flow Computing is a spinoff from the VTT Technical Research Centre of Finland and the company emerged from stealth mode last week with around €4 million in funding. Flow Computing doesn't intend to make its PPU by itself, but instead, the company wants to licence its tech to third parties, to give everyone an equal opportunity to take advantage of what's on offer. At this point in time, Flow Computing hasn't made any custom silicon, instead the company has validated its PPU using an FPGA tested against various Intel CPUs. As such, there are numbers to back up its claims and we've provided links below to a whitepaper and an FAQ for those that are interested in doing a deep dive into its claims. Flow Computing appears to have a few different implementations of its PPU, ranging from 16 to 256 cores, with the latter being for high-end computers, but the basic is said to be suitable for something as basic as a smartwatch. Time will tell if Flow Computing will be able to deliver on its claims and it'll be an interesting company to follow.

MediaTek announced today at COMPUTEX 2024 that the company has joined Arm Total Design, a fast-growing ecosystem that aims to accelerate and simplify the development of products based on Arm Neoverse Compute Subsystems (CSS). Arm Neoverse CSS is designed to meet the performance and efficiency needs of AI applications in the data center, infrastructure systems, telecommunications, and beyond.

"Together with Arm, we're enabling our customers' designs to meet the most challenging workloads for AI applications, maximizing performance per watt," said Vince Hu, Corporate Vice President at MediaTek. "We will be working closely with Arm as we expand our footprint into data centers, utilizing our expertise in hybrid computing, AI, SerDes and chiplets, and advance packaging technologies to accelerate AI innovation from the edge to the cloud."

South Korea's stock of semiconductor chips dropped more than it has since 2014. This big decrease shows that customers are buying chips faster than companies can make them, as they need more equipment for developing artificial intelligence (AI) technology. Official data released on May 31 revealed that in April, chip inventories fell by 33.7% compared to a year earlier - the largest drop since late 2014. This is the fourth month in a row that inventories have declined, while at the same time South Korea's exports of semiconductors have gone up again. Additionally, South Korea's production of chips rose 22.3% in April, which is less than the 30.2% increase from the previous month. Shipments from factories grew 18.6%, also lower than March's 16.4% growth.

South Korea is home to the two biggest memory chipmakers in the world (Samsung and SK Hynix), and they are competing to supply chips to NVIDIA, the latest having an insatiable appetite for more and more chips. These two Korean companies are in a race to develop a more advanced and more profitable version of high-bandwidth memory, or HBM. During the memory chip boom from 2013-2015, inventories didn't increase for about a year and a half. In the 2016-2017 cycle, inventory declines lasted nearly a year. A report from South Korea's central bank expects the latest surge in chip demand to continue at least until the first half of next year. This is because the "artificial intelligence boom" is driving up demand similarly to how cloud servers caused an expansion in 2016, and now mostly forgotten crypto-mining fever. South Korea will release its latest export data on June 1.

According to a report by KED Global, Korean chipmaking giant Samsung is ramping up its efforts to compete with global giants like TSMC and Intel. The latest partnership on the horizon is AMD's collaboration with Samsung. AMD is planning to utilize Samsung's cutting-edge 3 nm technology for its future chips. More specifically, AMD wants to utilize Samsung's gate-all-around FETs (GAAFETs). During ITF World 2024, AMD CEO Lisa Su noted that the company intends to use 3 nm GAA transistors for its future products. The only company offering GAAFETs on a 3 nm process is Samsung. Hence, this report from KED gains more credibility.

While we don't have any official information, AMD's utilization of a second foundry as a manufacturing partner would be a first for the company in years. This strategic move signifies a shift towards dual-sourcing, aiming to diversify its supply chain and reduce dependency on a single manufacturer, previously TSMC. We still don't know what specific AMD products will use GAAFETs. AMD could use them for CPUs, GPUs, DPUs, FPGAs, and even data center accelerators like Instinct MI series.

Silicon Motion Technology Corporation ("Silicon Motion"), a global leader in designing and marketing NAND flash controllers for solid-state storage devices, today launched the SM2322, the industry's fastest single-chip high-performance, low-power, and cost-effective solution for external portable SSDs, supporting up to 8 TB of storage and achieves unparalleled data transfer rates of 20 Gbps for storing and accessing large amounts of content seamlessly from AI smartphones, high-performance multimedia devices, and game consoles.

With the increase of AI-capable devices, high density and high-performance storage solutions are becoming more critical to consumers. Portable SSDs powered by the new SM2322 controller are the only solution that offers low-cost, high-density and high-performance, making it the ideal solution for these applications. Equipped with a USB 3.2 Gen 2x2 interface with 20 Gb/s bandwidth and fully integrated hardware and software solution delivering peak sequential read and write transfer speeds of 2,100 MB/s and 2,000 MB/s, respectively, with up to 8 TB capacity, SM2322 powered high-performance portable SSDs enable an ultra-compact and lightweight form factor. The SM2322 supports the ProRes format and MFi specification for iPhone users while also being compatible with Windows, Android OS, and macOS, making it an ideal high-density, high-performance portable storage solution for AI smartphones, HD content creators, and gaming enthusiasts who require high-density, high-performance portable storage.