AMD "Granite Ridge" is codename for the four new Ryzen 9000 series desktop processors the company plans to launch on July 31, 2024. The processor is built in the Socket AM5 package, and is meant to be backwards compatible with AMD 600-series chipset motherboards, besides the new 800-series chipset ones that will launch alongside. "Granite Ridge" is a chiplet-based processor, much like the Ryzen 7000 "Raphael," Ryzen 5000 "Vermeer," and Ryzen 3000 "Matisse." AMD is carrying over the 6 nm client I/O die over from "Raphael" in an effort to minimize development costs, much in the same way it carried over the 12 nm cIOD for "Vermeer" from "Matisse."

The SoC I/O features of "Granite Ridge" are contemporary, with its awesome 28-lane PCI-Express Gen 5 root complex that allows a PCI-Express 5.0 x16, two CPU-attached M.2 Gen 5 slots, and a Gen 5 x4 chipset bus. There's also a basic integrated graphics solution based on the older RDNA 2 graphics architecture; which should make these processors fit for all use-cases that don't need discrete graphics. The iGPU even has multimedia accelerators, an audio coprocessor, a display controller, and USB 3.2 interfaces from the processor.Moving over to the CPU complex dies (CCDs), which are at the heart of AMD's innovation; and the company confirmed that the 8-core "Zen 5" CCDs, internally referred to as "Eldora," are built on the TSMC N4P foundry node. Compared to the N5 node the "Zen 4" CCD is built on, the N4P node offers a massive 22% power reduction at the node level, a 6% performance improvement, and a 6% improvement in transistor density. TSMC's N4X node hasn't ramped, and the foundry targets it for HPC processors. Mass production of "Eldora" would have started around early-mid H1-2024, by which time N4X wouldn't have been ready for mass-production.

Each of the up to two CCDs talk to the cIOD over IFoP (Infinity Fabric over Package), with the same 32B/cycle per port reads, and 16B/cycle per port writes. Each CCD has eight full-sized "Zen 5" CPU cores, with their 512-bit FP data-paths fully available. Each of the eight cores has a 1 MB dedicated L2 cache, and the eight share a 32 MB L3 cache. The only other components on the CCD are the IFoP interface, and an SMU.