The first die shot of AMD's new 4 nm "Strix Point" mobile processor surfaced, thanks to an enthusiast on Chinese social media. "Strix Point" is a significantly larger die than "Phoenix." It measures 12.06 mm x 18.71 mm (L x W), compared to the 9.06 mm x 15.01 mm of "Phoenix." Much of this die size increase comes from the larger CPU, iGPU, and NPU. The process has been improved from TSMC N4 on "Phoenix" and its derivative "Hawk Point," to the newer TSMC N4P node.

Nemez (GPUsAreMagic) annotated the die shot in great detail. The CPU now has 12 cores spread across two CCX, one of which contains four "Zen 5" cores sharing a 16 MB L3 cache; and the other with eight "Zen 5c" cores sharing an 8 MB L3 cache. The two CCXs connect to the rest of the chip over Infinity Fabric. The rather large iGPU takes up the central region of the die. It is based on the RDNA 3.5 graphics architecture, and features 8 workgroup processors (WGPs), or 16 compute units (CU) worth 1,024 stream processors. Other key components include four render backends worth 16 ROPs, and control logic. The GPU has its own 2 MB of L2 cache that cushions transfers to the Infinity Fabric.

AMD "Granite Ridge" is codename for the four new Ryzen 9000 series desktop processors the company plans to launch on July 31, 2024. The processor is built in the Socket AM5 package, and is meant to be backwards compatible with AMD 600-series chipset motherboards, besides the new 800-series chipset ones that will launch alongside. "Granite Ridge" is a chiplet-based processor, much like the Ryzen 7000 "Raphael," Ryzen 5000 "Vermeer," and Ryzen 3000 "Matisse." AMD is carrying over the 6 nm client I/O die over from "Raphael" in an effort to minimize development costs, much in the same way it carried over the 12 nm cIOD for "Vermeer" from "Matisse."

The SoC I/O features of "Granite Ridge" are contemporary, with its awesome 28-lane PCI-Express Gen 5 root complex that allows a PCI-Express 5.0 x16, two CPU-attached M.2 Gen 5 slots, and a Gen 5 x4 chipset bus. There's also a basic integrated graphics solution based on the older RDNA 2 graphics architecture; which should make these processors fit for all use-cases that don't need discrete graphics. The iGPU even has multimedia accelerators, an audio coprocessor, a display controller, and USB 3.2 interfaces from the processor.

AMD is about give the new "Zen 5" microarchitecture a near-simultaneous launch across both its client segments—desktop and mobile. The desktop front is held by the Ryzen 9000 "Granite Ridge" Socket AM5 processors; while Ryzen AI 300 "Strix Point" powers the company's crucial effort to capture Microsoft Copilot+ AI PC market share. We recently did a technical deep-dive on the two. HardwareLuxx.de scored two important bits of specs for both processors in its Q&A interaction with AMD—die sizes and transistor counts.

To begin with, "Strix Point" is a monolithic silicon, which is confirmed to be built on the TSMC N4P foundry node (4 nm). This is a slight upgrade over the N4 node that the company built its previous generation "Phoenix" and "Hawk Point" processors on. The "Strix Point" silicon measures 232.5 mm² in area, which is significantly larger than the 178 mm² of "Hawk Point" and "Phoenix." The added die area comes from there being 12 CPU cores instead of 8, and 16 iGPU compute units instead of 12; and a larger NPU. There are many other factors, such as the larger 24 MB CPU L3 cache; and the sizes of the "Zen 5" and "Zen 5c" cores themselves.

TSMC today unveiled its newest semiconductor process, advanced packaging, and 3D IC technologies for powering the next generation of AI innovations with silicon leadership at the Company's 2024 North America Technology Symposium. TSMC debuted the TSMC A16 technology, featuring leading nanosheet transistors with innovative backside power rail solution for production in 2026, bringing greatly improved logic density and performance. TSMC also introduced its System-on-Wafer (TSMC-SoW) technology, an innovative solution to bring revolutionary performance to the wafer level in addressing the future AI requirements for hyperscaler datacenters.

This year marks the 30th anniversary of TSMC's North America Technology Symposium, and more than 2,000 attended the event, growing from less than 100 attendees 30 years ago. The North America Technology Symposium in Santa Clara, California kicks off TSMC Technology Symposiums around the world in the coming months. The symposium also features an "Innovation Zone," designed to highlight the technology achievements of our emerging start-up customers.

AMD's upcoming server processor, the 5th Gen EPYC "Turin," has been pictured as an engineering sample is probably being evaluated by the company's data-center or cloud customers. The processor has a mammoth core-count of 192-core/384-thread in its high-density cloud-focused variant that uses "Zen 5c" CPU cores. Its regular version that uses larger "Zen 5" cores that can sustain higher clock speeds, also comes with a fairly high core-count of 128-core/256-thread, up from the 96-core/192-thread of the "Zen 4" based EPYC "Genoa."

The EPYC "Turin" server processor based on "Zen 5" comes with an updated sIOD (server I/O die), surrounded by as many as 16 CCDs (CPU complex dies). AMD is expected to build these CCDs on the TSMC N4P foundry node, which is a more advanced version of the TSMC N4 node the company currently uses for its "Phoenix" client processors, and the TSMC N5 node it uses for its "Zen 4" CCD. TSMC claims that the N4P node offers an up to 22% improvement in power efficiency over N5, as well as a 6% increase in transistor density. Each of the "Zen 5" CCDs is confirmed to have 8 CPU cores sharing 32 MB L3 cache memory. A total of 16 such CCDs add up to the processor's 128-core/256-thread number. The high-density "Turin" meant for cloud data-centers, is a whole different beast.

Sony is developing the PlayStation 5 Pro console that targets higher refresh-rate gaming at 4K Ultra HD, or higher in-game eye-candy, given its faster hardware. Details about the console are few and far between, given its late-2024 tentative release, but by now the company would have co-developed its semi-custom SoC, so it could spend the next year extensively testing and optimizing it, before mass production in the 2-3 quarters leading up to the launch. Kepler_L2 and Tom Henderson on Twitter are fairly reliable sources for PlayStation hardware leaks, and piecing their recent posts together, VideoCardz compiled the most probable specs of the SoC at the heart of the PlayStation 5 Pro.

The semi-custom SoC powering the PlayStation 5 Pro is co-developed by Sony Computer Entertainment (SCE) and AMD; and is codenamed "Viola." The monolithic chip is built on the TSMC N4P foundry node (4 nm EUV), which is a big upgrade from the 7 nm DUV node on which the "Oberon" SoC powering the original PlayStation 5, and 6 nm DUV node powering the "Oberon Plus" SoC of the refreshed PS5, are based on. Sony is leaving the CPU component largely untouched, it is an 8-core/16-thread unit based on the "Zen 2" microarchitecture, spread across two 4-core CCXs. The CPU has a maximum boost frequency of 4.40 GHz, dialed up from the 3.50 GHz maximum boost of "Oberon." The iGPU is where all the magic happens.

TSMC today showcased its latest technology developments at its 2023 North America Technology Symposium, including progress in 2 nm technology and new members of its industry-leading 3 nm technology family, offering a range of processes tuned to meet diverse customer demands. These include N3P, an enhanced 3 nm process for better power, performance and density, N3X, a process tailored for high performance computing (HPC) applications, and N3AE, enabling early start of automotive applications on the most advanced silicon technology.

With more than 1,600 customers and partners registered to attend, the North America Technology Symposium in Santa Clara, California is the first of the TSMC's Technology Symposiums around the world in the coming months. The North America symposium also features an Innovation Zone spotlighting the exciting technologies of 18 emerging start-up customers.

A technology tipster has been dropping multiple tidbits this week about Qualcomm's upcoming Snapdragon 8 Gen 3 mobile chipset - this follows a leak (from a different source, going back to mid-April) about the next generation Adreno 750 GPU getting tuned up for a battle against Apple's Bionic A17 in terms of graphics benchmarks. The latest leak points to the GPU being clocked at 900 MHz, rather than the rumored higher figure of 1.0 GHz speed (garnered from tests at Qualcomm's labs). The focus has now turned to the next generation flagship Snapdragon's CPU aspect, with information emerging about core clock speeds and multiple cluster configurations.

Revegnus suggests that the Snapdragon 8 Gen 3 (SD8G3) chipset will be packing a large primary core in the shape of Arm's Cortex-X4 CPU with a reported maximum clock speed of 3.40 GHz. Leaks from the past have posited that the SD8G3 would feature a fairly standard 1x Large + 5x Big + 2x Small CPU core layout (with clocks predicted to be: large Cortex X4 at 3.2 GHz, big Cortex-A720 at 3.0 GHz, and small Cortex-A520 at 2.0 GHz). An insider source has provided Revegnus with additional information about two different CPU core configurations - 1+5+2 and 2+4+2 - it is theorized that smartphone manufacturers will be offered the latter layout as an exclusive option for special edition flagship phones. The more powerful 2+4+2 variant is said to sacrifice a big core (A720) in favor of a dual Cortex X4 headliner, although the resultant thermal output of twin large cores could prove to be problematic.

Early details of MediaTek's next generation mobile chipset have emerged this week, courtesy of renowned leaker Digital Chat Station via their blog on Weibo. The successor to MediaTek's current flagship Dimensity 9200 mobile chipset will likely be called "Dimensity 9300" - a very imaginative bump up in numbering - with smartphone brand Vivo involved as a collaborator. The tipster thinks that the fabless semiconductor company has contracted with TSMC for fabrication of the Dimensity 9300 chipset - and the foundry's N4P process has been selected by MediaTek, which could provide a bump in generational performance when compared to the older 4 nm and 5 nm standards used for past Dimensity SoC ranges. It should be noted that the current generation Dimensity 9200 chipset is presently manufactured via TSMC's N4P process.

MediaTek is seeking to turnaround its fortunes in the area of flagship mobile chipsets - industry watchdogs have cited a limited uptake of the Taiwanese company's Dimensity 9200 SoC as a motivating factor in the creation of a very powerful successor. Digital Chat Station suggests that the upcoming 9300 model will pack enough of a hardware punch to rival Qualcomm's forthcoming Snapdragon 8 Gen 3 SoC - both chipsets are touted to release within the same time period of late 2023. According to previous speculation, Qualcomm has also contracted with TSMC's factory to pump out the Snapdragon 8 Gen 3 via the N4P (4 nm) process.

Cadence Design Systems, Inc. today announced that its digital and custom/analog design flows have been certified for the TSMC N3E and N4P processes, supporting the latest Design Rule Manual (DRM). In addition, Cadence and TSMC delivered N3E and N4P process design kits (PDKs) and design flows to accelerate customer adoption and advance mobile, AI and hyperscale computing design innovation. Joint customers are actively designing with the new N3E and N4P PDKs, and several test chips have already been taped out, which demonstrates how Cadence solutions help customers improve engineering efficiency and maximize the power, performance and area (PPA) benefits offered by the latest TSMC process technologies. The Cadence digital and custom/analog advanced-node solutions support the company's Intelligent System Design strategy, enabling system-on-chip (SoC) design excellence.

Cadence worked closely with TSMC to ensure the digital full flow was optimized for TSMC's advanced N3E and N4P process technologies. The complete RTL-to-GDS flow includes the Cadence Innovus Implementation System, Quantus Extraction Solution, Quantus Field Solver, Tempus Timing Signoff Solution and ECO option, Pegasus Verification System, Liberate Characterization Solution and Voltus IC Power Integrity Solution. Additionally, the Cadence Genus Synthesis Solution and predictive iSpatial technology are enabled for the TSMC N3E and N4P process technologies.

According to DigiTimes, TSMC is working on increased its monthly shipments of finished wafers from 120,000 to 150,000 for its 5 nm nodes, under which 4 nm also falls. This is three times as much as what TSMC was producing just a year ago. The 4 nm node is said to be in full mass production now and the enhanced N4P node should be ready for mass production in the second half of 2022, alongside N3B. This will be followed by the N4X and N3E nodes in 2023. The N3B node is expected to hit 40-50,000 wafers initially, before ramping up from there, assuming everything is on track.

The report also mentions that TSMC is expecting a 20 percent revenue increase from its 28 to 7 nm nodes this year, which shows that even these older nodes are being heavily utilised by its customers. TSMC has what NVIDIA would call a demand problem, as the company simply can't meet demand at the moment, with customers lining up to be able to get a share of any additional production capacity. NVIDIA is said to have paid TSMC at least US$10 billion in advance to secure manufacturing capacity for its upcoming products, both for consumer and enterprise products. TSMC's top three HPC customers are also said to have pre-booked capacity on the upcoming 3 and 2 nm nodes, so it doesn't look like demand is going to ease up anytime soon.

TSMC today introduced its N4P process, a performance-focused enhancement of the 5-nanometer technology platform. N4P joins the industry's most advanced and extensive portfolio of leading-edge technology processes. With N5, N4, N3 and the latest addition of N4P, TSMC customers will have multiple and compelling choices for power, performance, area, and cost for its products.

As the third major enhancement of TSMC's 5 nm family, N4P will deliver an 11% performance boost over the original N5 technology and a 6% boost over N4. Compared to N5, N4P will also deliver a 22% improvement in power efficiency as well as a 6% improvement in transistor density. In addition, N4P lowers process complexity and improves wafer cycle time by reducing the number of masks. N4P demonstrates TSMC's pursuit and investment in continuous improvement of our process technologies.