Tenstorrent launched the next generation Blackhole chip family today at their DevDay event in San Francisco. Featuring all new RISC-V cores, Blackhole is built to handle massive AI workloads efficiently and offers an infinitely scalable solution.

Blackhole products are now available for order on tenstorrent.com:

• Blackhole p100, powered by one processor without Ethernet, active-cooled: available for $999
• Blackhole p150, powered by one processor with Ethernet, and available in passive-, active-, and liquid-cooled variants: available for $1,299
• TT-Quiet box, a liquid-cooled desktop workstation powered by 4 Blackhole processors: available for $11,999

At CES 2025, we found the SSD controller that will spur high-end NVMe Gen 5 SSD adoption. Until now, high-end Gen 5 SSDs were driven by Phison's E26 series controller that the company built on TSMC's 12 nm process. The company on Monday launched the new E28 series controller (full name PS5028-E28). This chip is built on the much more advanced TSMC 6 nm process. The new process lets Phison to significantly lower the electrical cost of its NAND flash interface serializer-deserializer, and step up performance closer to the interface limits of PCI-Express 5.0 x4. The controller offers sequential speeds of up to 14.5 GB/s, which is an increase from last year's E26 Max14um variant.

The company showed us the bare E28 controller chip, and a reference-design SSD based on it. Not much to report, except that the drive lacked any cooling solution. Production SSDs powered by the E28 will still need heatsinks to achieve optimal performance, although they won't run as hot as drives powered by the E26. The company didn't have any performance demo stations set up with this drive.

Today, at Lattice Developers Conference 2024, Lattice Semiconductor expanded its edge to cloud FPGA innovation leadership with the launch of exciting new hardware and software solutions. The new Lattice Nexus 2 next-gen small FPGA platform and the first device family based on the platform, Lattice Certus -N2 general purpose FPGAs, offer advanced connectivity, optimized power and performance, and class-leading security. Lattice also announced new mid-range FPGA device capacity options - Lattice Avant 30 and Avant 50 - and new versions of Lattice design software tools and application-specific solution stacks to help accelerate customer time-to-market.

"At Lattice, we are proud to lead technological advancements in low power, small form factor FPGAs, ensuring our customers have the optimal devices, tools, and solutions to design groundbreaking applications that are power efficient, fast, and secure," said Esam Elashmawi, Chief Strategy and Marketing Officer, Lattice Semiconductor. "From the edge to the cloud across a variety of industries, FPGAs stand at the forefront of innovation, and we're committed to delivering versatile and robust small and mid-range FPGA solutions that enable our customers and partners to unlock their full potential."

ASUS over the weekend introduced its third custom-design AMD Radeon RX 7600 graphics card, the RX 7600 DUAL EVO OC. This card is visually the largest, most spruced-up custom-design for this GPU from the company's DUAL series. It's positioned a notch below the premium ROG Strix RX 7600 OC, which remains the only ROG branded graphics card based on the RX 7000 series. The DUAL EVO OC is 22.9 cm in length, and 12.3 cm in height, and is 2.5 slots thick. Its cooling solution features an aluminium fin-stack heatsink, which is ventilated by a pair of 80 mm Axial-Tech fans. The cooler offers idle fan-stop.

Out of the box, the ASUS RX 7600 DUAL EVO OC comes with a 2280 MHz Game clock, and 2695 MHz maximum boost frequency, compared to AMD reference clock speeds of 2250 MHz Game clocks and 2655 MHz boost. The card draws power from a single 8-pin PCIe power connector, and puts out display outputs that include three DisplayPort 1.4a, and one HDMI 2.1. Based on the 6 nm "Navi 33" silicon and driven by the RDNA 3 graphics architecture, the RX 7600 features 2,048 stream processors across 32 CU, along with 64 AI accelerators, and 32 ray accelerators. It comes with 8 GB of 18 Gbps GDDR6 memory across a 128-bit wide memory bus. ASUS didn't reveal pricing.

As Intel's Core Ultra "Arrow Lake-S" desktop processors near their launch, ASUS China put out a video presentation about its Z890 chipset motherboards ready for these processors, which included a technical run-down of Intel's first tile-based desktop processor, which included detailed die-shots of the various tiles. This is stuff that would require not just de-lidding the processor (removing the integrated heat-spreader), but also clearing up the top layers of the die to reveal the various components underneath.

The whole-chip die-shot gives us a bird's eye view of the four key logic tiles—Compute, Graphics, SoC, and I/O, sitting on top of the Foveros base tile. Our article from earlier this week goes into the die areas of the individual tiles, and the base tile. The Compute tile is built on the most advanced foundry node among the four tiles, the 3 nm TSMC N3B. Unlike the older generation "Raptor Lake-S" and "Alder Lake-S," the P-cores and E-core clusters aren't clumped into the two ends of the CPU complex. In "Arrow Lake-S," they follow a staggered layout, with a row of P-cores, followed by a row of E-core clusters, followed by two rows of P-cores, and then another row of E-core clusters, before the final row of P-cores, to achieve the total core-count of 8P+16E. This arrangement reduces concentration of heat when the P-cores are loaded (eg: when gaming), and ensures each E-core cluster is just one ringbus stop away from a P-core, which should improve thread-migration latencies. The central region of the tile has this ringbus, and 36 MB of L3 cache shared among the P-cores and E-core clusters.

As a quick follow-up to last week's "Arrow Lake-S" de-lidding by Madness727, we now have a line-up of a de-lidded Core Ultra 9 285K "Arrow Lake-S" processor placed next to a Core i9-14900K "Raptor Lake-S," and the Core i9-12900K "Alder Lake-S." The tile-based "Arrow Lake-S" is visibly larger than the two, despite being made on more advanced foundry nodes. Both the 8P+16E "Raptor Lake-S" and 8P+8E "Alder Lake-S" chips are built on the Intel 7 node (10 nm Enhanced SuperFin). The "Raptor Lake-S" monolithic chip comes with a die-area of 257 mm². The "Alder Lake-S" is physically smaller, at 215 mm². What sets the two apart isn't just the two additional E-core clusters on "Raptor Lake-S," but also larger caches—2 MB of L2 per P-core, increased form 1.25 MB/core, and 4 MB per E-core cluster, increased from 2 MB/cluster.

Thanks to high quality die-shots of the "Arrow Lake-S" by Madness727, we have our first die-area estimations by A Hollow Knight on Twitter. The LGA1851 fiberglass substrate has the same dimensions as the LGA1700 substrate. This is to ensure the socket retains cooler compatibility. Using geometrical measurements, the base tile of the "Arrow Lake-S" is estimated to be 300.9 mm² in area. The base-tile is a more suitable guideline for "die-area," since Intel uses filler tiles to ensure gaps in the arrangement of logic tiles are filled, and the chip aligns with the base-tile below. The base tile, built on an Intel 22 nm foundry node, serves like a silicon interposer, facilitating high-density microscopic wiring between the various logic tiles stacked on top, and an interface to the fiberglass substrate below.

GPU chip packages of the "Navi 4x" generation of GPUs could be generationally smaller than their predecessors, according to leaked package dimensions of the "Navi 44" chip put out by Olrak29_. With its next-generation Radeon RX gaming GPUs based on the RDNA 4 graphics architecture, AMD has decided to focus on gaining market-share in the performance and mainstream segments, ceding the enthusiast segment to NVIDIA. As part of its effort, the company is making RDNA 4 efficient at every level—architecture, process, and package.

At the architecture level, RDNA 4 is expected to improve performance, particularly the performance cost of ray tracing, through a more specialized ray tracing hardware stack. At the process level, AMD is expected to switch to a more efficient foundry node, with some reports suggesting the TSMC 4 nm, such as the N4P or N4X. For a mid-range GPU like the "Navi 44," which succeeds the "Navi 23" and "Navi 33," these mean a rather big leap from the 7 nm or 6 nm DUV nodes. The leak suggests a smaller package, measuring 29 mm x 29 mm. In comparison, the "Navi 23" package measures 35 mm x 35 mm. The smaller package could make these GPUs friendlier with gaming notebooks, where mainboard PCB real-estate is at a premium.

AMD is readying a new mainstream graphics card positioned based on its current RDNA 3 graphics architecture, the Radeon RX 7650 GRE (Golden Rabbit Edition). The company has had great success in selling graphics card SKUs with the "GRE" brand extension in China, with the RX 6750 GRE being a popular SKU there; and it even has an enthusiast-class SKU with the RX 7900 GRE, which saw a global launch earlier this year. The company is hoping for the "GRE" moniker to compete better against the GeForce RTX 4060, at least in specific markets. A new Benchlife.info report says that the RX 7650 GRE will be based on the 6 nm "Navi 33" monolithic silicon, and not the 5 nm "Navi 32" chiplet-based GPU previously reported.

AMD has already maxed out the "Navi 33" for both the RX 7600 and RX 7600 XT, with the latter only seeing its memory size doubled over the former, so it remains to be seen where AMD goes with the RX 7650 GRE. The "7650" numbering suggests a faster SKU, so it's possible that AMD increases the engine clock speeds of the "Navi 33" by as much as it can. The RX 7600 comes with a 2.25 GHz Game clock, which the RX 7600 XT slightly bumps up to 2.47 GHz. If we were to guess, the RX 7650 GRE could focus on increasing the Game clock, not the memory size; and so it could have the power configuration of the RX 7600 XT, and room for Game clocks either on-par or higher than the RX 7600 XT, while retaining the 8 GB memory size of the RX 7600.

High-resolution die-shots of the AMD "Zen 5" 8-core CCD were released and annotated by Nemez, Fitzchens Fitz, and HighYieldYT. These provide a detailed view of how the silicon and its various components appear, particularly the new "Zen 5" CPU core with its 512-bit FPU. The "Granite Ridge" package looks similar to "Raphael," with up to two 8-core CPU complex dies (CCDs) depending on the processor model, and a centrally located client I/O die (cIOD). This cIOD is carried over from "Raphael," which minimizes product development costs for AMD at least for the uncore portion of the processor. The "Zen 5" CCD is built on the TSMC N4P (4 nm) foundry node.

The "Granite Ridge" package sees the up to two "Zen 5" CCDs snuck up closer to each other than the "Zen 4" CCDs on "Raphael." In the picture above, you can see the pad of the absent CCD behind the solder mask of the fiberglass substrate, close to the present CCD. The CCD contains 8 full-sized "Zen 5" CPU cores, each with 1 MB of L2 cache, and a centrally located 32 MB L3 cache that's shared among all eight cores. The only other components are an SMU (system management unit), and the Infinity Fabric over Package (IFoP) PHYs, which connect the CCD to the cIOD.

Some of the first die-shots and annotations of the Intel Core Ultra 200V "Lunar Lake" processor surfaced on the web, thanks to die-shots by GeenWens and Kurnalsalts on Twitter. Be sure to check out our Lunar Lake Technical Deep-dive article to learn the basics of how Lunar Lake is different from "Meteor Lake." Both are disaggregated chiplet-based processors, but Lunar Lake remodels things a bit. All the logic engines of the processor—the CPU, the iGPU, and the NPU, are located in a centralized Compute tile that's built on the TSMC 3 nm process, while all the I/O controllers are spun out to the Platform Controller tile built on TSMC 6 nm, which sit on a Foveros base tile that acts as an interposer, facilitating high-density microscopic connections between the two tiles. The base tile sits on the fiberglass substrate, which also has stacked LPDDR5X memory for either 16 GB or 32 GB of on-package system memory.

The Kurnalsalts annotation provides a good lay of the land for the Compute tile. The most striking aspect of it is the CPU. "Lunar Lake" comes with a 4P+4E core hybrid CPU, but the two kinds of cores do not share a last-level cache or sit in a ringbus, unlike in case of the Compute tile of "Meteor Lake." The four "Lion Cove" P-cores each come with 2.5 MB of dedicated L2 caches, and share a 12 MB L3 cache. The four "Skymont" E-cores are not part of the ringbus connecting the four P-cores, rather they are physically separated, much like the low-power island E-cores on "Meteor Lake." The E-core cluster shares a 4 MB L2 cache among the four E-cores. This E-core cluster is directly connected to the switching fabric of the Compute tile.

The first reviews of Silicon Motion's new PCIe 5.0 NVMe SSD controller, the SM2508 are starting to appear online, and the good news is that the controller is as power efficient as promised by the company. Tom's hardware has put up their review of a reference design M.2 SSD from Silicon Motion and in their testing, equipped with 1 TB of Kioxia's 162-layer BiCS6 TLC NAND. It easily bests the competition when it comes to power efficiency. In their file copy test, it draws nearly two watts less than its nearest competitor and as much as three watts less than the most power hungry drive. It's still using about one watt more than the best PCIe 4.0 drives, but it goes to show that the production nodes matters, as the SM2508 is produced on a 6 nm node, compared to 12 nm for Phison's E26.

We should point out that the peak power consumption did go over nine watts, but only one of the Phison E26 drives managed to stay below 10 watts here. The most power hungry PCIe 5.0 SSD controller in the test, the InnoGrit IG5666 peaks at nearly 14 watts for comparison. Idle power consumption of the SM2508 is also very good, still drawing more than the PCIe 4.0 drives it was tested against, but far less than any of the other PCIe 5.0 drives. What about performance you ask? The reference drive places itself ahead of all the Phison E26 drives when it comes to sequential file transfers, regardless if it's to or from the drive. Random read IOPS also places right at the top, but it's somewhat behind when it comes to random writes, without being a slow drive by any means. Overall we're looking at a very promising new SSD controller from Silicon Motion with the SM2508 and TPU has also received a sample that is currently undergoing testing, so expect a review here soon.

AMD is rumored to be readying two new entry-level desktop GPU models in the Radeon RX 7000 series. These are the RX 7400 and the RX 7300, which probably succeed the RX 6500 XT and RX 6400, respectively. Perhaps the most interesting aspect of the two are the silicon they're based on. Apparently, AMD is carving the two out from its 6 nm "Navi 33," the same chip it uses for its Radeon RX 7600 and RX 7600 XT SKUs.

The "Navi 33" monolithic silicon is based on the RDNA 3 graphics architecture, and has 16 workgroup processors (WGPs), or 32 compute units (CU), worth 2,048 stream processors, 64 AI accelerators, 32 Ray accelerators, 128 TMUs, and 64 ROPs. The silicon is maxed out in the RX 7600 and RX 7600 XT, and we haven't seen anything to suggest the existence of a desktop RX 7500, which means the RX 7400 and RX 7300 could be heavily cut down from the chip, with AMD reducing not just the CU count, but even the 128-bit GDDR6 memory bus width.

Cixin Technology, a Chinese tech firm, has introduced the Cixin P1 (CP8180), the region's first AI-centric consumer processor. This new chip aims to disrupt domestic markets by capitalizing on the growing AI PC trend, featuring up to 45 TOPS. According to IT Home, Cixin needed 15 months of research and development, 4 months for production, and 3 months of testing for their first CPU.

The Cixin P1 utilizes ARM-based architecture, similar to Qualcomm's successful Snapdragon X Elite CPUs. Built on a 6 nm process, the chip boasts a 12-core ARM CPU configuration, with eight performance cores and four efficiency cores, with a maximum frequency of 3.2 GHz.

AMD is readying a successor to its Ryzen 7045 series "Dragon Range" mobile processor for gaming notebooks and portable workstations. While we don't know its processor model naming yet, the chip is codenamed "Fire Range." We are learning that it will retain the FL1 package as "Dragon Range," which means it will be pin-compatible. This would significantly reduce development costs for notebook OEMs, as they can simply carry over their mainboard designs from their notebooks based on "Dragon Range."

"Fire Range" is essentially a mobile BGA version of the upcoming Ryzen 9000 "Granite Ridge" desktop processor. The FL1 package measures 40 mm x 40 mm in size, and has substrate for two CCDs and a cIOD, just like the desktop chip. "Fire Range" hence features one or two 4 nm "Zen 5" CCDs, depending on the processor model, and the 6 nm client I/O die. Much like "Dragon Range," the "Fire Range" chip will lack support for LPDDR5, and rely on conventional PC DDR5 memory in the SO-DIMM or CAMM2 form-factors. Besides the CPU core count consisting exclusively of full-sized "Zen 5" cores, the main flex for "Fire Range" over "Strix Point" will be its 28-lane PCIe Gen 5 root-complex, which can wire out the fastest discrete mobile GPUs, as well as drive multiple M.2 NVMe slots with Gen 5 wiring, and other high-bandwidth devices, such as Thunderbolt 4, USB4, or Wi-Fi 7 controllers wired directly to the processor.

AMD "Granite Ridge" is codename for the four new Ryzen 9000 series desktop processors the company plans to launch on July 31, 2024. The processor is built in the Socket AM5 package, and is meant to be backwards compatible with AMD 600-series chipset motherboards, besides the new 800-series chipset ones that will launch alongside. "Granite Ridge" is a chiplet-based processor, much like the Ryzen 7000 "Raphael," Ryzen 5000 "Vermeer," and Ryzen 3000 "Matisse." AMD is carrying over the 6 nm client I/O die over from "Raphael" in an effort to minimize development costs, much in the same way it carried over the 12 nm cIOD for "Vermeer" from "Matisse."

The SoC I/O features of "Granite Ridge" are contemporary, with its awesome 28-lane PCI-Express Gen 5 root complex that allows a PCI-Express 5.0 x16, two CPU-attached M.2 Gen 5 slots, and a Gen 5 x4 chipset bus. There's also a basic integrated graphics solution based on the older RDNA 2 graphics architecture; which should make these processors fit for all use-cases that don't need discrete graphics. The iGPU even has multimedia accelerators, an audio coprocessor, a display controller, and USB 3.2 interfaces from the processor.

AMD is about give the new "Zen 5" microarchitecture a near-simultaneous launch across both its client segments—desktop and mobile. The desktop front is held by the Ryzen 9000 "Granite Ridge" Socket AM5 processors; while Ryzen AI 300 "Strix Point" powers the company's crucial effort to capture Microsoft Copilot+ AI PC market share. We recently did a technical deep-dive on the two. HardwareLuxx.de scored two important bits of specs for both processors in its Q&A interaction with AMD—die sizes and transistor counts.

To begin with, "Strix Point" is a monolithic silicon, which is confirmed to be built on the TSMC N4P foundry node (4 nm). This is a slight upgrade over the N4 node that the company built its previous generation "Phoenix" and "Hawk Point" processors on. The "Strix Point" silicon measures 232.5 mm² in area, which is significantly larger than the 178 mm² of "Hawk Point" and "Phoenix." The added die area comes from there being 12 CPU cores instead of 8, and 16 iGPU compute units instead of 12; and a larger NPU. There are many other factors, such as the larger 24 MB CPU L3 cache; and the sizes of the "Zen 5" and "Zen 5c" cores themselves.

Apparently the AMD "Strix Halo" processor is real, and it's large. The chip is designed to square off against the likes of the Apple M3 Pro and M3 Max, in letting ultraportable notebooks have powerful graphics performance. A chiplet-based processor, not unlike the desktop socketed "Raphael," and mobile BGA "Dragon Range," the "Strix Halo" processor consists of one or two CCDs containing CPU cores, wired to a large die, that's technically the cIOD (client I/O die), but containing an oversized iGPU, and an NPU. The point behind "Strix Halo" is to eliminate the need for a performance-segment discrete GPU, and conserve its PCB footprint.

According to leaks by Harukaze5719, a reliable source with AMD leaks, "Strix Halo" comes in a BGA package dubbed FP11, measuring 37.5 mm x 45 mm, which is significantly larger than the 25 mm x 40 mm size of the FP8 BGA package that the regular "Strix Point," "Hawk Point," and "Phoenix" mobile processors are built on. It is larger in area than the 40 mm x 40 mm FL1 BGA package of "Dragon Range" and upcoming "Fire Range" gaming notebook processors. "Strix Halo" features one or two of the same 4 nm "Zen 5" CCDs featured on the "Granite Ridge" desktop and "Fire Range" mobile processors, but connected to a much larger I/O die, as we mentioned.

Intel has reportedly chosen the TSMC 4 nm EUV foundry node for its next generation Arc Xe2 discrete GPUs based on the "Battlemage" graphics architecture. This would mark a generational upgrade from the Arc "Alchemist" family, which Intel built on the TSMC 6 nm DUV process. The TSMC N4 node offers significant increases in transistor densities, performance, and power efficiency over the N6, which is allowing Intel to nearly double the Xe cores on its largest "Battlemage" variant in numerical terms. This, coupled with increased IPC, clock speeds, and other features, should make the "Battlemage" contemporary against today's AMD RDNA 3 and NVIDIA Ada gaming GPUs. Interestingly, TSMC N4 isn't the most advanced foundry node that the Xe2 "Battlemage" is being built on. The iGPU powering Intel's Core Ultra 200V "Lunar Lake" processor is part of its Compute tile, which Intel is building on the more advanced TSMC N3 (3 nm) node.

AMD's upcoming Ryzen 9000 series "Granite Ridge" desktop processors based on the "Zen 5" microarchitecture will see a slight improvement in memory overclocking capabilities. A chiplet-based processor, just like the Ryzen 7000 "Raphael," "Granite Ridge" combines one or two "Zen 5" CCDs, each built on the TSMC 4 nm process, with a client I/O die (cIOD) built on the 6 nm node. The cIOD of "Granite Ridge" appears to be almost identical to that of "Raphael." This is the chiplet that contains the processor's DDR5 memory controllers.

As part of the update, Ryzen 9000 "Granite Ridge" should be able to run DDR5-6400 with a 1:1 ratio between the MCLK and FCLK domains. This is a slight increase from the DDR5-6000 sweetspot speed of Ryzen 7000 "Raphael" processors. AMD is reportedly making it possible for motherboard manufacturers and prebuilt OEMs to enable a 1:2 ratio, making it possible to run high memory speeds such as DDR5-8000, although performance returns with memory speeds would begin to diminish beyond the DDR5-6400 @ 1:1 setting. Memory manufacturers should launch a new wave of DDR5 memory kits with AMD EXPO profiles for DDR5-6400.

ASUS introduced the Radeon RX 6500 XT DUAL OC V2 graphics card. This is the company's second DUAL branded RX 6500 XT product, the original has a similar appearance, and identical dimensions of 201 mm x 128 mm x 40 mm (length x height x thickness). ASUS has done away with the tiny addressable RGB lighting that the original had. While the new card has an aluminium fin-stack heatsink, its design is slightly different from that of the original. It still uses a single 6 mm-thick heatpipe that makes direct contact with the GPU at the base.

The factory overclock is unchanged between the two cards—2820 MHz boost and 2670 MHz Game clock, compared to AMD reference speeds of 2610 MHz boost and 2310 MHz Game clock. The memory speed is unchanged from the reference spec, at 18 Gbps (GDDR6-effective). Based on the 6 nm "Navi 24" silicon, the RX 6500 XT has all 1,024 stream processors present on the chip enabled. This card gets 4 GB of GDDR6 memory across the GPU's 64-bit memory interface. It draws power from a single 6-pin PCIe power connector. Display outputs include one each of DisplayPort 1.4a and HDMI 2.1.

ASRock expanded its entry level graphics card lineup with a new low-profile Radeon RX 6400 graphics card. Such a card had been missing in ASRock's lineup, as its only RX 6400 product had been the full-height RX 6400 Challenger, a product design it shared with the RX 6500 XT Challenger OC. This new RX 6400 Low Profile card isn't just half-height (low-profile), but also single-slot, and relies entirely on the PCIe slot for power.

The card's design involves a simple extruded aluminium heatsink ventilated by a 40 mm fan, with the interesting inclusion of idle fan-stop (something other low-profile cards in this segment tend to lack). The card is 150 mm long, and 68.9 mm tall. Out of the box, it comes with the low-profile bracket installed, but a full height bracket is included in the package. Based on the 6 nm "Navi 24" silicon, the RX 6400 is configured 768 stream processors across 12 compute units, and 4 GB of GDDR6 memory across a 64-bit wide memory interface. The company didn't announce pricing.

TSMC has commenced mass-production of chips for Intel on its 3 nm EUV FinFET foundry node, according to a report by Taiwan industry observer DigiTimes. Intel is using the TSMC 3 nm node for the compute tile of its upcoming Core Ultra 300 "Lunar Lake" processor. The company went into depth about "Lunar Lake" in its Computex 2024 presentation. While a disaggregated chiplet-based processor like "Meteor Lake," the new "Lunar Lake" chip sees the CPU cores, iGPU, NPU, and memory controllers sit on a single chiplet called the compute tile, built on the 3 nm node; while the SoC and I/O components are disaggregated the chip's only other chiplet, the SoC tile, which is built on the TSMC 6 nm node.

Intel hasn't gone into the nuts and bolts of "Arrow Lake," besides mentioning that the processor will feature the same "Lion Cove" P-cores and "Skymont" E-cores as "Lunar Lake," albeit arranged in a more familiar ringbus configuration, where the E-core clusters share L3 cache with the P-cores (something that doesn't happen on "Lunar Lake"). "Arrow Lake" also features a iGPU based on the same Xe2 graphics architecture as "Lunar Lake," and will feature an NPU that meets Microsoft Copilot+ AI PC requirements. What remains a mystery about "Arrow Lake" is the way Intel will go about organizing the various chiplets or tiles. Reports from February 2024 mentioned Intel tapping into TSMC 3 nm for just the disaggregated graphics tile of "Arrow Lake," but we now know from "Lunar Lake" that Intel doesn't shy away from letting TSMC fabricate its CPU cores. The first notebooks powered by "Lunar Lake" are expected to hit shelves within Q3-2024, with "Arrow Lake" following on in Q4.

An alleged company slide by motherboard maker GIGABYTE leaked a few interesting tidbits about the upcoming AMD Ryzen 9000 "Granite Ridge" Socket AM5 desktop processor powered by the "Zen 5" microarchitecture. To begin with, we're getting our first confirmation that the "Zen 5" common CCD used on "Granite Ridge" desktop processors and future EPYC "Turin" server processors, is built on the 4 nm EUV foundry node by TSMC, an upgrade from the 5 nm EUV node that the "Zen 4" CCD is built on. This could be the same version of the TSMC N4 node that AMD had been using for its "Phoenix" and "Hawk Point" mobile processors.

AMD is likely carrying over the client I/O die (cIOD) from the "Raphael" processor. This is built on the TSMC 6 nm DUV node. It packs a basic iGPU based on RDNA 2 with 2 compute units; a dual-channel DDR5 memory controller, and a 28-lane PCIe Gen 5 root complex, besides some SoC connectivity. AMD is rumored to be increasing the native DDR5 speeds for "Granite Ridge," up from the DDR5-5200 JEDEC-standard native speed, and DDR5-6000 "sweetspot" speed of "Raphael," so the cIOD isn't entirely the same.

AMD's future RDNA 5 graphics architecture will bear a "clean sheet" design, and may probably not even have the RDNA branding, says WJM47196, a source of AMD leaks on ChipHell. Two generations ahead of the current RDNA 3 architecture powering the Radeon RX 7000 series discrete GPUs, RDNA 5 could see AMD reimagine the GPU and its key components, much in the same way RDNA did over the former "Vega" architecture, bringing in a significant performance/watt jump, which AMD could build upon with its successful RDNA 2 powered Radeon RX 6000 series.

Performance per Watt is the biggest metric on which a generation of GPUs can be assessed, and analysts believe that RDNA 3 missed the mark with generational gains in performance/watt despite the switch to the advanced 5 nm EUV process from the 7 nm DUV. AMD's decision to disaggregate the GPU, with some of its components being built on the older 6 nm node may have also impacted the performance/watt curve. The leaker also makes a sensational claim that "Navi 31" was originally supposed to feature 192 MB of Infinity Cache, which would have meant 32 MB segments of it per memory cache die (MCD). The company instead went with 16 MB per MCD, or just 96 MB per GPU, which only get reduced as AMD segmented the RX 7900 XT and RX 7900 GRE by disabling one or two MCDs.

Silicon Motion Technology Corporation ("Silicon Motion"), a global leader in designing and marketing NAND flash controllers for solid state storage devices, today introduced its UFS (Universal Flash Storage) 4.0 controller, the SM2756, as the flagship of the industry's broadest merchant portfolio of UFS controller solutions for the growing requirements of AI-powered smartphones as well as other high-performance applications including automotive and edge computing. The company also added a new, second generation SM2753 UFS 3.1 controller to broaden its portfolio of controllers now supporting UFS 4.0 to UFS 2.2 standards. Silicon Motion's UFS portfolio delivers high-performance and low power embedded storage for flagship to mainstream and value mobile and computing devices, supporting the broadest range of NAND flash, including next-generation high speed 3D TLC and QLC NAND.

The new SM2756 UFS 4.0 controller solution is the world's most advanced controller, built on leading 6 nm EUV technology and using MIPI M-PHY low-power architecture, providing the right balance of high performance and power efficiency to enable the all day computing needs of today's premium and AI mobile devices. The SM2756 achieves sequential read performance exceeding 4,300 MB/s and sequential write speeds of over 4,000 MB/s and supports the broadest range of 3D TLC and QLC NAND flash with densities of up to 2 TB.