According to recently discovered shipping manifests, Intel is developing a new processor series codenamed "Wildcat Lake," potentially succeeding their entry-level "Intel Processor" lineup based on Alder Lake-N. The documents, revealed by x86deadandback, suggest a 2025 launch timeline for these chips targeting lightweight laptops and mini-PCs. The shipping records from October 30 mention CPU reball equipment compatible with BGA 1516 sockets, measuring 35 x 25 mm, indicating early validation testing is underway. These processors are expected to be manufactured using Intel's advanced 18A process technology, sharing the same manufacturing node as the upcoming Panther Lake series. Early technical specifications of Wildcat Lake point to a hybrid architecture combining next-generation "Cougar Cove" performance cores with "Darkmont" low-power efficiency (LPE) cores in a 2P+4LPE configuration.

This design appears to separate the core clusters, departing from traditional shared ring bus arrangements, similar to the approach taken in Intel's Lunar Lake and Arrow Lake processors. While Wildcat Lake's exact position in Intel's product stack remains unclear, it could serve as a modernized replacement for the what were Pentium and Celeron processor families. These chips traditionally power devices like Chromebooks, embedded systems, and home servers, with the new series potentially offering significant performance improvements for these market segments. The processor is expected to operate in the sub-double-digit TDP power envelope, positioning it below the more powerful Lunar Lake series. Graphics capabilities will likely be more modest than Lunar Lake's Xe2 architecture, aligning with its entry-level market positioning.

During Barclays 22nd Annual Global Technology Conference, Intel was a guest and two of the interim company co-CEOs Michelle Johnston Holthaus and David Zinsner gave a little update on the state of affairs at Intel. One of the most interesting aspects of the talk was Intel's upcoming "Panther Lake" processor—a direct successor to Intel Core Ultra 200S "Arrow Lake-H" mobile processors. The company confirmed that Panther Lake would utilize an Intel 18A node and that a few select customers have powered on Panther Lake on the E0 engineering sample chip. "Now we are using Intel Foundry for Panther Lake, which is our 2025 product, which will land on 18A. And this is the first time that we're customer zero in a long time on an Intel process," said interim co-CEO Michelle Johnston Holthaus, adding, "But just to give some assurances, on Panther Lake, we have our ES0 samples out with customers. We have eight customers that have powered on, which gives you just kind of an idea that the health of the silicon is good and the health of the Foundry is good."

While we don't know what ES0 means for Intel internally, we can assume that it is one of the first engineering samples on the 18A. The "ES" moniker usually refers to engineering samples, and zero after it could be the first design iteration. For reference, Intel's "Panther Lake-H" will reportedly have up to 18 cores: 6 P-cores, 8 E-cores, and 4 LP cores. The design brings back low-power island E-cores in the SoC tile. The P-cores use "Cougar Cove," which should have a higher IPC than "Lion Cove," while keeping the existing "Skymont" E-cores. The SoC tile may move from Arrow Lake's 6 nm to a newer process to fit the LP cores and an updated NPU. The iGPU is said to use the Xe3 "Celestial" architecture. With Arrow Lake-H launching in early 2025, Panther Lake-H likely won't arrive until 2026.

A few days ago, we published a report about Intel's 18A yields being at an abysmal 10%. This sparked quite a lot of discussion among the tech community, as well as responses from industry analysts and Intel's now ex-CEO Pat Gelsinger. Today, we are diving into known information about Intel's 18A node and checking out what the yields of possible products could be, using tools such as Die Yield Calculator from SemiAnalysis. First, we know that the defect rate of the 18A node is 0.4 defects per cm². This information is from August, and up-to-date defect rates could be much lower, especially since semiconductor nodes tend to evolve even when they are production-ready. To measure yields, manufacturers use various yield models based on the information they have, like the aforementioned 0.4 defect density. Expressed in defects per square centimeter (def/cm²), it measures manufacturing process quality by quantifying the average number of defects present in each unit area of a semiconductor wafer.

Measuring yields is a complex task. Manufacturers design some smaller chips for mobile and some bigger chips for HPC tasks. Thus, these two would have different yields, as bigger chips require more silicon area and are more prone to defects. Smaller mobile chips occupy less silicon area, and defects occurring on the wafer often yield more usable chips than wasted silicon. Stating that a node only yields x% of usable chips is only one side of the story, as the size of the test production chip is not known. For example, NVIDIA's H100 die is measuring at 814 mm²—a size that is pushing modern manufacturing to its limits. The size of a modern photomask, the actual pattern mask used in printing the design of a chip to silicon wafer, is only 858 mm² (26x33 mm). Thus, that is the limit before exceeding the mask and needing a redesign. At that size, nodes are yielding much less usable chips than something like a 100 mm² mobile chip, where defects don't wreak havoc on the yield curve.

Intel's Foundry business is the company's current pain point and probably the reason why the company board of directors forced out ex-CEO Pat Gelsinger. However, the new interim co-CEO, David Zinsner, confirmed that the foundry plan would remain the same. At the UBS technology conference, Zinsner indicated that the company's core strategy remains unchanged and reiterated the forecasts shared in October, highlighting optimism about growth in its PC and server segments. This is a healthy sign that Intel will not lose its foundry subsidiary, which, even though difficult to operate, could be Intel's silver lining with growth opportunities ahead.

Yesterday, we covered the choice of Lip-Bu Tan as Intel's next CEO. However, the new co-CEO, Zinsner, stated, "I'm not in the process, but I'm guessing that the CEO will have some capability around foundry as well as on the product side." A new CEO would be left with a lot of work that, apparently, no one so far can finish. There are speculations that Intel's 18A node is yielding 10% of usable silicon, while Intel's head of foundry business, Naga Chandrasekaran, has noted that 18A node is going through evolution phases to improve final yields and remain profitable, noting that "there's nothing fundamentally challenging on this node now. It is about going through the remaining yield challenges, defect density challenges."

In case you're wondering why Intel went with TSMC 3 nm to build the Compute tile of its "Arrow Lake" processor, and the SoC tile of "Lunar Lake," instead of Intel 3, or even Intel 20A, perhaps there's more to the recent story about Broadcom voicing its disappointment in the Intel 18A foundry node. The September 2024 report didn't specify a number to what yields on the Intel 18A node looked like to spook Broadcom, but we now have some idea as to just how bad things are. Korean publication Chosun, which tracks developments in the electronics and ICT industries, reports that yields on the Intel 18A foundry node stand at an abysmal 10%, making it unfit for mass-production. Broadcom validated Intel 18A as it was prospecting a cutting-edge node for its high-bandwidth network processors.

The report also hints that Intel's in-house foundry nodes going off the rails could be an important event leading up to the company's Board letting go of former CEO Pat Gelsinger, as huge 2nd order effects will be felt across the company's entire product stack in development. For example, company roadmaps put the company's next-generation "Clearwater Forest" server processor, slated for 2025, as being designed for the Intel 18A node. Unless Intel Foundry can pull a miracle, an effort must be underway to redesign the chip for whichever TSMC node is considered cutting-edge in 2025.

When Intel announced the completion of its $7.86 billion CHIPS Act grant from the Biden-Harris administration on Tuesday, we assumed some special terms were tied to the grant. Intel is essentially making a law-abiding promise to the US government that it will not sell its stake in the Intel Foundry unit under any circumstances, even if it manages to become an independent entity. This ensures that Intel is the major voting party in any event. Intel disclosed in a regulatory document that if Intel Foundry becomes its own private entity, Intel must maintain majority control with at least 50.1% ownership to keep its subsidy agreements. Additionally, if Intel Foundry goes public in the future, no single investor would be allowed to acquire more than 35% of shares unless Intel remains the largest shareholder, as this would trigger control-change clauses.

This essentially positions Intel Foundry as too big and too important of a unit to fail, both for Intel and the US government. Given Intel's ties with the US Department of Defense, with up to $3 billion in direct funding under the CHIPS and Science Act for the Secure Enclave program, Intel is vital for providing the US government with advanced semiconductor manufacturing. Strategically, Intel Foundry is the sole US-based company that competes with advanced manufacturing companies such as TSMC and Samsung. Even with TSMC and Samsung driving investments on US soil with advanced fabs, Intel's work with the government requires additional safety and secrecy clearances that only a US firm could provide. In the latest Q3 2024 financial results, Intel Foundry recorded a revenue of $4.4 billion with $5.8 billion in losses. While the operating marking of negative 134.3% seems like a disaster, upcoming quarters will bring it to a positive with more customers and using already developed nodes like 18A.

Apple is reportedly considering diversifying its chip manufacturing strategy with a new silicon manufacturer: Intel. While the upcoming iPhone 17 series, expected next year, will likely feature A19 chips produced by TSMC, a recent rumor from Chinese leaker Fixed Focus Digital hints at a potential switch to Intel for the A20 chipsets powering the 2026 iPhone 18 series. The A18 and A18 Pro chipsets debuted alongside the iPhone 16 series in September 2024, manufactured using TSMC's N3E node. Apple's A19 chips are expected to upgrade to TSMC's N3P node. According to the source, Apple is seeking an Intel 20A node. However, since the A20 node is canceled in favor of 18A, Apple could be an Intel Foundry customer for either 18A or 14A nodes.

Despite the buzz, skepticism persists. Intel has historically struggled with process node transitions and even outsourced production of its Arrow Lake CPUs to TSMC, raising questions about its readiness to deliver on Apple's demands. On the other hand, alternative reports suggest Apple might stick with TSMC's yet-unnamed 2 nm node for the A20, maintaining continuity in its supply chain. As the iPhone 18 series remains two years away, much can change. For now, we are left speculating whether this rumored collaboration with Intel represents a new chapter in Apple's chipset innovation or just a rumor with little substance. If the US government mandates more domestic production, chip designers could be looking at some of the more local manufacturing options, like Intel does on US soil. That could force Apple, NVIDIA, AMD, and Qualcomm to look into Intel's offerings.

Intel has prepared "Jaguar Shores," its "next-next" generation AI and HPC accelerator, successor to its upcoming "Falcon Shores" GPU. Revealed during a technical workshop at the SC2024 conference, the chip was unveiled by Intel's Habana Labs division, albeit unintentionally. This announcement positions Jaguar Shores as the successor to Falcon Shores, which is scheduled to launch next year. While details about Jaguar Shores remain sparse, its designation suggests it could be a general-purpose GPU (GPGPU) aimed at both AI training, inferencing, and HPC tasks. Intel's strategy aligns with its push to incorporate advanced manufacturing nodes, such as the 18A process featuring RibbonFET and backside power delivery, which promise significant efficiency gains, so we can expect to see upcoming AI accelerators incorporating these technologies.

Intel's AI chip lineup has faced numerous challenges, including shifting plans for Falcon Shores, which has transitioned from a CPU-GPU hybrid to a standalone GPU, and cancellation of Ponte Vecchio. Despite financial constraints and job cuts, Intel has maintained its focus on developing cutting-edge AI solutions. "We continuously evaluate our roadmap to ensure it aligns with the evolving needs of our customers. While we don't have any new updates to share, we are committed to providing superior enterprise AI solutions across our CPU and accelerator/GPU portfolio." an Intel spokesperson stated. The announcement of Jaguar Shores shows Intel's determination to remain competitive. However, the company faces steep competition. NVIDIA and AMD continue to set benchmarks with performant designs, while Intel has struggled to capture a significant share of the AI training market. The company's Gaudi lineup ends with third generation, and Gaudi IP will get integrated into Falcon Shores.

According to Taiwanese media Commercial Times, Intel is significantly increasing its outsourcing of "Arrow Lake" CPU production to TSMC, a strategic move as it grapples with persistent issues in its own foundry division. This decision to outsource a substantial portion of Arrow Lake's production is a significant shift in Intel's strategy, showing the company's rising reliance on external partners to meet quality and performance demands. The Arrow Lake Core Ultra 200 series is Intel's first major outsourcing initiative, in which Intel gave its core IP to third-party foundries, more specifically for a 3 nm node at TSMC. However, it clearly indicates the performance gaps in Intel's own Intel Foundry and the high demand expectations for the new CPUs. Originally intended to use Intel 20A node, Intel shifted focus of 18A node for its products and upcoming foundry customers.

Intel's recent orders with TSMC extend to its upcoming Lunar Lake chips and next-generation Falcon Shores AI GPUs, both of which will use TSMC's 3 nm process. Although Intel's 18A node remains promising, the company relies on current products to sustain its revenue streams, making TSMC's support crucial in ensuring timely shipments. This increased outsourcing reflects Intel's need to maintain competitive performance in the short term. Once its Foundry division meets performance and capacity targets, Intel aims to bring more CPU manufacturing back in-house. However, if anything goes wrong, Intel could face challenges securing sufficient volume from TSMC, as the foundry has longstanding commitments with major clients like Apple, NVIDIA, Qualcomm, and AMD.

Intel's recent financial woes have brought the company into severe cost-cutting measures, including job cuts and project delays. However, a silver lining remains—Intel is reportedly in the final stages of securing $8.5 billion in direct funding from the US government under the CHIPS Act, delivered by the end of the year. The potential financing comes at a crucial time for Intel, which has been grappling with financial challenges. The company reported a $1.6 billion loss in the second quarter of 2024, leading to short-term setbacks. However, thanks to sources close to the Financial Times, we learn that Intel's funding target will represent the CHIPS Act's largest share, leading to a massive boost to US-based semiconductor manufacturing.

Looking ahead, the potential CHIPS Act funding could serve as a catalyst for Intel's resurgence, reassuring both investors and customers about the company's future. A key element of Intel's recovery strategy lies in the ramp-up of production for its advanced 18A node, which should become the primary revenue driver for its foundry unit. This advancement, coupled with the anticipated government backing, positions Intel to potentially capture market share from established players like TSMC and Samsung. The company has already secured high-profile customers such as Amazon and (allegedly) Broadcom, hinting at its growing appeal in the foundry space. Moreover, Intel's enhanced domestic manufacturing capabilities align well with potential US government mandates for companies like NVIDIA and Apple to produce processors locally, a consideration driven by escalating geopolitical tensions.

Details have emerged about Intel's upcoming "Panther Lake" processors, set to be the third generation of Core Ultra mobile chips. Called the Core Ultra 300 series, these CPUs are expected to succeed "Lunar Lake". According to recent leaks, Panther Lake-H will be manufactured using Intel's cutting-edge 18A process node. The chips are said to feature a combination of Cougar Cove P-Cores, Skymont E-Cores, and Xe3 (Celestial) integrated graphics. This architecture builds upon Intel's hybrid core design, refining it for even better performance on mobile devices. The leaked information suggests a range of configurations for Panther Lake-H, the high-perfomance variant of the lineup. These include models with varying core counts and power envelopes, from efficient 25 W parts to more interesting 45 W options. Notably, some SKUs reportedly feature up to 18 cores in total, combining P-cores, E-cores, and LP E-cores in a five-tile package. This is an increase from previously believed 16 cores.

Intel has announced the cancellation of its 20A node for Foundry customers, as well as shifting majority of Arrow Lake production to external foundries. The tech giant will instead focus its resources on the more advanced 18A node while relying on external partners for Arrow Lake production, likely tapping TSMC or Samsung for their 2 nm nodes. The decision follows Intel's successful release of the 18A Process Design Kit (PDK) 1.0 in July, which garnered positive feedback from the ecosystem, according to the company. Intel reports that the 18A node is already operational, booting operating systems and yielding well, keeping the company on track for a 2025 launch. This early success has enabled Intel to reallocate engineering resources from 20A to 18A sooner than anticipated. As a result, the "Arrow Lake processor family will be built primarily using external partners and packaged by Intel Foundry".

The 20A node, while now cancelled for Arrow Lake, has played a crucial role in Intel's journey towards 18A. It served as a testbed for new techniques, materials, and transistor architectures essential for advancing Moore's Law. The 20A node successfully integrated both RibbonFET gate-all-around transistor architecture and PowerVia backside power delivery for the first time, providing valuable insights that directly informed the development of 18A. Intel's decision to focus on 18A is also driven by economic factors. With the current 18A defect density already at D0 <0.40, the company sees an opportunity to optimize its engineering investments by transitioning now. However, challenges remain, as evidenced by recent reports of Broadcom's disappointment in the 18A node. Despite these hurdles, Intel remains optimistic about the future of its foundry services and the potential of its advanced manufacturing processes. The coming months will be crucial as the company works to demonstrate the capabilities of its 18A node and secure more partners for its foundry business.

According to a recent Reuters report, Intel's 18A node doesn't seem to be production-ready. As the sources indicate, Broadcom has been reportedly testing Intel's 18A node on its internal company designs, which include an extensive range of products from AI accelerators to networking switches. However, as Broadcom received the initial production run from Intel, the 18A node seems to be in a worse state than initially expected. After testing the wafers and powering them on, Broadcom reportedly concluded that the 18A process is not yet ready for high-volume production. With Broadcom's comments reflecting high-volume production, it signals that the 18A node is not producing a decent yield that would satisfy external customers.

While this is not a good sign of Intel's Fundry contract business development, it shows that the node is presumably in a good state in terms of power/performance. Intel's CEO Pat Gelsinger confirmed that 18A is now at 0.4 d0 defect density, and it is now a "healthy process." However, alternatives exist at TSMC, which proves to be a very challenging competitor to take on, as its N7 and N5 nodes had a defect density of 0.33 during development and 0.1 defect density during high-volume production. This leads to better yields and lower costs for the contracting party, resulting in higher profits. Ultimately, it is up to Intel to improve its production process further to satisfy customers. Gelsinger wants to see Intel Foundry as "manufacturing ready" by the end of the year, and we can see the first designs in 2025 reach volume production. There are still a few more months to improve the node, and we expect to see changes implemented by the end of the year.

Intel today announced that its lead products on Intel 18A, Panther Lake (AI PC client processor) and Clearwater Forest (server processor), are out of the fab and have powered-on and booted operating systems. These milestones were achieved less than two quarters after tape-out, with both products on track to start production in 2025. The company also announced that the first external customer is expected to tape out on Intel 18A in the first half of next year.

"We are pioneering multiple systems foundry technologies for the AI era and delivering a full stack of innovation that's essential to the next generation of products for Intel and our foundry customers. We are encouraged by our progress and are working closely with customers to bring Intel 18A to market in 2025." -Kevin O'Buckley, Intel senior vice president and general manager of Foundry Services

Intel's CEO, Pat Gelsinger, has confirmed that the upcoming 18A process of the Panther Lake CPU generation is on schedule for a mid-2025 release, which aligns with the initial projection. This development marks a significant milestone in the company's ongoing efforts to integrate AI capabilities into its processors. The mid-2025 release date is expected to follow the debut of Intel's Arrow Lake process in late 2024 or early 2025, a release that holds the promise of significant advancements in AI computing. During Intel's Q1 2024 Quarterly Results, Gelsinger expressed confidence in the company's AI capabilities, stating that the Core Ultra platform currently delivers leadership AI performance and that the next-generation platforms, Lunar Lake and Arrow Lake, will launch later this year, tripling AI performance. He also mentioned that the Panther Lake generation, set to release in 2025, will grow AI performance up to an additional 2x.

The Panther Lake generation represents the culmination of three generations of work in a short time and is expected to continue Intel's iterative approach. This transition is marked by a shift from a hybrid architecture, a combination of different types of processors, to a disaggregated die, where different components of the processor are separated, as AI computing becomes increasingly prominent. This strategic move is aimed at optimizing AI performance and flexibility. This marks the third generation of the Intel Core Ultra series, following Ultra 100 (Meteor Lake), Ultra 200 (Arrow Lake), and Lunar Lake (200V). Intel's release strategy mirrors the pattern set by the Hybrid Architecture, with Alder Lake debuting in 2021, followed by Raptor Lake in 2022, and a refreshed Raptor Lake released last year to bridge the gap until LGA 1851 was ready. However, Intel's roadmap has seen adjustments in the past, such as the initial promise of an Arrow Lake release before the end of 2024, which was later retracted. The mid-2025 release of Panther Lake aligns with rumors of Arrow Lake's late 2024 or early 2025 debut, suggesting that the 18A process CPU generation could debut several months after Arrow Lake.

Intel Core Ultra "Lunar Lake-MX" will be the company's bulwark against Apple's M-series Pro and Max chips, designed to power the next crop of performance ultraportables. The MX codename extension denotes MoP (memory-on-package), which sees stacked LPDDR5X memory chips share the package's fiberglass substrate with the chip, to conserve PCB footprint, and give Intel greater control over the right kind of memory speed, timings, and power-management features suited to its microarchitecture. This is essentially what Apple does with its M-series SoCs powering its MacBooks and iPad Pros. Igor's Lab scored the motherlode on the way Intel has restructured the various components across its chiplets, and the various I/O wired to the package.

When compared to "Meteor Lake," the "Lunar Lake" microarchitecture sees a small amount of "re-aggregation" of the various logic-heavy components of the processor. On "Meteor Lake," the CPU cores and the iGPU sat on separate tiles—Compute tile and Graphics tile, respectively, with a large SoC tile sitting between them, and a smaller I/O tile that serves as an extension of the SoC tile. All four tiles sat on top of a Foveros base tile, which is essentially an interposer—a silicon die that facilitates high-density microscopic wiring between the various tiles that are placed on top of it. With "Lunar Lake," there are only two tiles—the Compute tile, and the SoC tile.

Intel and Arm have signed a memorandum of understanding that finalizes the Emerging Business Initiative, their collaboration to support the startup community. The initiative builds on the April 2023 multi-generation agreement to enable chip designers to build low-power compute system-on-chips (SoCs) on the Intel 18A process. Together, the companies will provide essential intellectual property (IP) and manufacturing support, while also making financial assistance available, to foster innovation and growth for startups developing a range of devices and servers built on Arm-based SoCs and manufactured by Intel Foundry. The Emerging Business Initiative was announced last month at Intel Foundry Direct Connect in San Jose, California.

"Intel Foundry and Arm share the belief that for technology to benefit everyone, the building blocks of innovation must be available to anyone. Startups play a crucial role in bringing the great promise of transformations like AI to reality. The Emerging Business Initiative provides a path for new companies to leverage leading-edge Arm-based SoCs and Intel Foundry's global manufacturing capabilities to make their ideas real," said Stuart Pann, Intel senior vice president and general manager of Foundry Services.

The Biden-Harris Administration announced today that Intel and the U.S. Department of Commerce have signed a non-binding preliminary memorandum of terms (PMT) for up to $8.5 billion in direct funding to Intel for commercial semiconductor projects under the CHIPS and Science Act. CHIPS Act funding aims to increase U.S. semiconductor manufacturing and research and development capabilities, especially in leading-edge semiconductors. Intel is the only American company that both designs and manufactures leading-edge logic chips. The proposed funding would help advance Intel's critical semiconductor manufacturing and research and development projects at its sites in Arizona, New Mexico, Ohio and Oregon, where the company develops and produces many of the world's most advanced chips and semiconductor packaging technologies.

"Today is a defining moment for the U.S. and Intel as we work to power the next great chapter of American semiconductor innovation," said Intel CEO Pat Gelsinger. "AI is supercharging the digital revolution and everything digital needs semiconductors. CHIPS Act support will help to ensure that Intel and the U.S. stay at the forefront of the AI era as we build a resilient and sustainable semiconductor supply chain to power our nation's future."

Intel is revamping its foundry play, and the company is set on its goals of becoming a strong contender to rivals such as TSMC and Samsung. Under Pat Gelsinger's lead, Intel recently split (virtually, under the same company) its units into Intel Product and Intel Foundry. During the SPIE 2024 conference for optics and photonics, Anne Kelleher, Intel's senior vice president, revealed that the 14A (1.4 nm) process offers a 15% performance-per-watt improvement over the company's 18A (1.8 nanometers) process. Additionally, the enhanced 14A-E process boasts a further 5% performance boost from the regular A14 node, being a small refresh. Intel's 14A process is set to be the first to utilize High-NA extreme ultraviolet (EUV) equipment, delivering a 20% increase in transistor logic density compared to the 18A node.

The company's aggressive pursuit of next-generation processes poses a significant threat to Samsung Electronics, which currently holds the second position in the foundry market. As part of its IDM 2.0 strategy, Intel hopes to reclaim its position as a leading foundry player and surpass Samsung by 2030. The company's collaboration with American companies, such as Microsoft, further solidifies its ambitions. Intel has already secured a $15 billion chip production contract with Microsoft for its 1.8 nm 18A process. The semiconductor industry is closely monitoring Intel's progress, as the company's advancements in process technology could potentially reshape the competitive landscape. With Samsung planning to mass-produce 2 nm process products next year, the race for dominance in the foundry market is heating up.

Cadence's digital and custom/analog flows are certified on the Intel 18A process technology. Cadence design IP supports this node from Intel Foundry, and the corresponding process design kits (PDKs) are delivered to accelerate the development of a wide variety of low-power consumer, high-performance computing (HPC), AI and mobile computing designs. Customers can now begin using the production-ready Cadence design flows and design IP to achieve design goals and speed up time to market.

"Intel Foundry is very excited to expand our partnership with Cadence to enable key markets for the leading-edge Intel 18A process technology," said Rahul Goyal, Vice President and General Manager, Product and Design Ecosystem, Intel Foundry. "We will leverage Cadence's world-class portfolio of IP, AI design technologies, and advanced packaging solutions to enable high-volume, high-performance, and power-efficient SoCs in Intel Foundry's most advanced process technology. Cadence is an indispensable partner supporting our IDM2.0 strategy and the Intel Foundry ecosystem."

Intel Corp. today launched Intel Foundry as a more sustainable systems foundry business designed for the AI era and announced an expanded process roadmap designed to establish leadership into the latter part of this decade. The company also highlighted customer momentum and support from ecosystem partners - including Synopsys, Cadence, Siemens and Ansys - who outlined their readiness to accelerate Intel Foundry customers' chip designs with tools, design flows and IP portfolios validated for Intel's advanced packaging and Intel 18A process technologies.

The announcements were made at Intel's first foundry event, Intel Foundry Direct Connect, where the company gathered customers, ecosystem companies and leaders from across the industry. Among the participants and speakers were U.S. Secretary of Commerce Gina Raimondo, Arm CEO Rene Haas, Microsoft CEO Satya Nadella, OpenAI CEO Sam Altman and others.

Pat Gelsinger—CEO of Intel Corporation—happily revealed late last month, during an earnings call: "Clearwater Forest, our first Intel 18A part for servers has already gone into fab and Panther Lake for clients will be heading into Fab shortly." The former is positioned as the natural successor to Team Blue's many-times-delayed Xeon "Sierra Forest" (all E-Core) processor family. Intel's second generation E-core Xeon "Clearwater Forest" design is expected to launch in 2025, with a deployment of "Darkmont" efficiency-oriented cores. Official product roadmaps and patch notes have revealed basic "Clearwater Forest" information, but we have not seen many leaks. Bionic_Squash has a history of releasing strictly internal Intel presentation slides—Meteor Lake (MTL-S) desktop SKUs were uncovered last April.

Their latest discovery does not include any photo or documented evidence—Bionic_Squash's concise social media post stated: "Clearwater Forest uses 3D stacking with hybrid bonding." This claim points to the possible deployment of Foveros Direct advanced packaging—this technology was expected to be ready at some point within the second half of 2023, although a mid-December technology showcase implied that things were behind schedule. The fanciest "Clearwater Forest" Xeon processors could arrive with a maximum total of 288 E-core count (and 288 threads)—according to Wccftech analysis: "The CPU package is going to consist of a base tile on top of the interposer which is connected through a high-speed I/O, EMIB, and the cores will be sitting on the topmost layer...Foveros Direct technology will allow direct copper-to-copper bonding, enabling low resistance interconnects and around 10-micron bump pitches. Intel itself states that Foveros Direct will blur the boundary between where the wafer ends and the package begins."

Intel Foundry Services (IFS) and Cadence Design Systems Inc. today announced a multiyear strategic agreement to jointly develop a portfolio of key customized intellectual property (IP), optimized design flows and techniques for Intel 18A process technology featuring RibbonFET gate-all-around transistors and PowerVia backside power delivery. Joint customers of the companies will be able to accelerate system-on-chip (SoC) project schedules on process nodes from Intel 18A and beyond while optimizing for performance, power, area, bandwidth and latency for demanding artificial intelligence, high performance computing and premium mobile applications.

"We're very excited to expand our partnership with Cadence to grow the IP ecosystem for IFS and provide choice for customers," said Stuart Paann, Intel senior vice president and general manager of IFS. "We will leverage Cadence's world-class portfolio of leading IP and advanced design solutions to enable our customers to deliver high-volume, high-performance and power-efficient SoCs on Intel's leading-edge process technologies."

According to a Bloomberg report, Intel is seeking to raise at least $2 billion in equity funding from investors for expanding its fabrication facility in Leixlip, Ireland, known as Fab 34. The chipmaker has hired an advisor to find potential investors interested in providing capital for the project. Fab 34 is currently Intel's only chip plant in Europe that uses cutting-edge extreme ultraviolet (EUV) lithography. It produces processors on the Intel 4 process node, including compute tiles for Meteor Lake client CPUs and expected future Xeon data center chips. While $2 billion alone cannot finance the construction of an entirely new fab today, it can support meaningful expansion or upgrades of existing capacity. Intel likely aims to grow Fab 34's output and/or transition it to more advanced 3 nm-class technologies like Intel 3, Intel 20A, or Intel 18A.

Expanding production aligns with Intel's needs for its own products and its Intel Foundry Services business, providing contract manufacturing. Intel previously secured a $15 billion investment from Brookfield Infrastructure for its Arizona fabs in exchange for a 49% stake, demonstrating the company's willingness to partner to raise capital for manufacturing projects. The Brookfield deal also set a precedent of using outside financing to supplement Intel's own spending budget. It provided $15 billion in effectively free cash flow Intel can redirect to other priorities like new fabs without increasing debt. Intel's latest fundraising efforts for the Ireland site follow a similar equity investment model that leverages outside capital to support its manufacturing expansion plans. Acquiring High-NA EUV machinery for manufacturing is costly, as these machines can reach up to $380 million alone.

ASML has revealed that its cutting-edge High-NA extreme ultraviolet (EUV) chipmaking tools, called High-NA Twinscan EXE, will cost around $380 million each—over twice as much as its existing Low-NA EUV lithography systems that cost about $183 million. The company has taken 10-20 initial orders from the likes of Intel and SK Hynix and plans to manufacture 20 High-NA systems annually by 2028 to meet demand. The High-NA EUV technology represents a major breakthrough, enabling an improved 8 nm imprint resolution compared to 13 nm with current Low-NA EUV tools. This allows chipmakers to produce transistors that are nearly 1.7 times smaller, translating to a threefold increase in transistor density on chips. Attaining this level of precision is critical for manufacturing sub-3 nm chips, an industry goal for 2025-2026. It also eliminates the need for complex double patterning techniques required presently.

However, superior performance comes at a cost - literally and figuratively. The hefty $380 million price tag for each High-NA system introduces financial challenges for chipmakers. Additionally, the larger High-NA tools require completely reconfiguring chip fabrication facilities. Their halved imaging field also necessitates rethinking chip designs. As a result, adoption timelines differ across companies - Intel intends to deploy High-NA EUV at an advanced 1.8 nm (18A) node, while TSMC is taking a more conservative approach, potentially implementing it only in 2030 and not rushing the use of these lithography machines, as the company's nodes are already developing well and on time. Interestingly, the installation process of ASML's High-NA Twinscan EXE 150,000-kilogram system required 250 crates, 250 engineers, and six months to complete. So, production is as equally complex as the installation and operation of this delicate machinery.