Under its new CEO, Lip-Bu Tan, Intel is stepping back from building its glass substrate technology in favor of sourcing ready-made solutions from specialized vendors. Driven by Tan's strategy to concentrate resources on Intel's primary lines, CPU/GPU development, and foundry, Intel's operations are becoming leaner. By outsourcing glass substrates, Intel can significantly reduce development timelines and mitigate the financial risk associated with pioneering novel substrate manufacturing. Crucially, this model grants Intel the freedom to evaluate multiple suppliers, pivot quickly if performance or cost benchmarks change, and integrate advanced packaging more rapidly than if it continued to develop substrates internally. Just as the company is focusing on 14A and 18A-P(T), abandoning in-house glass substrate development is a step in the right direction to reduce costs and achieve profitability.

Meanwhile, the glass‑substrate sector is gathering momentum, particularly among South Korean firms. SK Hynix, in partnership with Applied Materials, has been trialing its Absolics pilot line for some time, while Samsung has recently scaled up its efforts in this niche. JNTC celebrated the opening of its first glass‑substrate plant in May, announcing sixteen prospective clients and projecting revenues to climb from $14.7 million this year to $147 million in 2026, and ultimately hitting $735 million by 2028. A complementary facility under construction in Vietnam will triple the original plant's output, targeting a combined annual production of roughly 500,000 substrates. Intel hasn't yet named which suppliers it will partner with. Still, the company plans to tap into this growing network, potentially joining JNTC's customer roster, to support its advanced packaging roadmap and accelerate product rollouts.

Intel's CEO Lip-Bu Tan is looking at a big change to how the company makes chips for others, Reuters reports citing people who know about it. The new plan might mean Intel stops offering its 18A process technology to other companies. This is different from the strategy of the former CEO, Pat Gelsinger, who had invested heavily in the 18A manufacturing process. Since assuming leadership in March, Tan has been working to reduce costs and find new approaches to revive the struggling chipmaker. By June, he began expressing concerns that the 18A process was failing to attract new customers. Abandoning external sales of 18A technology and focusing on its 14A process would require Intel to take substantial write-offs on the billions invested in its development. Industry analysts suggest these charges could reach hundreds of millions or potentially billions of dollars.

Intel plans to show the board these options later this month. However, a final decision is not expected until this autumn given the complexity and financial stakes involved. Even if they change plans, Intel will still keep its promises about 18A process including producing small amounts of chips for Amazon and Microsoft, and making its own "Panther Lake" laptop processors scheduled for late 2025. Along with standard 18A, Intel is creating two upgraded versions: 18A-P launching in 2026 and 18A-PT arriving in 2028.

Intel's "Nova Lake-S" desktop processors are getting the finishing touches, with a likely arrival scheduled for the second half of 2026. As the successor to "Arrow Lake Refresh," Nova Lake-S introduces a modular design that separates graphics and media functions across distinct tiles. This approach builds on experience from "Meteor Lake," which splits its graphics engine from its media and display units onto separate chiplets. For Nova Lake-S, Intel plans to employ two different GPU architectures: Xe3 "Celestial" for graphics rendering and Xe4 "Druid" for media and display duties, all within a single package. Celestial will manage primary 3D rendering and gaming workloads, while Druid will handle display pipelines and hardware-accelerated video encoding and decoding. By utilizing a more advanced process node, such as TSMC's 2 nm, Intel can optimize media engine performance without increasing costs for the entire GPU subsystem.

On the CPU side, Nova Lake-S is expected to span four primary SKU tiers. The flagship model could feature 52 cores (16 P-cores, 32 E-cores, and four LPE-cores). A 28-core version may target high-end laptops and desktops with eight P-cores, 16 E-cores, and four low-power E-cores. A 16-core variant could serve both the lower-power desktop and laptop segments, featuring four P-cores, eight E-cores, and four low-power E-cores. Finally, an 8-core entry-level part offers four P-cores and four low-power E-cores. Although it remains uncertain whether all SKUs will combine both Xe3 and Xe4 tiles, Intel's tile-based strategy makes it straightforward to mix and match GPU configurations for different market segments. Rumors also suggest that Intel may use its 18A node alongside TSMC's advanced processes for various tile elements. As Panther Lake mobile parts approach the second half of 2025 and Arrow Lake Refresh prepares for its desktop release, Nova Lake-S is the pinnacle of Intel's advanced chip packaging.

Intel says its struggling Foundry division will finally break even in 2027, just as its advanced 14A process comes online. The announcement came during the J.P. Morgan Global Technology, Media & Communications Conference, where CFO David Zinsner outlined the plan to offset years of quarterly losses. Intel has been pouring billions of dollars into new fabs and equipment as it races to keep pace with TSMC and Samsung. Its first milestone is the 18A process, whose first product, codenamed Panther Lake, will arrive in client PCs late in 2025, with volume production following in 2026. Intel also plans to use 18A for its next Xeon "Clearwater Forest" server chips and offer it to a small set of external partners to prove the technology's readiness. "We have to start by using our own chips," Zinsner explained. "Once we show that Panther Lake and Clearwater Forest perform as expected, we'll see more interest from outside customers for 18A, 18A‑P, and then 14A."

He acknowledged that initial adoption is low, but expressed confidence that proven performance will drive committed volume. A key part of the strategy is the use of High‑NA EUV lithography at 14A. Zinsner admitted this will raise equipment costs at first, but he believes the improved transistor density and power efficiency will more than make up for the investment, boosting margins and factory utilization. Intel's path to break even also incorporates revenue from mature nodes such as Intel 16/12, advanced packaging services, and collaborations with UMC and Tower. Under its "smart capital" model, the company will balance internal wafer demand with third‑party work, maintaining flexibility and cost discipline. With a relatively modest external revenue target (for a cash-bleeding foundry), low to mid single‑digit billions per year, Intel Foundry aims to reach break‑even in 2027 and move into sustained profitability soon afterward. By 2027, Intel 14A node and ehnaced the 1.8 nm-class 18A-P(T) node will also complement these break-even efforts.

According to Chosun Biz, Intel Foundry client acquisition efforts for the 18A node have shifted into high gear, with the latest reports indicating that Microsoft has inked a substantial foundry deal based on the 18A process. Talks with Google are also said to be advancing, suggesting that Intel may soon secure a second cloud giant for a customer of its 18A technology. Intel's flagship 18A node, which entered risk production earlier this year, is slated for full-scale volume manufacturing before the end of 2025. Beyond the baseline 18A offering, the company is already developing two enhanced variants: 18A-P, scheduled for rollout in 2026, and 18A-PT, targeted for 2028. Chosun Biz reports that prototype 18A-P wafers have been produced in Intel's domestic fabs, pointing out the foundry's swift pace of new node production.

Intel has even begun sharing early PDKs for its next-generation 14A node with select partners, paving the way for continued scaling beyond the 18A era. Strategically, Intel's extensive US fab footprint, which includes two under-construction fabs in Arizona (a USD 32 billion investment), expanded packaging facilities in New Mexico, a new 300 mm logic plant in Oregon, and two Ohio fabs earmarked for the early 2030s, could prove advantageous amid ongoing tariff uncertainties. Beyond North America, Intel is gearing up Fab 34 in Ireland for mass production of its Intel 4 node and inaugural 3 nm chips later this year. In Israel, Fab 38 is being outfitted for EUV-based, high-performance wafer manufacturing, while an advanced packaging site in Penang, Malaysia, supports global assembly and testing.

During Intel's Foundry Direct Connect symposium in San Jose, where Intel confirmed the ramp of the 18A node at the Arizona fab, the company also announced Intel has achieved a significant advancement in its future node development with the announcement of "turbo cell" technology for its upcoming 14A process. Now slated for production in 2027, this progress supports Intel's objective of introducing five process nodes within a four-year period. The 18A node is presently in risk production and incorporates RibbonFET gate-all-around transistors along with PowerVia, Intel's backside power-delivery architecture. Intel anticipates transitioning 18A to full-volume manufacturing later this year, thereby internalizing greater chiplet assembly work that was previously outsourced for designs such as Lunar Lake.

For the upcoming 14A process, it combines second-generation RibbonFET with PowerDirect, the company's enhanced power network. When implemented using High-NA EUV lithography, Intel projects a performance-per-watt gain of between 15 and 20 percent over the 18A process. Of particular interest is the introduction of turbo cells. These specialized standard-cell libraries enable designers to integrate both high-performance and energy-efficient cells within a single design block. Such flexibility permits precise optimization of chip speed, power consumption, and die area to meet diverse application requirements. In practical terms, turbo cells are expected to elevate peak CPU frequencies and accelerate critical GPU pathways without incurring substantial energy penalties. Intel has already distributed its PDK for the 14A node to prospective customers for feedback, with multiple partners already planning test-chip tape-outs. Complementing these advances, the company will employ advanced packaging technologies, including Foveros 3D stacking and EMIB, and a new high-bandwidth EMIB-T variant to integrate 14A and 18A dies within unified hybrid packages.

Ansys today announced thermal and multiphysics signoff tool certifications for designs manufactured with Intel 18A process technology. These certifications help ensure functionality and reliability of advanced semiconductor systems for the most demanding applications—including AI chips, graphic processing units (GPUs), and high-performance computing (HPC) products. Intel Foundry and Ansys have also enabled a comprehensive multiphysics signoff analysis flow for Intel Foundry's EMIB technology used for creating multi-die 3D integrated circuit (3D-IC) systems.

Recognized as industry-leading solutions, RedHawk-SC and Totem deliver speed, accuracy, and capacity to analyze the power integrity and reliability of Intel 18A RibbonFET Gate-all-around (GAA) transistors with PowerVia backside power delivery. For scalable electromagnetic analysis, Ansys is introducing HFSS-IC Pro, a new addition to the HFSS-IC product family. HFSS-IC Pro is certified for modeling on-chip electromagnetic integrity in radio frequency chips, Wi-Fi, 5G/6G, and other telecommunication applications made with the Intel 18A process node.

At today's Intel Foundry Direct Connect 2025 event, Synopsys, Inc. announced broad EDA and IP collaborations with Intel Foundry, including availability of its certified AI-driven digital and analog design flows for the Intel 18A process node and production-ready EDA flows for the Intel 18A-P process node with RibbonFET Gate-all-around transistor architecture and the industry's first commercial foundry implementation of PowerVia backside power delivery. To drive multi-die design innovation forward, Synopsys and Intel Foundry are collaborating to enable Intel's new Embedded Multi-die Interconnect Bridge-T (EMIB-T) advanced packaging technology with an EDA reference flow powered by Synopsys 3DIC Compiler. With its EDA flows, multi-die solution, and broad portfolio of Synopsys' foundation and interface IP on Intel 18A and Intel 18A-P, Synopsys is helping designers accelerate the development of highly optimized AI and HPC chip designs from silicon to systems.

In a keynote presentation at today's event, John Koeter, Senior Vice President, for the Synopsys IP Group, emphasized: "The successful collaboration between Synopsys and Intel Foundry is advancing the semiconductor industry with silicon to system design solutions to meet the evolving needs for AI and high-performance computing applications. Our production-ready EDA flows, IP, and multi-die solution, provides our mutual customers with comprehensive technologies to accelerate the development of chip designs that meet or exceed their requirements."

Cadence today announced a significant expansion of its portfolio of design IP optimized for Intel 18A and Intel 18A-P technologies and certification of Cadence digital and analog/custom design solutions for the latest Intel 18A process design kit (PDK). These advancements are being showcased today at Intel Foundry Direct Connect, underscoring Cadence's continued leadership in driving industry innovation for artificial intelligence and machine learning (AI/ML), high-performance computing (HPC) and advanced mobility applications through its strategic partnership with Intel Foundry.

Cadence has collaborated closely with Intel Foundry to design and optimize a comprehensive range of solutions that fully leverage the innovative features of the Intel 18A/18A-P nodes, including RibbonFET Gate-all-around transistors and PowerVia backside power delivery network. With this collaboration, joint customers can achieve exceptional power, performance and area (PPA) efficiencies, accelerating time to market for cutting-edge system-on-chip (SoC) designs.

Intel's upcoming "Panther Lake" architecture has just popped up in a perfmon platform update, which now recognizes its core codenames and CPUID via the InstLatX64 lookup table. Tagged "GenuineIntel-6-CC" (Family 6, Model 204), the patch confirms that Panther Lake will combine "Cougar Cove" P-cores with Darkmont E-cores and even hints at a third tier of LPE cores in some configurations. It's the clearest sign yet that Intel is sticking firmly to its hybrid-core strategy. We've also got our first look at the actual SKUs. On the high-performance side (PTL-H), there's a 45 W model with 4 P-cores, 8 E-cores, no LP-E-Cores, and 4 Xe3 graphics cores. Two 25 W models share the same 4 P-cores and 8 E-cores but differ in the rest: one adds 4 LP-E-Cores plus 12 Xe3 cores, while the other pairs 4 LP-E-Cores with just 4 Xe3 cores.

The PTL-U series will offer a 15 W chip with 4 P-cores, 4 LPE-Cores, and 4 Xe3 graphics cores for ultralight devices, dropping the traditional E-cores entirely. Intel plans to move Panther Lake into mass production later this year, lining it up behind the risk production of its cutting-edge 18A process. If things follow the Meteor Lake timeline, we'll likely see most Panther Lake chips hitting shelves in Q1 2026. This isn't Lunar Lake 2.0—Lunar Lake was a niche effort aimed at extreme efficiency with on-package memory. Panther Lake, by contrast, seems built for real-world mobile performance. Most laptops will stick with standard SODIMM or soldered LPDDR memory, though a few OEMs are talking up next-generation LP-CAMM slots for easy RAM upgrades. With a rumored maximum TDP of 64 W, Panther Lake can power everything from budget notebooks and handheld gaming devices to serious gaming laptops and even car infotainment systems.

As revealed during a recent Q1 earnings call, Intel leadership mentioned that "external clients are getting their ASICs designs tested." The company's foundry business is working towards the finalization of its much discussed 18A node process, with alleged trial samples receiving an "impressive performance rating." According to Ctee Taiwan, Team Blue's foundry service has submitted test subjects to the likes of NVIDIA, Broadcom and Faraday Technology. The latter organization has (reportedly) disclosed that the 18A platform tape-out was completed last October—since then, received samples have been "successfully connected." Industry moles believe that NVIDIA and Broadcom are in the middle of conducting manufacturing tests. Additional whispers suggest the delivery of 18A prototypes chez IBM and several other unnamed partner companies. Insiders have indicated impressive/good "verification results." Contrary to reports from other sources, Ctee has picked up on insider chatter about Intel's next-gen Nova Lake compute tile design being "not entirely outsourced." Further conjecture points to Team Blue becoming increasingly confident in its own manufacturing techniques.

Intel just reported its Q1 revenue results, and there are several interesting highlights from the earnings call. Intel Foundry, long touted for a comeback, is generating most of its revenue from a single customer, and it isn't the latest node. Intel's biggest customer is actually itself, predominantly using the "Intel 7" node (Intel's name for its 10 nm SuperFin process), which underpins the Alder Lake and Raptor Lake consumer CPU generations as well as the Sapphire Rapids Xeon server generation. As Intel ramps up 18A-node production and external clients begin testing their ASIC designs, 18A still isn't the Foundry division's primary revenue driver. Instead, demand for Intel 7 wafers is being fueled by massive orders for Intel's 13th- and 14th-generation Raptor Lake processors.

During the Q1 earnings call, Intel CFO Dave Zinsner noted, "Intel Foundry delivered revenue of $4.7 billion, up 8% sequentially on pull-ins of Intel 7 wafers and increased advanced packaging services." He also commented on the Q1 Foundry operating loss of $2.3 billion, attributing it to "startup costs associated with the ramp of products on Intel 18A." While the 18A node is gradually scaling to volume production for upcoming internal and external products, older nodes continue to fuel the revenue stream. Zinsner further confirmed that "we have a lot of important building blocks in place, including the ramp of Intel 18A in the second half of 2025 to support the launch of our first Panther Lake SKU by year-end, with additional SKUs coming in the first half of 2026."

Intel's Vision 2025 conference ended yesterday—since then, media outlets have spent time poring over a multitude of announcements made during the two-day Las Vegas, Nevada event. Notably, Team Blue leadership confirmed that their Core Ultra 300 "Panther Lake" processor series is built to scale (on) 18A, and is on track for production later this year." Prominently-displayed presentation material indicated a roadmapped 2026 launch of "Panther Lake" client chips. The success of this next-gen mobile processor family is intertwined with Intel's Foundry service making marked progress. As summarized by the company's social media account, production teams are celebrating another milestone: "Intel 18A has entered risk production. This final stage is about stress-testing volume manufacturing before scaling up to high volume in the second half of 2025."

Under Pat Gelsinger's command, Team Blue set off on a "five nodes in four years" (5N4Y) adventure around mid-2021. This plan is set to conclude with the finalization of 18A, at some point this year, under a newly refreshed regime—with Lip-Bu Tan recently established as CEO. During an on-stage Intel Vision 2025 session, Kevin O'Buckley—Senior VP of Foundry Services—explained the meaning of: "risk production, while it sounds scary, is actually an industry standard terminology, and the importance of risk production is we've gotten the technology to a point where we're freezing it...Our customers have validated that; 'Yep, 18A is good enough for my product.' And we have to now do the 'risk' part, which is to scale it from making hundreds of units per day to thousands, tens of thousands, and then hundreds of thousands. So risk production..is scaling our manufacturing up and ensuring that we can meet not just the capabilities of the technology, but the capabilities at scale." By original "5N4Y" decree, top brass demanded that process nodes be (fully) available for production, rather than be stuck in a (not quite there) final high volume manufacturing (HVM) phase.

Intel's freshly concluded Vision 2025 "Products Update and GTM" showcase included a segment dedicated to forthcoming Core Ultra 300 "Panther Lake" client processors. Industry watchdogs have grabbed a select few screenshots from Team Blue's broadcast from Las Vegas, Nevada—one backdropped slide confirms that Intel's next-generation mobile CPU series will launch in 2026. This information mirrors the company's Chinese office presenting of an AI PC roadmap—coverage of last month's event highlighted a scheduled first quarter 2026 "volume" arrival of "Core Ultra Next-gen Panther Lake (18A)."

Going back to early March, Intel leadership refuted online rumors of "Panther Lake" mobile CPUs being delayed into 2026, due to alleged problems encountered during the development of the Foundry service's 18A process node. An interviewed executive repeatedly insisted that his firm's brand-new series was on track for release within the second half of 2025. Fast-forward to the end of last week; Lip-Bu Tan expressed a similar outlook in a letter addressed to investors. The newly-established boss stated: "we will further enhance our (leadership) position in the second half of this year with the launch of Panther Lake, our lead product on Intel 18A, followed by Nova Lake in 2026." Industry insiders propose that the Core Ultra 300 series will become available in a very limited capacity come October, via an Early Enablement Program (EEP). Returning to this week—Jim Johnson, senior vice president of the firm's Client Computing Group, informed a watchful audience about the merits of his group's design: "I'm personally excited about Panther Lake because it combines the power efficiency of Lunar Lake, the performance of Arrow Lake, and is built to scale 18A and is on track for production later this year...Our client roadmap is the most innovative we've ever had, and we are far from done."

According to an investment bank UBS note, two industry titans—NVIDIA and Broadcom—are potential future clients that could significantly enhance Intel's Foundry business revenue. To revitalize Intel, newly appointed CEO Lip-Bu Tan reportedly aims to forge strategic alliances with two AI chip manufacturers. Tan, who assumed leadership earlier this month, is determined to rebuild the company's reputation by focusing on customer satisfaction and accelerating the development of its foundry business. UBS analyst Tim Arcuri suggests that while Broadcom might join the client roster, NVIDIA appears to be the more likely candidate. Rather than initially manufacturing NVIDIA's AI GPUs, Intel is expected to begin production with gaming GPUs. NVIDIA could even move to AI GPU production at Intel's fabs if satisfied.

Despite some early optimism, Intel's new CEO is now committed to addressing issues related to power consumption in Intel's manufacturing processes. UBS analyst Tim Arcuri noted that the firm is pushing hard to introduce a lower-power version of its 18A process, the so-called 18AP, which has reportedly struggled to meet energy requirements. Additionally, Intel is working to improve its advanced packaging techniques to rival Taiwan's TSMC CoWoS (S/L/R variants) technology, aiming to overcome packaging constraints that have slowed AI chip production. Analysts speculate that Intel might also become a secondary supplier to tech giant Apple. A promising partnership with Taiwan's United Microelectronics (UMC) could pave the way for Intel's chips to find their way into future Apple products. Whatever materializes, we are yet to see. Switching foundries from TSMC to Intel entirely is not possible for any of the aforementioned fabless designers, so it will likely be dual-sourcing at first, with some non-flagship SKUs getting the full port to Intel 18A.

Intel just started a succession of its Foundry division management. According to an Intel spokesperson for Tom's Hardware, Dr. Ann Kelleher is heading for retirement after spending 30 years at Intel. Dr. Kelleher is the executive vice president of Intel Foundry and has been the head of foundry technology development since 2020. For the past 30 years, Dr. Kelleher has been there for Intel's ups and downs, overcoming many challenges for the company. This year, Dr. Kelleher's impressive 30-year run at Intel is coming to an end as she heads to a well-deserved retirement. While not being active, her immense knowledge and education are still valuable, and she will remain a board advisor.

Succeeding her at the head of the Foundry front-end division will be Naga Chandrasekaran, who brings over three decades of semiconductor experience, 20 of which have been spent at Micron. Assisting Naga Chandrasekaran with back-end foundry operations like packaging will be Navid Shahriari, who spent over 35 years at Intel and is currently a senior vice president. In a statement for Tom's Hardware, Intel noted: "As previously announced, Dr. Ann Kelleher plans to retire later this year following a distinguished career spanning over 30 years with Intel. With a strong foundry leadership team in place and Intel 18A progressing well ahead of our first product launch and external customer tape-outs, this is a well-planned transition as we continue to advance our Foundry priorities in service to customers."

Intel's 18A node, often referred to as Intel's silver lining, has just produced tangible result. In a LinkedIn post of Intel's engineering manager Pankaj Marria, we learn that Intel's 18A node is now being produced in initial wafer lots for testing and evaluation by Intel's customers. This means that Intel's 18A node PDK is officially in version 1.0, and customers are already using that PDK for testing of custom chips. "The Eagle has landed," noted the post, referring to the node development as a major milestone for a node developed and made in US. There were even posters with the same slogans being brought up, meaning that possible customers are also happy with inital test runs. With high-volume manufacturing slated for second half of 2025, we could even see 18A HVM going before initial targets.

Intel's leadership transition to CEO Lip-Bu Tan has overlapped with a recalibration of corporate messaging around the foundry business. Tan's internal communication explicitly frames Intel's strategy as a dual-track approach that maintains both product development and foundry services under unified corporate governance. This position counters speculation regarding potential foundry spinoff scenarios, though it doesn't categorically exclude future structural changes. Previous industry rumors had outlined potential joint venture configurations involving TSMC and major US semiconductor firms, including AMD, Broadcom, and NVIDIA, taking equity positions in a separate foundry entity. While such arrangements remain theoretically viable, Tan's emphasis on fab strategic importance aligns with predecessor Pat Gelsinger's manufacturing-centric vision, suggesting continuity in Intel's Foundry and Product model despite market pressure.

Earlier in the week, online chatter pointed to a possible delay in the production of Panther Lake silicon. Well-known industry analyst—Ming-Chi Kuo—has kept tabs on the inner workings of several big semiconductor players. A previous insider tale revealed NVIDIA's allegedly revised "Blackwell" architecture roadmap. Kuo's latest insight focused on Intel and their 18A node process; rumored setbacks have reportedly pushed the launch of next-gen Panther Lake (PTL) mobile processors into 2026. Team Blue leadership has already reacted to the relatively fresh allegations—earlier in the week, John Pitzer sat down with Morgan Stanley Semiconductor Research's Joe Moore. During their conference fireside chat, Intel's Corporate Vice President of Investor Relations addressed recent internet whispers.

When asked about 18A being developed on schedule, Pitzer responded with: "yes, it is. I mean, I tend to wake up every morning trying to fish through rumors that are coming across on social media about Intel 18A. I want to be very clear. Panther Lake is on track to launch in the second half of this year. That launch date has not changed. We feel really good about the progress that we are making. In fact, if you look at where our yields are on Panther Lake today, they're actually slightly ahead at a similar point in time to Meteor Lake, if you look at the development process for Meteor Lake. I think a couple of weeks ago, there was a technical paper out that actually looked at our SRAM density on Intel 18A that compared well with TSMC's N2. Lots of different metrics you can compare technologies on. I think in general, we think about Intel 18A being an N3 type/N2 sort of comp with the external peers." Panther Lake is set to become the company's first product family that will utilize its own Foundry's 18A node process. Mid-way through February, we heard about the importance of PTL with Intel's portable gaming strategy.

Intel has successfully deployed two advanced ASML High-NA Twinscan EXE:5000 EUV lithography systems at its D1 development facility near Hillsboro, Oregon, processing approximately 30,000 wafers in a single quarter. The High-NA EUV systems, each reportedly valued at $380 million, represent a substantial improvement over previous lithography tools, achieving resolution down to 8 nm with a single exposure compared to the 13.5 nm resolution of current Low-NA systems. Early operational data indicates these machines are approximately twice as reliable as previous EUV generations, addressing reliability challenges that previously hampered Intel's manufacturing progress. The ability to accomplish with a single exposure what previously required three exposures and approximately 40 processing steps has been reduced to just "single digit" processing steps.

Intel has historically been an early adopter of high-NA EUV lithography, a much more aggressive strategy than its competitors like TSMC, which manufactures its advanced silicon using low-NA EUV tools. The company plans to utilize these systems for its upcoming 14A chip manufacturing process, though no specific mass production date has been announced. While ASML classifies these Twinscan EXE:5000 systems as pre-production tools not designed for high-volume manufacturing, Intel's extensive wafer processing is more of a test bed. The early adoption provides Intel with valuable development opportunities across various High-NA EUV manufacturing aspects, including photomask glass, pellicles, and specialized chemicals that could establish future industry standards. Intel's current 18A node is utilizing Low-NA lithography tools, where Intel is only exploring High-NA with it for testing, before moving on to 14A high-volume manufacturing with High-NA EUV.

Intel has updated its 18A node website with the message, "Intel 18A is now ready for customer projects with the tape outs beginning in the first half of 2025: contact us for more information." The contact hyperlink includes an email where future customers can direct their questions to Intel. Designed as a turnaround node for Intel, 18A carries industry-leading features like SRAM density scaling comparable with TSMC's N2, 15% better performance per watt, and 30% better chip density vs. the Intel 3 process node used in Intel Xeon 6, as well as PowerVia backside-power delivery to increase transistor density.

Other features like RibbonFET are the first to replace FinFET transistors, making gate leakage a tighter control. Interestingly, Intel's first products to use the 18A node are client CPUs "Panther Lake" and "Clearwater Forest" Xeon CPUs for data centers. External Intel Foundry customers using the 18A node include Amazon's AWS, Microsoft for its internal silicon for Azure, and Broadcom exploring 18A-based designs. The process of gaining customers for advanced manufacturing is complex, as many existing Samsung/TSMC customers are not risking their capacity and contracts with established advanced silicon makers. However, if Intel's first few customers prove successful, many others could flock over to Intel's fabs as geopolitical tensions are questioning whether the current models of the semiconductor supply chain are feasible in the future. If US companies and startups decide to move with Intel for their chip manufacturing, Intel could experience a complete recovery.

Intel has unveiled some interesting advances in semiconductor manufacturing at the International Solid-State Circuits Conference (ISSCC), showcasing the capabilities of its highly anticipated Intel 18A process technology. The presentation highlighted significant improvements in SRAM bit cell density. The PowerVia system, coupled with RibbonFET (GAA) transistors, is at the heart of Intel's node. The company demonstrated solid progress with their high-performance SRAM cells, achieving a reduction from 0.03 µm² in Intel 3 to 0.023 µm² in Intel 18A. High-density cells showed similar improvement, shrinking to 0.021 µm². These advancements represent scaling factors of 0.77 and 0.88 respectively, which are significant achievements in SRAM technology, once thought to be done with scaling benefits.

Implementing PowerVia technology is an Intel-first approach to addressing voltage drops and interference in processor logic areas. Using an "around the array" scheme, Intel strategically applies PowerVias to I/O, control, and decoder elements while optimizing bit cell design without a frontal power supply. The macro bit density of 38.1 MBit/mm² achieved by Intel 18A puts the company in a strong competitive position. While TSMC reported matching figures with their N2 process, Intel's comprehensive approach with 18A, combining PowerVia and GAA transistors, could challenge Smausng and TSMC, with long-term aspirations to compete for premium clients currently served by TSMC, including giants like NVIDIA, Apple, and AMD.

Thanks to a well-known industry leaker, Jaykihn, Intel's Panther Lake-H processor family, built on the 18A process node, features three distinct configurations, with several power profiles for each case. The flagship model combines four "Cougar Cove" P-cores, eight "Skymont" E-cores, and four LPE cores alongside a 12-core Xe3 "Celestial" GPU. This variant supports LPDDR5X memory exclusively and delivers 180 TOPS of computational power for local AI workloads, operating at 25 W PL1 (base) and 64 W PL2 (turbo) power levels. Secondary configurations include a 4P+8E+4LP+4Xe3 model and a 4P+0E+4LP+4Xe3 variant, both rated at 100 TOPS and supporting both LPDDR5X and DDR5 memory.

The entry-level model operates at 15 W PL1 with 44 W PL2 in baseline mode, scaling to 25 W PL1 and 55 W PL2 in performance mode. All variants feature Thunderbolt 4 connectivity, with high-end models incorporating expanded PCIe 5.0 lane configurations. The integrated Xe3 graphics architecture scales from four to 12 cores across the product stack, with the top SKU eliminating DDR5 compatibility in favor of LPDDR5X optimization. The Panther Lake processor family is slated for launch within the latter half of 2025, and it will be the company's leading 18A product. As a "Lunar Lake" successor, Panther Lake will deliver improved IPC and optimization for new cores in the same device form-factor like laptops, ultrabooks, and handhelds.

So far, this Friday (February 7) has been a bumper day for Intel CPU-related leaks. Golden Pig Upgrade and Jaykihn appear to be in competition with each other—they have uncovered all manner of speculative treasures across desktop and mobile segments. The latest revelation provides an early insight into unannounced feline-themed next-gen CPUs, courtesy of a Jaykihn social media post. Team Blue's Panther Lake processor family is slated for launch within the latter half of 2025—Intel officially stated that it would be their "lead product" on 18A. Older rumors had the "mobile-exclusive" Panther Lake processor family linked to a mixed configuration of new "Cougar Cove" P-cores and updated "Skymont" E-cores. According to today's leak, a variety of core configurations and feature sets are in the pipeline.

Jaykihn has listed three Panther Lake SKUs, and a "more mainstream" lower-end Wildcat Lake model. Common features include support for Thunderbolt 4 connectivity and LPDDR5X memory. Team Blue's rumored highest-end Panther Lake-H (PTL-H) processor appears to max out with a grand total of sixteen cores—consisting of 4 P-cores, 8 E-Cores, and 4 LP cores. The integrated graphics solution is (allegedly) a 12 core Xe3 "Celestial" GPU, with support for LPDDR5X memory—it is the only one on the list to completely jettison DDR5 compatibility. Insiders believe that the total platform (TOPS) rating is 180. As interpreted by VideoCardz, a 12-core "Panther Lake-U" (PTL-U) SKU is reportedly free of efficiency (E) units. The sole Wildcat Lake (WCL) model seems to sport a 2 P-core, 4-LP, and 2-Xe3 configuration.

Intel has officially announced that its "Clearwater Forest" Xeon processor family will be arriving somewhere in the first half of 2026. During a recent earnings call, interim co-CEO—Michelle Johnston Holthaus—discussed Team Blue's product roadmap for 2025 and beyond: "this year is all about improving Intel Xeon's competitive position as we fight harder to close the gap to the competition. The ramp of Granite Rapids has been a good first step. We are also making good progress on Clearwater Forest, our first Intel 18A server product that we plan to launch in the first half of next year." Press outlets have (correctly) pointed out that Intel's "Clearwater Forest" Xeon processors were originally slated for release in 2025, so the company's executive branch has seemingly admitted—in a low-key manner—that their next-gen series is delayed. Industry whispers from last autumn posit that Team Blue foundries were struggling with their proprietary 18A (1.8 nm) node process—at the time, watchdogs predicted a postponement of "Clearwater Forest" server processors.

The original timetable had "Clearwater Forest" server CPUs arriving not long after the launch of Intel's latest line of "Sierra Forest" products—288-core models from the Xeon 6-series. The delay into 2026 could be beneficial—The Register proposes that "Xeons bristling with E-cores" have not found a large enough audience. Holthaus disclosed a similar sentiment (in the Q4 earnings call): "what we've seen is that's more of a niche market, and we haven't seen volume materialize there as fast as we expected." Despite rumors swirling around complications affecting chip manufacturing volumes, Intel's temporary co-leaders believe that things are going well. David Zinsner—Team Blue's CFO—stated: "18A has been an area of good progress...Like any new process, there have been ups and downs along the way, but overall, we are confident that we are delivering a competitive process." His colleague added: "as the first volume customer of Intel 18A, I see the progress that Intel Foundry is making on performance and yield, and I look forward to being in production in the second half, as we demonstrate the benefits of our world-class design."

Intel's freshly uploaded fourth-quarter 2024 "CEO/CFO earnings call comments" document has revealed grand CPU-related plans for 2025 and beyond. One of Team Blue's interim leaders—Michelle Johnston Holthaus—believes that "Nova Lake" processors (a next-generation client family) will arrive in 2026, following a comprehensive rollout of "Panther Lake" CPU products. This official timeline matches previously leaked and rumored development schedules—most notably, in a shipping manifest that was discovered last week. In recent times, industry watchdogs have linked "Nova Lake" to Intel's own 14A node and a TSMC 2 nm process node. Additionally, tipsters pointed to an apparent selection of Coyote Cove performance cores and Arctic Wolf efficiency-oriented cores.

Following yesterday's official announcements, a leaker shared several insights—theorized core configurations and manufacturing details were posted on the Hardware subreddit. Community members were engaged in a debate over Intel's "killing of Falcon Shore," but a plucky contributor—going under the moniker "Exist50"—redirected conversation to all-things "Nova Lake." They believe that Intel has shifted all "compute dies to TSMC" for manufacturing, after a change in plans—initial designs had the "8+16 die" on TSMC's N2P, and the "4+8 die on Intel 18A." Exist50 seemed to have inside track knowledge of product ranges: "Nova Lake (NVL) has a unified HUB/SoC die across mobile and desktop. So yeah, the baseline there is 4+8+4. But there's at least one more die for mobile." The flagship desktop (NVL-S or NVL-SK) chip's configuration could feature as many as sixteen performance cores and thirty-two efficiency cores, due to tile reuse—2x (8P+16E). Exist50 advised Intel CPU enthusiasts to forgo current generation offerings. "Nova Lake" should be: "quite a jump from Arrow Lake (ARL) in terms of MT performance, to say the least. I think anyone who buys ARL will end up regretting it, big time!"