This could in theory mean much lower latency compared to Arrow Lake. Let’s wait to see what (and if) Intel can deliver on desktop with the 18A node.

docnorthThis could in theory mean much lower latency compared to Arrow Lake. Let’s wait to see what (and if) Intel can deliver on desktop with the 18A node.

How so? Assuming that the memory controller lives in the SoC tile, it'd still have the same latency issue as LNL and ARL since those are not monolithic designs anymore.

igormpHow so? Assuming that the memory controller lives in the SoC tile, it'd still have the same latency issue as LNL and ARL since those are not monolithic designs anymore.

Yes, I believe they confirmed that the Memory controller would be moved to the Compute tile in future iterations (currently it's located on the SOC tile which is a key factor to the increased latencies observed on Alder Lake).

alexbwang111Yes, I believe they confirmed that the Memory controller would be moved to the Compute tile in future iterations (currently it's located on the SOC tile which is a key factor to the increased latencies observed on Alder Lake).

Oh, that'd really interesting then, thanks for the clarification!

igormpHow so? Assuming that the memory controller lives in the SoC tile, it'd still have the same latency issue as LNL and ARL since those are not monolithic designs anymore.

on lunar lake, it is already in the compute tile. there is much less tile in LNL than in ARL/Meteor Lake.

ARL has the "old" inneficient long latency design probably because of the last minute move from Intel 2 to TSMC N3, as a stop gap solution.

No reason it is retained in Panther Lake. But we ll see.

Seriously Intel, you couldn't share some interesting details to get excited about?
I surely hope the comparison to Lunar Lake isn't an indicator of this being just another boring mobile platform with tiny bursts of performance.

bgxARL has the "old" inneficient long latency design probably because of the last minute move from Intel 2 to TSMC N3, as a stop gap solution.

Porting a design to a new node is most certainly not a "last minute move", especially a totally different type of node which will require a lot of different implementations. This move was planned out years in advance.

Since apple quit and made its own cpus i feel that somehow company culture is to blame more than lack of innovation.

Look at 15th gen and their own wrong assumptions of their own product.
It did not deliver what all other intel personell believed to be true.

My respect to their interim CEOs but what can they do if they are beeing lied to by their own treams concerning progress.

So let´s wait and see.

Good luck!

efikkanPorting a design to a new node is most certainly not a "last minute move", especially a totally different type of node which will require a lot of different implementations. This move was planned out years in advance.

True, but Imagine the following:
Pat knows intel 20A may not be ready.

Hence he said:
have a plan B ready.

Plan B uses the already designed meteor lake , except 1 tiles redesigned, the CPU tile with TSMC N3.

So they may have been ready with 2 designs, and "last minute" (probably begining of 2024?) commit to the suboptimal N3 route.

That's why ARL design is suboptimal, with the old and ineficient meteor lake design.

bgxTrue, but Imagine the following:
Pat knows intel 20A may not be ready.

Hence he said:
have a plan B ready.

Plan B uses the already designed meteor lake , except 1 tiles redesigned, the CPU tile with TSMC N3.

So they may have been ready with 2 designs, and "last minute" (probably begining of 2024?) commit to the suboptimal N3 route.

That's why ARL design is suboptimal, with the old and ineficient meteor lake design.

After the failures of their 10 nm node they better be designing and taping out their designs for multiple nodes, and considering the resources Intel have at their disposal, the cost of doing this is much lower than the cost of having a single design and failing. So if Intel did do something like this for Arrow Lake, it means they had a plan B all along; and after they got back the engineering samples they made about which design to ramp up to volume production.
(If it were up to me, they should even tape out multiple more ambitous designs too)

There is still a challenge though, wafers are usually reserved years in advance, at least if they want a decent price. So they might have to pay a hefty premium to TSMC if they want a "last minute" scaling of a backup plan, or there might not even be more free capacity available. This is also one of the many advantages of Intel owning their own foundries. And even though they may take a few iterations to get their node right sometimes, they usually make much larger and ambitious improvements and iterate their nodes more than TSMC, and as we saw with the "disastrous" 10 nm, they managed to achieve some impressive performance (especially for large dies) eventually.