Parallels has announced the introduction of x86 emulation support in Parallels Desktop 20.2.0 for Apple Silicon Macs. This new feature enables users to run x86-based virtual machines on their M-series Mac computers, addressing a longstanding limitation since Apple's transition to its custom Arm-based processors. The early technology preview allows users to run Windows 10, Windows 11 (with some restrictions), Windows Server 2019/2022, and various Linux distributions through a proprietary emulation engine. This development particularly benefits developers and users who need to run 32-bit Windows applications or prefer x86-64 Linux virtual machines as an alternative to Apple Rosetta-based solutions.

However, Parallels is transparent about the current limitations of this preview release. Performance is notably slow, with Windows boot times ranging from 2 to 7 minutes, and overall system responsiveness remains low. The emulation only supports 64-bit operating systems, though it can run 32-bit applications. Additionally, USB device support is not available, and users must rely on Apple's hypervisor as the Parallels hypervisor isn't compatible. Despite these constraints, the release is a crucial step forward in bridging the compatibility gap for Apple Silicon Mac users so legacy software can still be used. The feature has been implemented with the option to start virtual machines hidden in the user interface to manage expectations, as it is still imperfect.

Intel at its 2025 International CES keynote unveiled its next-generation mobile processor, codenamed "Panther Lake." Intel confirmed that the chip will be built on its homebrew Intel 18A foundry node. The current "Lunar Lake" and "Arrow Lake" processors see the company leverage TSMC N3 node for the Compute tiles. "Panther Lake" would see the x86-64 core IP return to an Intel node. "Panther Lake" is rumored to combine next-generation "Cougar Cove" P-cores with existing "Skymont" E-cores both in the Compute complex, and in the SoC tile as low-power island E-cores. "Panther Lake" is expected to debut in the second half of 2025.

Nintendo Switch 2 promises to be this year's big (well small) gaming platform launch. It goes up against a growing ecosystem of handhelds based on x86-64 mobile processors running Windows, its main play would have to be offering a similar or better gameplay experience, but with better battery life, given that all of its hardware is purpose-built for a handheld console, and runs a highly optimized software stack; and the SoC forms a big part of this. Nintendo turned to NVIDIA for the job, given its graphics IP leadership, and its ability to integrate it with Arm CPU IP in a semi-custom chip. Someone with access to a Switch 2 prototype, likely an ISV, took the device apart, revealing the chip, a die-shrunk version of the Tegra T239 from 2023.

It's important to note that prototype consoles physically appear nothing like the final product, they're just designed so ISVs and game developers can validate them, and together with PC-based "official" emulation, set up the ability to develop or port games to the new platform. The Switch 2 looks very similar to the original Switch, it is a large tablet-like device, with detachable controllers. The largest chip on the mainboard is the NVIDIA Tegra T239. Nintendo Prime shared more details about the chip.

"Twin Lake" is codename for a line of low-power x86-64 processors by Intel, which succeed the Core i3 N-series and N200 series "Alder Lake-N" processors. These non-socketed (BGA) chips power a wide range of devices from entry level notebooks and mini PCs to consumer NAS servers, and other embedded applications. The chips feature only E-cores. While "Alder Lake-N" used "Gracemont" cores, "Twin Lake" uses the swanky new "Skymont" cores, which serve as E-cores in "Lunar Lake" and "Arrow Lake" hybrid processors. "Skymont" cores feature massive IPC and clock-speed gains over "Gracemont," of nearly 50%, which pulls up their performance levels to match the "Golden Cove" and "Raptor Cove" P-cores of "Alder Lake" and "Raptor Lake," although these cores can't boost up to 5.00 GHz. We got the first name-drop of "Twin Lake" way back in May 2024. Jaykihn leaked what the processor lineup could look like.

The "Twin Lake" silicon features two "Skymont" E-core clusters sharing an L3 cache. At this point, the sizes of the shared L2 caches of the E-core clusters, and the size of the shared L3 cache are not known. On "Alder Lake-N," each "Gracemont" cluster features 2 MB of L2 cache, and the two clusters share a 6 MB L3 cache. The silicon also features an iGPU based on what is very likely the Xe-LPG graphics architecture, with four Xe cores worth 32 execution units (EU). The series is led by the Intel N355. This chip maxes out the "Twin Lake" silicon, enabling both "Skymont" clusters, for an 8-core/8-thread CPU configuration. The CPU comes with a base frequency of 3.00 GHz, and boosts up to 3.90 GHz. The chip comes with a configurable TDP of 9 W and 15 W. It comes with a maxed out iGPU, with all 32 EU being enabled, and a graphics frequency of 1.35 GHz.

Intel has announced it will not proceed with X86S, an experimental instruction set architecture that aims to simplify its processor design by removing legacy support for older 32-bit and 16-bit operating modes. The decision comes after gathering feedback from the technology ecosystem on a draft specification that was released for evaluation. The x86, and its 64-bit x86-64 we use today, is a giant cluster of specifications that contains so many instructions rarely anyone can say with precision how many are there. All of this stems from the era of original 8086 processor, which has its own 16-bit instructions. Later on we transitioned to 32, then 64-bit systems with all have brought their own specific instructions. Adding support for processing of vector, matrix, and other data types has increased the ISA specification so much that no one outside a few select engineers at Intel (and AMD) understands in full. From that x86S idea was born to solve the issue of supporting legacy systems and legacy code, and moving on to the x86S ISA, where "S" stands for simplified.

The X86S proposal included several notable modifications, such as eliminating support for rings 1 and 2 in the processor's protection model, removing 16-bit addressing capabilities, and discontinuing legacy interrupt controller support. These changes would have potentially reduced hardware complexity and modernized the platform's architecture. A key feature of the proposed design was a simplified boot process that would have allowed processors to start directly in 64-bit mode, eliminating the current requirement for systems to boot through various legacy modes before reaching 64-bit operation. The architecture also promised improvements in handling modern features like 5-level paging. "Intel will continue to maintain its longstanding commitment to software compatibility," the company stated in the official document on its website, acknowledging that the x86S dream is over.

The RPCS3 team has announced the successful implementation of arm64 architecture support for their PlayStation 3 emulator. This development enables the popular emulator to run on a broader range of devices, including Apple Silicon machines, Windows-on-Arm, and even some smaller Arm-based SBC systems like the Raspberry Pi 5. The journey to arm64 support began in late 2021, following the release of Apple's M1 processors, with initial efforts focused on Linux platforms. After overcoming numerous technical hurdles, the development team, led by core developer Nekotekina and graphics specialist kd-11, achieved a working implementation by mid-2024. One of the primary challenges involved adapting the emulator's just-in-time (JIT) compiler for arm64 systems.

The team developed a solution using LLVM's intermediate representation (IR) transformer, which allows the emulator to generate code once for x86-64 and then transform it for arm64 platforms. This approach eliminated the need to maintain separate codebases for different architectures. A particular technical challenge emerged from the difference in memory management between x86 and arm64 systems. While the PlayStation 3 and traditional x86 systems use 4 KB memory pages, modern arm64 platforms typically operate with 16 KB pages. Though this larger page size can improve memory performance in native applications, it presented unique challenges for emulating the PS3's graphics systems, particularly when handling smaller textures and buffers. While the emulator now runs on arm64 devices, performance varies significantly depending on the hardware. Simple applications and homebrew software show promising results, but more demanding commercial games may require substantial computational power beyond what current affordable Arm devices can provide.

Intel has released version 1.2 of its X86S architecture specification. The X86S project, first announced last year, aims to modernize the x86 architecture that has been the heart of PCs since the late 1970s. Over the decades, Intel and AMD have continually expanded x86's capabilities, resulting in a complex instruction set that Intel now sees as partially outdated. The latest specification primarily focuses on removing legacy features, particularly 16-bit and 32-bit support. This radical departure from x86's long-standing commitment to backward compatibility aligns with the simplification of x86. While the specification does mention a "32-bit compatibility mode," we are yet to how would 32-bit apps run. This ambiguity raises questions about how X86S might handle existing 32-bit applications, which, despite declining relevance, still play a role in many computing environments.

The potential transition to X86S comes at a time when the industry is already moving away from 32-bit support. However, the proposed changes are subject to controversy. The x86 architecture's strength has long been its extensive legacy support, allowing older software to run on modern hardware. A move to X86S could disrupt this ecosystem, particularly for users relying on older applications. Furthermore, introducing X86S raises questions about the future relationship between Intel and AMD, the two primary x86 CPU designers. While Intel leads the initiative, AMD's role in the potential transition remains uncertain, given its significant contributions to the current x86-64 standard.

Qualcomm has started accepting preorders for its Snapdragon Dev Kit for Windows, based on the Snapdragon X Elite processor. Initially announced in May, the device is now available for preorder through Arrow at a competitive price point of $899. Despite its relatively high cost compared to typical mini PCs, it undercuts most recent laptops equipped with Snapdragon X processors, making it an attractive option for both developers and power users alike. Measuring a mere 199 x 175 x 35 mm, it comes equipped with 32 GB of LPDDR5x RAM, a 512 GB NVMe SSD, and support for the latest Wi-Fi 7 and Bluetooth 5 technologies. The connectivity options are equally robust, featuring three USB4 Type-C ports, two USB 3.2 Type-A ports, an HDMI output, and an Ethernet port.

This mini PC's heart lies the Snapdragon X Elite (X1E-00-1DE) processor. This chip houses 12 Oryon CPU cores capable of reaching speeds up to 3.8 GHz, with a dual-core boost potential of 4.3 GHz. The processor also integrates Adreno graphics, delivering up to 4.6 TFLOPS of performance, and a Hexagon NPU capable of up to 45 TOPS for AI tasks. While similar to its laptop counterpart, the X1E-84-100, this version is optimized for desktop use. It can consume up to 80 watts of power, enabling superior sustained performance without the constraints of battery life or heat dissipation typically associated with mobile devices. This dev kit is made primarily to optimize x86-64 software to run on the Arm platform; hence, removing the power limit is beneficial for translating the code to Windows on Arm. The Snapdragon Dev Kit for Windows ships with a 180 W power adapter and comes pre-installed with Windows 11, making it ready for immediate use upon arrival.

Microsoft Auto Super Resolution (ASR), the standardized game super-resolution based performance enhancement, is initially only being offered to Copilot+ AI PCs powered by Qualcomm Snapdragon X Elite processors, says the Microsoft FAQ for Copilot+ AI PCs. "At initial launch, this feature will be exclusive to Copilot+ PCs equipped with a Qualcomm Snapdragon X Elite processor and a curated set of games that can be found here, a third-party open-source site that Microsoft has contributed compatibility data to," the FAQ answer reads, in response to the question "What is automatic super resolution?"

The way we understand this, Microsoft ASR will be launched initially only Windows Arm devices, specifically those powered by the Snapdragon X Elite SoC. The Snapdragon X Plus is excluded; but more importantly, all x86-64 platforms (Intel or AMD) are excluded from the initial rollout. This doesn't mean that ASR won't make it to x86, it just will at a later date. Copilot+ devices based on the Snapdragon X Elite tend to have a high degree of design collaboration between the OEM and Microsoft, and Redmond wants to use them as tech demonstrators, mostly since these platforms lack the usual super resolution tech such as AMD FSR, Intel XeSS, or NVIDIA DLSS. It's important to note that ASR is a super-resolution tech that's not meant to be confused with DirectSR, the API it's based on. Development of DirectSR for Windows PCs on x86-64 platforms continues.

Qualcomm Snapdragon X Elite is about to make landfall in the ultraportable notebook segment, powering a new wave of Windows 11 devices powered by Arm, capable of running even legacy Windows applications. The Snapdragon X Elite SoC in particular has been designed to rival the Apple M3 chip powering the 2024 MacBook Air, and some of the "entry-level" variants of the 2023 MacBook Pros. These chips threaten the 15 W U-segment and even 28 W P-segment of x86-64 processors from Intel, such as the Core Ultra "Meteor Lake," and Ryzen 8040 "Hawk Point." Erdi Özüağ, prominent tech journalist from Türkiye, has access to a Qualcomm-reference notebook powered by the Snapdragon X Elite X1E80100 28 W SoC. He compared its performance to an off-the-shelf notebook powered by a 28 W Intel Core Ultra 7 155H "Meteor Lake" processor.

There are three tests that highlight the performance of the key components of the SoCs—CPU, iGPU, and NPU. A Microsoft Visual Studio code compile test sees the Snapdragon X Elite with its 12-core Oryon CPU finish the test in 37 seconds; compared to 54 seconds by the Core Ultra 7 155H with its 6P+8E+2LP CPU. In the 3DMark test, the Adreno 750 iGPU posts identical performance numbers to the Arc Graphics Xe-LPG of the 155H. Where the Snapdragon X Elite dominates the Intel chip is AI inferencing. The UL Procyon test sees the 45 TOPS NPU of the Snapdragon X Elite score 1720 points compared to 476 points by the 10 TOPS AI Boost NPU of the Core Ultra. The Intel machine is using OpenVINO, while the Snapdragon is using Qualcomm SNPE SDK for the test. Don't forget to check out the video review by Erdi Özüağ in the source link below.

Qualcomm Snapdragon 8cx Gen 3 is a high performance Arm SoC designed to compete with Apple M3, with Windows 11 thin and light notebooks and Chromebooks being its main target devices. Microsoft pins a lot of hope in chips such as the Snapdragon 8cx series as they offer comparable performance and battery life to the current crop of M3 MacBooks. A lot of water has flown under the bridge since Windows RT, and the latest crop of Windows 11 for Arm has a much wider PC application support base thanks to official translation layers by Microsoft. CPUID has an Arm64 version of the popular CPU-Z utility, which correctly detects all the specs of the Snapdragon 8cx, but more importantly, has a Bench tab that can test the single- and multithreaded performance of the CPU.

A Chinese tech enthusiast wasted no time in putting the Snapdragon 8cx through this CPU-Z internal benchmark, and found surprisingly good performance numbers. The single-threaded bench, which loads one of chip's four Arm Cortex-X1C P-cores, registers a score of 543.7 points. This is roughly comparable to that of the AMD "Zen 2" or Intel "Comet Lake" x86-64 core. The multithreaded test, which saturates all four P-cores, and all four Cortex-A78C E-cores, springs up 3479.7 points, which again compares to entry/mainstream x86-64 processors from AMD or Intel. Not impressed? How about the fact that the Snapdragon 8cx Gen 3 is a 7 W chip that idles under 2 W for the most part, and can make do with passive cooling, posting scores comparable to 35 W x86 chips that need active cooling?

AMD's upcoming family of Ryzen 9000 series of processors on the AM5 platform will carry a new silicon SKU under the hood—Zen 5. The latest revision of AMD's x86-64 microarchitecture will feature a few interesting improvements over its current Zen 4 that it is replacing, targeting the rumored 10-15% IPC improvement. Thanks to the latest set of patches for GNU Compiler Collection (GCC), we have the patch set that proposes changes taking place with "znver5" enablement. One of the most interesting additions to the Zen 5 over the previous Zen 4 is the expansion of the AVX instruction set, mainly new AVX and AVX-512 instructions: AVX-VNNI, MOVDIRI, MOVDIR64B, AVX512VP2INTERSECT, and PREFETCHI.

AVX-VNNI is a 256-bit vector version of the AVX-512 VNNI instruction set that accelerates neural network inferencing workloads. AVX-VNNI delivers the same VNNI instruction set for CPUs that support 256-bit vectors but lack full 512-bit AVX-512 capabilities. AVX-VNNI effectively extends useful VNNI instructions for AI acceleration down to 256-bit vectors, making the technology more efficient. While narrow in scope (no opmasking and extra vector register access compared to AVX-512 VNNI), AVX-VNNI is crucial in spreading VNNI inferencing speedups to real-world CPUs and applications. The new AVX-512 VP2INTERSECT instruction is also making it in Zen 5, as noted above, which has been present only in Intel Tiger Lake processor generation, and is now considered deprecated for Intel SKUs. We don't know the rationale behind this inclusion, but AMD sure had a use case for it.