AMD A10-7850K and A10-7700K APU Specifications Detailed
Specifications of two of AMD's top next-generation APUs, the A10-7850K and A10-7700K, were leaked to the web, revealing an incremental or evolutionary upgrade over the 6000 "Richland" series. To begin with, the two are based on the 28 nm "Kaveri" silicon. Straightaway we find that AMD hasn't been able to catch up with Intel's 22 nm leap for close to two years. All that it manages is to bring the rated TDP of the overclockable "K" chips down to 95W, from the traditional 100W. "Kaveri" puts three of AMD's recent innovations in CPU and GPU on one chip - "Steamroller" CPU micro-architecture, "Graphics CoreNext" GPU architecture, and hUMA (heterogeneous Uniform Memory Access), a technology that allows the CPU and GPU to access the same portion of memory simultaneously.
"Steamroller" features the same component hierarchy and basic design as its predecessors "Piledriver" and "Bulldozer," in which clumps of two cores that feature dedicated and shared number-crunching resources, called modules, make up the basic units of a processor. "Kaveri" features two such modules, and hence features four CPU cores. "Kaveri" misses out on an L3 cache cushioning transfers between the modules, and other uncore components on the APU yet again, and each module features a 2-megabyte L2 cache at its last level, totaling the L2 cache amount to 4 MB on "Kaveri." The integrated memory controller features a 128-bit (dual-channel) DDR3 memory interface, with support for standards as high as DDR3-2133 MHz on some models. The PCI-Express root complex complies with the newer PCIe gen 3.0 standard, as do we imagine the A-Link (chipset bus). AMD introduced huge changes with the GPU component.
"Steamroller" features the same component hierarchy and basic design as its predecessors "Piledriver" and "Bulldozer," in which clumps of two cores that feature dedicated and shared number-crunching resources, called modules, make up the basic units of a processor. "Kaveri" features two such modules, and hence features four CPU cores. "Kaveri" misses out on an L3 cache cushioning transfers between the modules, and other uncore components on the APU yet again, and each module features a 2-megabyte L2 cache at its last level, totaling the L2 cache amount to 4 MB on "Kaveri." The integrated memory controller features a 128-bit (dual-channel) DDR3 memory interface, with support for standards as high as DDR3-2133 MHz on some models. The PCI-Express root complex complies with the newer PCIe gen 3.0 standard, as do we imagine the A-Link (chipset bus). AMD introduced huge changes with the GPU component.