Introspect Technology, a JEDEC member and a leading manufacturer of test and measurement instruments, announced today that it has shipped the M5512 GDDR7 Memory Test System, the world's first commercial solution for testing JEDEC's newly minted JESD239 Graphics Double Data Rate (GDDR7) SGRAM specification. This category-creating solution enables graphics memory engineers, GPU design engineers, product engineers in both memory and GPU spaces, and system integrators to rapidly bring up new GDDR7 memory devices, debug protocol errors, characterize signal integrity, and perform detailed memory read/write functional stress testing without requiring any other tool.

The GDDR7 specification is the latest industry standard that is aimed at the creation of high-bandwidth and high-capacity memory implementations for graphics processing, artificial intelligence (AI), and AI-intensive networking. Featuring pulse-amplitude modulation (PAM) and an improved signal to noise ratio compared to other PAM4 standards used in networking, the GDDR7 PAM3 modulation technology achieves greater power-efficiency while significantly increasing data transmission bandwidth over constrained electrical channels.

JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, is pleased to announce the publication of JESD239 Graphics Double Data Rate (GDDR7) SGRAM. This groundbreaking new memory standard is available for free download from the JEDEC website. JESD239 GDDR7 offers double the bandwidth over GDDR6, reaching up to 192 GB/s per device, and is poised to meet the escalating demand for more memory bandwidth in graphics, gaming, compute, networking and AI applications.

JESD239 GDDR7 is the first JEDEC standard DRAM to use the Pulse Amplitude Modulation (PAM) interface for high frequency operations. Its PAM3 interface improves the signal to noise ratio (SNR) for high frequency operation while enhancing energy efficiency. By using 3 levels (+1, 0, -1) to transmit 3 bits over 2-cycles versus the traditional NRZ (non-return-to-zero) interface transmitting 2 bits over 2-cycles, PAM3 offers higher data transmission rate per cycle resulting in improved performance.

Samsung isn't the only Korean memory giant showing off its latest tech at the upcoming IEEE Solid State Circuit Conference (SSCC) in February, 2024; it will be joined by SK Hynix, which will demo competing tech across both its volatile and non-volatile memory lines. To begin with, SK Hynix will be the second company to show off a GDDR7 memory chip, after Samsung. The SK Hynix chip is capable of 35.4 Gbps speeds, which is lower than the 37 Gbps Samsung is showing off, but at the same 16 Gbit density. This density allows the deployment of 16 GB of video memory across a 256-bit memory bus. Not all next-generation GPUs will max out 37 Gbps, some may run at lower memory speeds, and they have suitable options in the SK Hynix product stack. Much like Samsung, SK Hynix is implementing PAM3 I/O signaling, and a proprietary low-power architecture (though the company wouldn't elaborate on whether it's similar to the four low-speed clock states as the Samsung chips).

GDDR7 is bound to dominate the next generation of graphics cards across the gaming and pro-vis segments; however the AI HPC processor market will continue to bank heavily on HBM3E. SK Hynix has innovated here, and will show off a new 16-high 48 GB (384 Gbit) HBM3E stack design that's capable of 1280 GB/s over a single stack. A processor with even four such stacks will have 192 GB of memory at 5.12 TB/s of bandwidth. The stack implements a new all-around power TSV (through silicon via) design, and a 6-phase RDQS (read data queue strobe) scheme, for TSV area optimization. Lastly, the SK Hynix sessions will also include the first demo of its ambitious LPDDR5T (LPDDR5 Turbo) memory standard aimed at smartphones, tablets, and thin-and-light notebooks. This chip achieves a data-rate of 10.5 Gb/s per pin, and a DRAM voltage of 1.05 V. Such high data speeds are possible thanks to a proprietary parasitic capacitance reduction technology, and a voltage offset calibrated receiver tech.

Samsung Electronics will demonstrate its next generation GDDR7 memory chips at the IEEE Solid State Circuit Conference (SSCC), to be held in San Francisco in February. The company had teased GDDR7 way back at its Tech Day in 2022. The GDDR7 memory standard is targeted squarely at graphics cards and game consoles, it offers a 2x bandwidth gain over the current GDDR6. Samsung is expected to showcase a GDDR7 chip that's capable of 37 Gbps data-rate, with 16 Gbit (2 GB) density.

The GDDR7 memory standard leverages PAM3 signaling to achieve these high data-rates. The current GDDR6 standard uses NRZ signaling, while its off-shoot GDDR6X co-developed by NVIDIA and Micron Technology relies on PAM4 signaling. The standard also features four read clock modes, which should help with power management when the device is idling. Both NVIDIA and AMD are expected to implement GDDR7 with their next-generation GPUs. GDDR7 enters mass-production this year, and will feature in NVIDIA's GeForce RTX 50-series "Blackwell" graphics cards, as well as AMD Radeon RX 8000 series RDNA4.

Samsung Electronics, a world leader in advanced semiconductor technology, today announced that it has completed development of the industry's first Graphics Double Data Rate 7 (GDDR7) DRAM. It will first be installed in next-generation systems of key customers for verification this year, driving future growth of the graphics market and further consolidating Samsung's technological leadership in the field.

Following Samsung's development of the industry's first 24 Gbps GDDR6 DRAM in 2022, the company's 16-gigabit (Gb) GDDR7 offering will deliver the industry's highest speed yet. Innovations in integrated circuit (IC) design and packaging provide added stability despite high-speed operations. "Our GDDR7 DRAM will help elevate user experiences in areas that require outstanding graphics performance, such as workstations, PCs and game consoles, and is expected to expand into future applications such as AI, high-performance computing (HPC) and automotive vehicles," said Yongcheol Bae, Executive Vice President of Memory Product Planning Team at Samsung Electronics. "The next-generation graphics DRAM will be brought to market in line with industry demand and we plan on continuing our leadership in the space."

Last week Micron Technology CEO, Sanjay Mehrotra, announced during an investors meeting that the company's next generation GPU memory—GDDR7—will be arriving next year: "In graphics, industry analysts continue to expect graphics' TAM compound annual growth rate (CAGR) to outpace the broader market, supported by applications across client and data center. We expect customer inventories to normalize in calendar Q3. We plan to introduce our next-generation G7 product on our industry-leading 1ß node in the first half of calendar year 2024." His proposed launch window seems to align with information gleaned from previous reports—with NVIDIA and AMD lined up to fit GDDR7 SGRAM onto their next-gen mainstream GPUs, although Team Green could be delaying their Ada Lovelace successor into 2025.

Micron already counts these big players as key clients for its current GDDR6 and GDDR6X video memory offerings, but Samsung could be vying for some of that action with its own GDDR7 technology (as announced late last year). Presentation material indicated that Samsung is anticipating data transfer rates in the range of 36 Gbps, with usage of PAM3 signalling. Cadence has also confirmed similar numbers for its (industry first) GDDR7 verification solution, but the different encoding standard will require revising of memory controllers and physical interfaces.

Cadence, a leading developer of tools for system design and verification, has announced the industry's first GDDR7 verification solution. This in-depth software solution affords IC designers the ability to simulate and verify their GDDR7 silicon designs before printing a single chip. The challenges of designing GDDR7 stem from a rather massive leap in operating speed and advanced features, with GDDR7 targeting speeds of 36,000 MT/s and utilizing more advanced signaling methods.

The next-generation GDDR7 memory standard is shaping up nicely, to double bandwidth and density over the current GDDR6. In a company presentation detailing upcoming memory technologies, Samsung revealed that GDDR7 uses PAM3 signalling. While ones and zeroes are stored in DRAM memory cells, it is transmitted between devices (such as the DRAM chip and the GPU) in electrical waveforms known as "signals." Ones and zeroes are interpreted by patterns in the signal waveform.

Conventional GDDR6 memory uses NRZ (non-return to zero) or PAM2 signalling to achieve data-rates starting from 14 Gbps, with 24 Gbps expected to be the fastest production GDDR6 memory speed on offer, however some of the faster GDDR6 speeds such as 18 Gbps, 20 Gbps, and 22 Gbps couldn't hit production soon enough for the development phase of the GeForce RTX 30-series "Ampere" GPU, and so NVIDIA and Micron Technology co-developed the GDDR6X standard leveraging PAM4 signalling, to offer speeds ranging between 18 Gbps to 23 Gbps (or higher) several quarters ahead of this faster JEDEC-standard GDDR6.

USB Implementers Forum (USB-IF), the support organization for the advancement and adoption of USB technology, today announced the publication of the USB4 Version 2.0 specification, a major update to enable USB 80 Gbps performance over the USB Type-C cable and connector. The updated USB4 specification doubles the maximum aggregate bandwidth of USB to the benefit of higher-performance displays, storage, and USB-based hubs and docks. The USB Type-C and USB Power Delivery (USB PD) specifications have also been updated to support this higher level of data performance.

"For engineers, USB4 is defined by its multi-protocol tunneling that architecturally differentiates it from its predecessors - USB 3.2 and USB 2.0," said Brad Saunders, USB-IF Board Chair and CEO. "This updated technical specification extends USB4 speed and data protocol performance, enabling manufacturers to develop products that can deliver USB 80 Gbps in addition to existing USB 40 Gbps and USB 20 Gbps to end users."

It was only yesterday that the USB Promoters Group announced the USB4 Version 2.0 spec with support for speeds of up to 80 Gbps, something TechPowerUp mentioned at the end of our USB4 article back in June. Now details of a 120 Gbps asymmetric mode has popped up, courtesy of Angstronomics and we've managed to confirm that it is indeed something that is coming from one of our own sources. We were in fact told back in June that the 80 Gbps mode was meant to be asymmetric, but this was not mentioned in the recent press release.

The 120 Gbps mode will use three of the four data pairs for upstream data and the fourth 40 Gbps data pair will be for downstream data from and to the host controller.Asymmetric data transfers are nothing new over USB Type-C cables, as the DP Alt Mode is already taking advantage of this. This is possible because USB4 Version 2.0 will move to PAM3 (Pulse-Amplitude Modulation) data encoding from today's 64/66- or 128/132-bit encoding. The next generation of Thunderbolt is also expected to use PAM3 encoding to reach the rumoured 80 Gbps speeds that were posted somewhat by mistake by an Intel executive last year.