Cadence, a leading developer of tools for system design and verification, has announced the industry's first GDDR7 verification solution. This in-depth software solution affords IC designers the ability to simulate and verify their GDDR7 silicon designs before printing a single chip. The challenges of designing GDDR7 stem from a rather massive leap in operating speed and advanced features, with GDDR7 targeting speeds of 36,000 MT/s and utilizing more advanced signaling methods.New Features Added in GDDR7

Clock

DRAM uses a single Write Clock (WCK) for command-address and data latching, while it generates and internal divide-by-4 clock named CK4 that is used as a reference for latencies.

Read clock in GDDR7 has some extra flexibility and can be configured in four different modes from the mode register:

• Always running - Always runs and only stops during sleep modes
• Disable - Stopped
• Start with RCK Start command - Read clock can start when issuing the RCK Start command prior to reading data. It can then be stopped by using the RCK STOP command, and the host can start or stop as required
• Start with Read - Read clock starts automatically when the DRAM receives any command which involves reading data out. It can also be stopped via the RCK STOP command.

The last two modes contribute to power efficiency within the GDDR7 spec by only enabling RCK when it is needed.

Command Driving

With GDDR6 only a single command can be issued at any given time. Conversely GDDR7 commands can be issued in parallel using different bits of the Command/Address (CA) bus. The provided example states Bank X can be refreshed via Refresh command on CA[2:0], while Bank Y can be read by issuing a read command on CA[4:3] at the same time.

PAM3 Signaling

GDDR7 uses PAM3 signal encoding in high-speed operation for data, Cyclical Redundancy Check (CRC), ERR feedback, and the read clock. In PAM3 mode, 256-bits of data are encoded and transferred over 8 Write Clock cycles. PAM3 provides a significant improvement to energy efficiency, SNR, and eye density (the gaps that exist between intersecting wave forms which translate to individual bits).

LFSR Mode of Data Training

Data training enables the host the ability to find the appropriate voltage values and timings required to transfer data reliably over a high-speed link. In First-In-First-Out (FIFO) mode the host writes data to FIFO then reads back custom patterns. For continuous training GDDR7 utilizes a new Linear-Feedback Shift Register (LFSR) mode in which random training data is generated using pseudo-random bit streams. LFSR also offers lane masking and eye masking, and it has error counters for each lane which keep track of errors in write training.

Cadence GDDR7 VIP supports all modes and new features as defined in the JEDEC GDDR7 specification including a smart way to simulate the three levels of PAM3 by a real number representation.

To allow the data UI simulation, Cadence VIP provides three solutions through binary bus, strength modeling or real number modeling.

Cadence GDDR7 VIP can be integrated into various environments such as Verilog, plain system Verilog, SV-UVM, and systemC. It has a complete set of protocol checkers and re-configurable timers to check behavior compliance with the protocol. It supports various modes of error injection in multiple fields of transactions during array data transfer and interface training as well. It is also integrated with the waveform debugger solution to visualize transactions on the waveform viewers for faster debugging and overall verification.

With the first-to-market availability of the Cadence GDDR7 VIP, early adopters can start working with the latest specification immediately, ensuring compliance with the standard and achieving the fastest path to IP and SoC verification closure. More information about Cadence's Verification IP solution can be found on the Cadence VIP website.