IBM Research has unveiled a significant advancement in optical interconnect technology for advanced data center communications. The breakthrough centers on a novel co-packaged optics (CPO) system featuring a sophisticated Polymer Optical Waveguide (PWG) design, marking a potential shift from traditional copper-based interconnects. The innovation introduces a Photonic Integrated Circuit (PIC) measuring 8x10mm, mounted on a 17x17mm substrate, capable of converting electrical signals to optical ones and vice versa. The system's waveguide, spanning 12 mm in width, efficiently channels light waves through precisely engineered pathways, with channels converging from 250 to 50 micrometers.

While current copper-based solutions like NVIDIA's NVLink offer impressive 1.8 TB/s bandwidth rates, and Intel's Optical Compute Interconnect achieves 4 TBit/s bidirectional throughput, IBM's technology focuses on scalability and efficiency. The company plans to implement 12 carrier waves initially, with the potential to accommodate up to 32 waves by reducing spacing to 18 micrometers. Furthermore, the design allows for vertical stacking of up to four PWGs, potentially enabling 128 transmission channels. The technology has undergone rigorous JEDEC-standard testing, including 1,000 cycles of thermal stress between -40°C and 125°C, and extended exposure to extreme conditions including 85% humidity at 85°C. The components have also proven reliable during thousand-hour storage tests at various temperature extremes. The bandwidth of the CPO is currently unknown, but we expect it to surpass current solutions.

Samsung Electronics and SK hynix are working together to standardize "Low Power Double Data Rate 6 (LPDDR6) - Processing in Memory (PIM)" technology according to a report from Business Korea. This collaboration seeks to accelerate the development of low power memory products. The cooperation is still in its early stage, the companies initial work is focused on registering the standard with the Joint Electron and Device Engineering Council (JEDEC). Discussions are underway to determine technical requirements, specific characteristics of LPDDR with PIM, such as "internal bandwidth"—the data transfer rate within the memory, unlike the "external bandwidth" between the processor and memory in traditional systems. According to a Samsung Electronics representative, the two companies are in the process of developing a timeline for standardization.

This partnership is notable given how Samsung and SK hynix compete in the high-bandwidth memory (HBM) market. SK hynix beat Samsung in profits reporting 7.3 trillion won in the third quarter, while Samsung made 3.86 trillion won. However, the rise of AI with its increased demand for more memory has shaken up the scene pushing for teamwork instead of wasting resources in developing completely different and unstandardized products. Both firms see PIM technology as a way to grow, previous attempts to independently develop PIM products include Samsung's HBM and LPDDR5-PIM and SK hynix's GDDR6-PIM.

JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, today announced the publication of JESD230G: NAND Flash Interface Interoperability Standard. JESD230G introduces speeds of up to 4800 MT/s, as compared to 400 MT/s in the first version of JESD230 published in 2011. Also, JESD230G adds a separate Command/Address Bus Protocol (SCA), delivering enhanced throughput and efficiency by allowing hosts and NAND devices to take maximum advantage of the latest interface speeds. JESD230G is available for free download from the JEDEC website.

"JEDEC is excited to release JESD230G," said David Landsman, Distinguished Engineer at Western Digital and Chair of the JEDEC NAND TG. He added, "This version of JESD230 further advances the capabilities of NAND flash devices to meet the growing demands of their expanding range of applications and continues the JEDEC tradition of building interoperable ecosystems through open industry standards."

GeIL - Golden Emperor International Ltd. - one of the world's leading PC components and peripheral manufacturers, announced today that its full range of DDR5 memory products, from 6400 MT/s to 8000 MT/s, will now be available in both CUDIMM and UDIMM options to meet diverse consumer needs. For high-end overclocking applications, GeIL is introducing two new high-speed specifications, 8800 MT/s and 9200 MT/s, offering overclocking enthusiasts an optimal choice for top performance. Both CUDIMM and UDIMM options ensure excellent compatibility and full support for Intel's latest Core Ultra Processors (Series 2).

According to the latest JEDEC standards, CUDIMM includes an additional CKD (Clock Driver) chip, which regenerates the clock signal directly on the DIMM. This integration reduces signal degradation and noise, resulting in enhanced memory stability and performance, with stable operation at speeds of 6400 MT/s and even reaching up to 7200 MT/s. For both standard and high-performance applications, the CKD chip plays a crucial role in signal integrity and reliability, enabling faster, more stable speeds.

JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced the publication of PS-007A LPDDR5 CAMM2 Connector Performance Standard. The connector, referred to as "LP5CAMM2," is designed to offer a standardized modular LPDDR5 solution with ecosystem support, unlike the traditional LPDDR5 memory-down approach. Developed by JEDEC's JC-11 Committee for Mechanical Standardization, PS-007A is available for free download from the JEDEC website.

As compared to a DDR5 SODIMM connector, benefits of the LP5CAMM2 connector include:

• Better signal integrity (SI) and improved radio frequency interference (RFI)
• To enable a module solution with lower power consumption and increased battery life
• 50% form factor reduction with the similar Z height

KIOXIA America, Inc. today announced that it has begun mass production of the industry's first Universal Flash Storage (UFS) Ver. 4.0 embedded flash memory devices with 4-bit-per-cell, quadruple-level cell (QLC) technology.

QLC UFS offers a higher bit density than traditional TLC UFS, making it suitable for mobile applications that require higher storage capacities. Advancements in controller technology and error correction have enabled QLC technology to achieve this while maintaining competitive performance. KIOXIA's new 512 gigabyte (GB) QLC UFS achieves sequential read speeds of up to 4,200 megabytes per second (MB/s) and sequential write speeds of up to 3,200 MB/s, taking full advantage of the UFS 4.0 interface speed.

Kingston Technology Company, Inc., a world leader in memory products, announced the upcoming release of Kingston FURY Renegade DDR5 CUDIMMs, compatible with Intel's new 800-series chipset (formerly codenamed Arrow Lake). Intel's 800-series chipset is the first platform to utilize Clock Drivers on CUDIMMs (Clocked Unbuffered Dual Inline Memory Modules). At 6400 MT/s DDR5, JEDEC mandates the inclusion of a Client Clock Driver (CKD) on UDIMMs and SODIMMs. This component buffers and redrives the clock signal from the processor, enhancing signal integrity to the module. To distinguish these advanced modules from standard DDR5 UDIMMs and SODIMMs, JEDEC has designated them as CUDIMMs and CSODIMMs, respectively.

Kingston FURY Renegade RGB and non-RGB CUDIMM modules start at an overclocked speed of 8400 MT/s and are available as 24 GB single modules and 48 GB dual channel kits. Since CUDIMMs and UDIMMs share the same 288-pin connector, Kingston FURY UDIMMs with XMP and EXPO profiles are also compatible with Intel 800-series motherboards. However, it's recommended to verify compatibility through the motherboard manufacturer's QVL (Qualified Vendor List) or by checking the Kingston Configurator for supported speeds and capacities.

KLEVV, the leading consumer memory and storage brand introduced by Essencore, today announces its first-ever CU-DIMM & CSO-DIMM memory modules, which work seamlessly with the latest Intel Core Ultra (Series 2) "Arrow Lake-S" Processors/ Z890 platform to unleash the true DDR5 performance. KLEVV's next-generation DDR5 memory lineup receives a substantial performance boost with the integration of advanced Client Clock Driver (CKD) technology. Incorporated via a small integrated circuit (IC) directly on the DIMM, CKD IC enhances the module's speed and efficiency for both desktop and laptop applications. By regenerating the memory chips' clock signal, it improves stability, supports higher operating frequencies, and minimizes electrical interference and signal degradation—pushing the boundaries of memory performance.

Designed for both performance desktop and laptop systems, KLEVV's new Standard CU-DIMM and CSO-DIMM memory modules combine the brand's renowned quality with cutting-edge DDR5 technology, making them ideal for both casual and professional users. Leveraging the innovative CKD architecture, these modules deliver exceptional stability and reliability, even at high speeds, effectively mitigating electrical interference that could otherwise hinder performance. With this advanced design, users can count on smooth, efficient operation, even under heavy workloads.

JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced upcoming raw card designs currently in development in JEDEC's JC-45 Committee for DRAM Modules in collaboration with the JC-40 and JC-42 Committees. These raw card memory device standards are intended for use in client computing applications such as laptops and desktops and will be supported by related appendix specifications. The forthcoming raw cards will also complement two DDR5 Clock Driver standards published earlier this year: JESD323: DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Common Specification and JESD324: DDR5 Clocked Small Outline Dual Inline Memory Module (CSODIMM) Common Specification.

Integrating a Clock Driver (CKD) into a DDR5 DIMM provides numerous advantages, particularly in memory stability and performance, and enhances signal integrity and reliability at high speeds. By regenerating the clock signal locally on the DIMM, a CKD ensures stable operation even at elevated clock speeds. With a DDR5 CKD, DIMM data rates can be increased from 6400 Mbps to 7200 Mbps in the initial version of the standard, and targeting up to 9200 Mbps in future versions.

As a global leader in memory solutions, Team Group Inc. today unveiled its latest T-Force CKD (Client Clock Driver) DDR5 Gaming Memory. Following the worldwide attention received for the 7200 MHz T-CREATE EXPERT Ai CKD DDR5 showcased at COMPUTEX 2024, the T-Force gaming brand takes performance to new heights with the upcoming T-Force XTREEM CKD DDR5 8200 to 9000 (Gear 2) 2x24GB, featuring overclocking capabilities reaching up to 9600 MHz (Gear 4). Consumers can now push the limits of CUDIMM overclocking on the Intel Z890 platform with next-generation CKD DDR5 overclocking memory, achieving unprecedented performance breakthroughs.

Team Group continues to lead the industry in pushing boundaries by crafting the T-Force XTREEM CKD DDR5, which breaks beyond JEDEC frequency specifications. Utilizing CKD components and Intel XMP profiles on the Intel Z890 motherboard, users can effortlessly overclock to DDR5 speeds beyond 9000 MHz with a single click. Unlike JEDEC-compliant memory modules, the T-Force XTREEM CKD DDR5 leverages CKD components to enhance and buffer high-frequency signals from the CPU, ensuring more stable signal transmission to the memory modules. This enables DDR5 to push overclocking performance to even higher frequencies, surpassing traditional U-DIMM overclocking limitations.

Intel's Arrow Lake-S launch line-up has been confirmed courtesy of serial leaker @9550pro on X/Twitter and although the leaked Intel product slide doesn't contain any real surprises by now, it does confirm that Intel will launch five different SKUs later this month. The Core 200S-series should be unveiled on Thursday by Intel, but retail availability isn't expected until the 24th of October. The Initial five CPU SKUs will be the Core Ultra 9 285K, the Core Ultra 7 265K and 265KF and finally the Core Ultra 5 245K and 245KF. As noted earlier today in the performance leak of the Core Ultra 9 285K, the entire Arrow Lake-S series will lack Hyper-Threading in favour of more E-cores. The Core Ultra 9 285K features eight Lion Cove P-cores and 16 Skymont E-cores, followed by the Core Ultra 7 265 SKUs which retain the Lion Cove core count, but ends up with only 12 Skymont cores. Finally, the Core Ultra 5 SKUs have six Lion Cove P-cores and eight Skymont E-cores. All the upcoming SKUs feature Intel's Thermal Velocity Boost, a feature that used to be exclusive to the Core i9 tier of CPUs in the past, but only the Core Ultra 9 and Ultra 7 SKUs support Intel Turbo Boost Max Technology 3.0. The Core Ultra 9 and Ultra 7 SKUs have a maximum TDP of 250 W, with the Core Ultra 5 SKUs peaking at 159 W. All five processors have a base power of 125 W.

As such, we're looking at boost speeds of up to 5.7 GHz for the Core Ultra 9, 5.5 GHz for the Core Ultra 7 and 5.2 GHz for the Core Ultra 5 processors. The Core Ultra 5 has the highest base frequency of the three SKUs with the P-cores clocking in at 4.2 GHz and the E-cores at 3.6 GHz. The Core Ultra 7 follows at 3.9 GHz for the P-Cores and 3.3 GHz for the E-cores and finally the Core Ultra 9 has a base frequency of 3.7 GHz for the P-Cores and 3.2 GHz for the E-cores. Intel has upped the JEDEC memory support to DDR5-6400, which is an 800 MHz jump in the officially supported memory speed from its 14th Gen Core i processors. Up to 192 GB of RAM is supported, which is the same as the previous generation of desktop CPUs from Intel. The IGP sports four Xe-cores across the board of the K SKU CPUs, with a base clock of 300 MHz and a boost clock of up to 2 GHz, although the Core Ultra 5 SKUs end up with an IGP that only boosts to 1.9 GHz. All SKUs also feature a third generation NPU capable of 13 TOPS, which is a lot weaker than the mobile Core Ultra 200V Lunar Lake CPUs which have an NPU capable of up to 48 TOPS, depending on the SKU. As this leak appears to be from the same original source as the performance figures that leaked earlier, we'd assume the information is correct, especially as it lines up with earlier leaks, but it should still be taken with a pinch of salt until everything has been confirmed by Intel.

JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced the publication of two new standards supporting Compute Express Link (CXL ) technology. These additions complete a comprehensive family of four standards that provide the industry with unparalleled flexibility to develop a wide range of CXL memory products. All four standards are available for free download from the JEDEC website.

JESD319: JEDEC Memory Controller Standard - for Compute Express Link (CXL ) defines the overall specifications, interface parameters, signaling protocols, and features for a CXL Memory Controller ASIC. Key aspects include pinout reference information and a functional description that includes CXL interface, memory controller, memory RAS, metadata, clocking, reset, performance, and controller configuration requirements. JESD319 focuses on the CXL 3.1 based direct attached memory expansion application, providing a baseline of standardized functionality while allowing for additional innovations and customizations.

Intel's upcoming Core Ultra 200 "Arrow Lake-S" desktop processors will herald a new wave of overclocking memory kits as the architecture is expected to support even higher memory speeds than the current 14th Gen Core. The product page of an ASRock Z890 motherboard lists out maximum memory speeds for various DIMM configurations. The most overclocker-friendly config—1 single-rank DIMM per channel—sees ASRock mention support for DDR5-9200+ (OC). The fastest DDR5 OC memory kits in the market are DDR5-8600, and over the Summer, JEDEC announced standardization of high frequency DDR5 configurations, including the likes of DDR5-8800. Such high frequencies require the DIMM to feature a clock driver.

Those looking for high capacity memory configurations have big reason to cheer. For two single-rank DIMMs per channel, or one dual-rank DIMM per channel, the motherboard's product page mentions an OC speed of DDR5-6800+. This should be a boon for those wanting large memory capacities such as 96 GB or 128 GB using dual-rank DIMMs at reasonably high speeds. Even the densest memory configuration, two dual-rank DIMMs per channel, has a maximum OC speed of DDR5-5800+. This should allow users to approach the platform's maximum memory capacity, such as 256 GB using four 64 GB dual-rank DIMMs, or 192 GB using four 48 GB DIMMs, but at much higher speeds that what the current platforms are capable of.

Rambus Inc., a premier chip and silicon IP provider making data faster and safer, today announced the industry's first HBM4 Memory Controller IP, extending its market leadership in HBM IP with broad ecosystem support. This new solution supports the advanced feature set of HBM4 devices, and will enable designers to address the demanding memory bandwidth requirements of next-generation AI accelerators and graphics processing units (GPUs).

"With Large Language Models (LLMs) now exceeding a trillion parameters and continuing to grow, overcoming bottlenecks in memory bandwidth and capacity is mission-critical to meeting the real-time performance requirements of AI training and inference," said Neeraj Paliwal, SVP and general manager of Silicon IP, at Rambus. "As the leading silicon IP provider for AI 2.0, we are bringing the industry's first HBM4 Controller IP solution to the market to help our customers unlock breakthrough performance in their state-of-the-art processors and accelerators."

JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced the publication of the JESD406-5 LPDDR5/5X Serial Presence Detect (SPD) Contents V1.0, consistent with the updated contents of JESD401-5B DDR5 DIMM Label and JESD318 DDR5/LPDDR5 Compression Attached Memory Module (CAMM2) Common Standard.

JESD406-5 documents the contents of the SPD non-volatile configuration device included on all JEDEC standard memory modules using LPDDR5/5X SDRAMs, including the CAMM2 standard designs outlined in JESD318. The JESD401-5B standard defines the content of standard memory module labels using the other two standards, assisting end users in selecting compatible modules for their applications.

MSI is excited to announce the launch of the latest AMD Ryzen 9000 Series processors, set to debut on the AM5 platform. Powered by advanced 4 nm CPU process technology, the Ryzen 9000 Series promises to revolutionize the computing landscape with unmatched performance, efficiency, and versatility for gamers and content creators. At launch, August 8th, AMD Ryzen 7 9700X, and Ryzen 5 9600X are available while the Ryzen 9 9950X and 9900X will launch on August 15th. These processors will feature up to 16 cores and 32 threads, with a theoretical maximum boost clock speed of 5.7 GHz, 64 MB of L3 cache, and a maximum TDP of 170 W.

AMD Ryzen 9000 Series will also support PCIe 5.0 for the GPU and M.2 while enhancing DDR5 memory speed. Notably, the AMD Ryzen 7 9700X offers approximately 12% better overall performance than the first-gen AMD 3D V-cache CPU. All these processors are compatible with the AM5 socket, and existing AMD 600 Series motherboards and Ryzen 9000 Series processors can seamlessly integrate by updating to the latest BIOS, available on MSI's product support page.

JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, proudly announces upcoming standards for advanced memory modules designed to power the next generation of high-performance computing and AI applications. JEDEC today revealed key details about its upcoming standards for DDR5 Multiplexed Rank Dual Inline Memory Modules (MRDIMM) and a next-generation Compression-Attached Memory Module (CAMM) for LPDDR6. The new MRDIMM and CAMM for LPDDR6 are set to revolutionize the industry with unparalleled bandwidth and memory capacity.

The JEDEC MRDIMM standard is set to deliver up to twice the peak bandwidth of native DRAM, enabling applications to surpass current data rates and achieve new levels of performance. It maintains the same capacity, reliability, availability, serviceability (RAS) features as JEDEC RDIMM. The committee aims to double the bandwidth to 12.8 Gbps and increase the pin speed. MRDIMM is envisioned to support more than two ranks and is being designed to utilize standard DDR5 DIMM components ensuring compatibility with conventional RDIMM systems.

JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, today announced it is nearing completion of the next version of its highly anticipated High Bandwidth Memory (HBM) DRAM standard: HBM4. Designed as an evolutionary step beyond the currently published HBM3 standard, HBM4 aims to further enhance data processing rates while maintaining essential features such as higher bandwidth, lower power consumption, and increased capacity per die and/or stack. These advancements are vital for applications that require efficient handling of large datasets and complex calculations, including generative artificial intelligence (AI), high-performance computing, high-end graphics cards, and servers.

HBM4 is set to introduce a doubled channel count per stack compared to HBM3, with a larger physical footprint. To support device compatibility, the standard ensures that a single controller can work with both HBM3 and HBM4 if needed. Different configurations will require various interposers to accommodate the differing footprints. HBM4 will specify 24 Gb and 32 Gb layers, with options for supporting 4-high, 8-high, 12-high and 16-high TSV stacks. The committee has initial agreement on speeds bins up to 6.4 Gbps with discussion ongoing for higher frequencies.

JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced the publication of JESD405-1B JEDEC Memory Module Label - for Compute Express Link (CXL ) V1.1. JESD405-1B joins JESD317A JEDEC Memory Module Reference Base Standard - for Compute Express Link (CXL ) V1.0, first introduced in March 2023, in defining the function and configuration of memory modules that support CXL specifications, as well as the standardized content for labels for these modules. JESD405-1B and JESD317A were developed in coordination with the Compute Express Link standards organization. Both standards are available for free download from the JEDEC website.

JESD317A provides detailed guidelines for CXL memory modules including mechanical, electrical, pinout, power and thermal, and environmental guidelines for emerging CXL Memory Modules (CMMs). These modules conform to SNIA (Storage Networking Industry Association) EDSFF form factors E1.S and E3.S to provide end-user friendly hot pluggable assemblies for data centers and similar server applications.

The race is on for memory manufacturers to bring the next generation GDDR7 graphics memory into mass production. While rivals Samsung and Micron are aiming to have GDDR7 chips available in Q4 of 2024, South Korean semiconductor giant SK Hynix revealed at Computex 2024 that it won't kick off mass production until the first quarter of 2025. GDDR7 is the upcoming JEDEC standard for high-performance graphics memory, succeeding the current GDDR6 and GDDR6X specifications. The new tech promises significantly increased bandwidth and capacities to feed the appetites of next-wave GPUs and AI accelerators. At its Computex booth, SK Hynix showed off engineering samples of its forthcoming GDDR7 chips, with plans for both 16 Gb and 24 Gb densities.

The company is targeting blazing-fast 40 Gbps data transfer rates with its GDDR7 offerings, outpacing the 32 Gbps rates its competitors are starting with on 16 Gb parts. If realized, higher speeds could give SK Hynix an edge, at least initially. While trailing a quarter or two behind Micron and Samsung isn't ideal, SK Hynix claims having working samples now validates its design and allows partners to begin testing and qualification. Mass production timing for standardized memories also doesn't necessarily indicate a company is "late" - it simply means another vendor secured an earlier production window with a specific customer. The GDDR7 transition is critical for SK Hynix and others, given the insatiable demand for high-bandwidth memory to power AI, graphics, and other data-intensive workloads. Hitting its stated Q1 2025 mass production target could ensure SK Hynix doesn't fall too far behind in the high-stakes GDDR7 race, with faster and higher-density chips to potentially follow shortly after volume ramp.

KLEVV by Essencore had a formidable lineup of high-end gaming PC memory and SSDs at Computex 2024. We were greeted at the booth with an Essencore-branded LPCAMM2 module with 32 GB density, and LPDDR5-8533 speeds on tap. The Genuine G560 (it's named Genuine) is a modern M.2 NVMe Gen 5 SSD with a fanless heatsink. It comes in capacities of 1 TB, 2 TB, and 4 TB; with sequential speeds ranging between 13 GB/s to 14 GB/s reads, and 9.5 GB/s to 12 GB/s writes; and depending on the capacity, the endurance is between 700 TBW to 3000 TBW. The CRAS C930 is a premium M.2 Gen 4 SSD, with 1 TB and 2 TB models available, sequential read speeds of up to 7.4 GB/s, and sequential write speeds between 6.4 GB/s to 6.8 GB/s. Endurance ranges between 750 TBW for the 1 TB model, and 1500 TBW for the 2 TB.

At the value end of KLEVV's SSD lineup is the CRAS C925, which offers mostly similar performance numbers to the C930, but with slightly different endurance ratings. It ranges between 500 GB and 2 TB; with the same 7.4 GB/s maximum read speeds, but slightly lower maximum write speeds of 6.2 GB/s for the 500 GB model, 6.3 GB/s for the 1 TB, and 6.5 GB/s for the 2 TB model; and endurance rated at 600 TBW, 1200 TBW, and 2400 TBW, respectively.

On June 4th, COMPUTEX 2024 was successfully held at the Taipei Nangang Exhibition Center. Mnemonic Electronic Co., Ltd., the Taiwanese subsidiary of Longsys, showcased industry-leading high-capacity SSDs under the theme "Embracing the Era of High-Capacity SSDs." The products on display included the Mnemonic MS90 8TB SATA SSD, FORESEE ORCA 4836 series enterprise NVMe SSDs, FORESEE XP2300 PCIe Gen 4 SSDs, and rich product lines comprising embedded storage, memory modules, memory cards, and more. The company offers reliable industrial-grade, automotive-grade, and enterprise-grade storage products, providing high-capacity solutions for global users.

High-Capacity SSDs
For SSDs, Mnemonic Electronic presented products in various form factors and interfaces, including PCIe M.2, PCIe BGA, SATA M.2, and SATA 2.5-inch. The Mnemonic MS90 8 TB SATA SSD supports the SATA interface with a speed of up to 6 Gb/s (Gen 3) and is backward compatible with Gen 1 and Gen 2. It also supports various SATA low-power states (Partial/Sleep/Device Sleep) and can be used for nearline HDD replacement, surveillance, and high-speed rail systems.

ADATA Technology, the world's leading brand for memory modules and flash memory, will team up with its gaming brand XPG and industrial-grade embedded storage brand ADATA Industrial for Computex Taipei 2024 from June 4 to June 7. ADATA's theme for 2024 is "Innovate Today, Embrace Tomorrow." At the show, ADATA will present products in three major categories tied to their vision and commitment to leading innovation and sustainable initiatives. These categories include "AI Computing," "Sustainability and Innovation," and "Immersive Reality."

ADATA and XPG brand ambassador Mera will make a surprise appearance in the "AI Computing" section. ADATA will showcase the world's first AI gaming laptop equipped with an SSD of up to 24 TB and 96 GB of DRAM, overclocked DDR5 8000 R-DIMM for handling massive computing workloads and data processing, and a complete line of Express Card storage solutions that promote AI mobile devices. ADATA will also display various high performance products that continue to lead sustainability trends in the "Sustainability and Innovation" section including the industry's only comprehensive innovative cooling solutions, and a full range of green storage products made of recycled materials. Other highlights will include the 2024 iF Design Award winning INVADER X family of gaming chassis, and gaming components that combine optimized heat dissipation, environmental awareness, and the application of future technologies. The "Immersive Reality" section features a new gaming handheld PC, the XPG NIA, a full range of gaming products and peripherals, and the industry's most powerful external SSD solutions and mobile peripherals. In order to make it easier for consumers around the world to participate in the exhibition, ADATA will simultaneously launch its online COMPUTEX event from June 4, allowing consumers to experience ADATA's full range of industry-leading products.

Yesterday we reported on DDR6 memory hitting new heights of performance and it looks like LPDDR6 will follow suit, at least based on details in a JEDEC presentation. LPDDR6 will just like LPDDR5 be available as solder down memory, but it will also be available in a new LPCAMM2 module. The bus speed of LPDDR5 on LPCAMM2 modules is expected to peak at 9.2 GT/s based on JEDEC specifications, but LPDDR6 will extend this to 14.4 GT/s or roughly a 50 percent increase. However, today the fastest and only LPCAMM2 modules on the retail market which are using LPDDR5X, comes in at 7.5 GT/s, which suggests that launch speeds of LPDDR6 will end up being quite far from the peak speeds.

There will be some other interesting changes to LPDDR6 CAMM2 modules as there will be a move from 128-bit per module to 192-bit per module and each channel will go from 32-bits to 48-bits. Part of the reason for this is that LPDDR6 is moving to a 24-bit channel width, consisting of two 12-bit sub channels, as mentioned in yesterday's news post. This might seem odd at first, but in reality is fairly simple, LPDDR6 will have native ECC (Error Correction Code) or EDC (Error Detection Code) support, but it's currently not entirely clear how this will be implemented on a system level. JEDEC is also looking at developing a screwless solution for the CAMM2 and LPCAMM2 memory modules, but at the moment there's no clear solution in sight. We might also get to see LPDDR6 via LPCAMM2 modules on the desktop, although the presentation only mentions CAMM2 for the desktop, something we've already seen that MSI is working on.

The next-generation PC DDR6 memory standard (not to be confused with GDDR6), will offer a 10-times increase in bandwidth over DDR4, according to a presentation by Synopsys, a major vendor of memory controller and PHY IP blocks. The initial draft of DDR6 specification by JEDEC is expected to be ready within 2024, with version 1.0 of the spec ready by mid-2025. Speeds (data-rates) of DDR6 start at DDR6-8800, and range up to DDR6-17600 in the first generation; with future generations of DDR6 going all the way up to DDR6-21333 (or 21 Gbps). This is exactly 10 times the bandwidth of DDR4-2133, the initial speed of DDR4 that debuted with 6th Gen Core "Skylake" processors, almost a decade ago. It hence makes sense for a memory specification 10 years since to offer such a linear scaling in bandwidth.

Synopsys also talks about LPDDR6 in this presentation, the future low power memory standard for thin-and-light computing devices and smartphones. LPDDR6 will have an introductory data-rate of LPDDR6-10667 over a 24-bit memory channel, with two 12-bit sub-channels. The highest defined data-rate for LPDDR6 is expected to be LPDDR6-14400 (likely 14466 MT/s). Besides generational increases in bandwidth, both PC DDR6 and LPDDR6 are expected to introduce several security and energy-efficiency features, including an "efficiency mode" that reduces idle power draw for the memory devices.