Monday, July 22nd 2024
JEDEC Unveils Plans for DDR5 MRDIMM and LPDDR6 CAMM Standards to Propel High-Performance Computing and AI
JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, proudly announces upcoming standards for advanced memory modules designed to power the next generation of high-performance computing and AI applications. JEDEC today revealed key details about its upcoming standards for DDR5 Multiplexed Rank Dual Inline Memory Modules (MRDIMM) and a next-generation Compression-Attached Memory Module (CAMM) for LPDDR6. The new MRDIMM and CAMM for LPDDR6 are set to revolutionize the industry with unparalleled bandwidth and memory capacity.
The JEDEC MRDIMM standard is set to deliver up to twice the peak bandwidth of native DRAM, enabling applications to surpass current data rates and achieve new levels of performance. It maintains the same capacity, reliability, availability, serviceability (RAS) features as JEDEC RDIMM. The committee aims to double the bandwidth to 12.8 Gbps and increase the pin speed. MRDIMM is envisioned to support more than two ranks and is being designed to utilize standard DDR5 DIMM components ensuring compatibility with conventional RDIMM systems.
DDR5 MRDIMMs offer an innovative, efficient new module design to enhance data transfer rates and overall system performance. Multiplexing allows multiple data signals to be combined and transmitted over a single channel, effectively increasing the bandwidth without the need for additional physical connections and providing a seamless bandwidth upgrade to enable applications to exceed DDR5 RDIMM data rates. Other planned features include:
As a follow-on to JEDEC's JESD318 CAMM2 Memory Module standard, JC-45 is developing a next-generation CAMM module for LPDDR6 targeting a maximum speed greater than 14.4 GT/s. As planned, the module will also offer a 24-bit subchannel, a 48-bit channel and a connector array.
Both projects are in development in JEDEC's JC-45 Committee for DRAM Modules. JEDEC encourages companies to join and help shape the future of JEDEC standards. Membership grants access to pre-publication proposals and provides early insights into active projects such as MRDIMM.
The JEDEC MRDIMM standard is set to deliver up to twice the peak bandwidth of native DRAM, enabling applications to surpass current data rates and achieve new levels of performance. It maintains the same capacity, reliability, availability, serviceability (RAS) features as JEDEC RDIMM. The committee aims to double the bandwidth to 12.8 Gbps and increase the pin speed. MRDIMM is envisioned to support more than two ranks and is being designed to utilize standard DDR5 DIMM components ensuring compatibility with conventional RDIMM systems.
- Platform compatibility with RDIMM for flexible end-user bandwidth configuration
- Utilization of standard DDR5 DIMM components including DRAM, DIMM Form Factor & Pinout, SPD, PMIC, and TS for ease of adoption
- Efficient I/O scaling using RCD/DB logic process capability
- Leverage existing LRDIMM ecosystem for design and test infrastructure
- Support for Multi-generational scaling to DDR5-EOL
As a follow-on to JEDEC's JESD318 CAMM2 Memory Module standard, JC-45 is developing a next-generation CAMM module for LPDDR6 targeting a maximum speed greater than 14.4 GT/s. As planned, the module will also offer a 24-bit subchannel, a 48-bit channel and a connector array.
Both projects are in development in JEDEC's JC-45 Committee for DRAM Modules. JEDEC encourages companies to join and help shape the future of JEDEC standards. Membership grants access to pre-publication proposals and provides early insights into active projects such as MRDIMM.
3 Comments on JEDEC Unveils Plans for DDR5 MRDIMM and LPDDR6 CAMM Standards to Propel High-Performance Computing and AI
JDEC SLOWS the market down. They intentionally take too long.
JEDEC for a large part doesn't just lead but will also bring into implement features that some companies bring up, or in some cases may have wanted to rather not implement. I'm sure the on-die ECC feature in DDR5 is a feature a couple of manufacturers would probably rather have swerved.
With the tighter integration of the memory controller onto CPU blocks / SoCs, it's a slower process transitioning to a newer memory tech. When the system chipset had the memory controller it was a bit easier to add new memory tech (LGA 775 saw DDR1 > DDR3 in its lifetime) so you could literally take an old crappy Pentium 4 and run it with DDR3 RAM. Even the original Pentium saw chipset support ranging from SIMM memory to SDRAM DIMM within it's lifetime. That sort of 'upgrade' path is now gone.
Intel/AMD/Qualcomm/Apple/MediaTek/etc. will all design for what is / will be available during their product run - for sure they could ignore JEDEC and partner with an IC maker to have their own memory standard but then this will limit them to relying on that one supplier and not being able to switch to a cheaper option, or worse still if that supplier wants to stop then not having an alternative. This just harks back to the Rambus and NEC's VC RAM standards that ultimately demonstrated my above points.