Synopsys, Inc. announced today its ongoing close collaboration with Samsung Foundry to power the next generation of designs for advanced edge AI, HPC, and AI applications. The collaboration between the companies is helping mutual customers achieve successful tape-outs of their complex designs using Synopsys' 3DIC Compiler and Samsung's advanced packaging technologies with fast turnaround time. Mutual customers can improve power, performance and area (PPA) with certified EDA flows for SF2P process, and minimize IP integration risk with the high-quality portfolio of IP on Samsung's most advanced process technologies.

"The adoption of Edge AI applications is driving the need for advancements in semiconductor technologies to enable complex computational tasks, improve efficiency, and expand AI capabilities across various industries and applications," said John Koeter, senior vice president for the Synopsys IP Group. "Together with Samsung Foundry, we're enabling the most advanced AI processors across a broad spectrum of use cases from high-performance AI inference engines for data centers to ultra-efficient Edge AI devices like cameras and drones, all optimized for development on sub-2 nm Samsung Foundry process technologies."

Late last month, speculative Snapdragon 8 Elite Gen 2 (aka SM8850) technical details emerged online. Up until then, Digital Chat Station's Weibo channel has delivered all sorts of pre-release information—mostly concentrating on Qualcomm's alleged redeployment of a familiar "2 + 6" core configuration, and selection of TSMC's 3 nm "N3P" node process. Earlier today, the veteran leaker predicted a couple of new-gen improvements—first concentrating on the alleged mobile chipset's "Adreno 840" integrated graphics solution. Digital Chat Station (DCS) believes that the company's engineering team has increased their iGPU design's independent cache size "from 12 MB to 16 MB," leading to: "early setting performance increased by 30%±." It is not clear whether this rumored upgrade has affected the SoC's L2 or L3 cache provisions, but the current-gen Snapdragon 8 Elite mobile processor makes do with 12 MB of L2 cache per cluster. Additionally, DCS reckons that an enlargement of caches has resulted in performance of Qualcomm's "second-generation self-developed CPU architecture" increasing "by 25%±."

As interpreted by Wccftech: "the upcoming SoC will now feature 32 MB of L2 cache, with the L3 count currently unknown at this time. The initial test results revealed that the 'Snapdragon 8 Elite Gen 2' delivered a 30 percent performance increase, but it is unconfirmed if this delta exists between the Snapdragon 8 Elite or some other silicon." DCS has heard whispers about the upcoming chip supporting "new generations of high-speed LPDDR5X/LPDDR6" memory. The mentioning of LPDDR5X is not surprising; given that the current Snapdragon 8 Elite model is already up to snuff with this spec. Just over a year ago, JEDEC was reportedly working on the finalization of LPDDR6 standards for mobile platforms. Shortly thereafter, smartphone industry watchdogs started to theorize about the arrival of a so-called "Snapdragon 8 Gen 4" chip with LPDDR6 RAM in 2025. Fast-forward to the present day; fresh reports suggest that manufacturers will have the option to outfit next-gen flagship devices with "bog-standard" LPDDR5X or faster/more efficient LPDDR6 memory.

Samsung Electronics and SK hynix are working together to standardize "Low Power Double Data Rate 6 (LPDDR6) - Processing in Memory (PIM)" technology according to a report from Business Korea. This collaboration seeks to accelerate the development of low power memory products. The cooperation is still in its early stage, the companies initial work is focused on registering the standard with the Joint Electron and Device Engineering Council (JEDEC). Discussions are underway to determine technical requirements, specific characteristics of LPDDR with PIM, such as "internal bandwidth"—the data transfer rate within the memory, unlike the "external bandwidth" between the processor and memory in traditional systems. According to a Samsung Electronics representative, the two companies are in the process of developing a timeline for standardization.

This partnership is notable given how Samsung and SK hynix compete in the high-bandwidth memory (HBM) market. SK hynix beat Samsung in profits reporting 7.3 trillion won in the third quarter, while Samsung made 3.86 trillion won. However, the rise of AI with its increased demand for more memory has shaken up the scene pushing for teamwork instead of wasting resources in developing completely different and unstandardized products. Both firms see PIM technology as a way to grow, previous attempts to independently develop PIM products include Samsung's HBM and LPDDR5-PIM and SK hynix's GDDR6-PIM.

JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, proudly announces upcoming standards for advanced memory modules designed to power the next generation of high-performance computing and AI applications. JEDEC today revealed key details about its upcoming standards for DDR5 Multiplexed Rank Dual Inline Memory Modules (MRDIMM) and a next-generation Compression-Attached Memory Module (CAMM) for LPDDR6. The new MRDIMM and CAMM for LPDDR6 are set to revolutionize the industry with unparalleled bandwidth and memory capacity.

The JEDEC MRDIMM standard is set to deliver up to twice the peak bandwidth of native DRAM, enabling applications to surpass current data rates and achieve new levels of performance. It maintains the same capacity, reliability, availability, serviceability (RAS) features as JEDEC RDIMM. The committee aims to double the bandwidth to 12.8 Gbps and increase the pin speed. MRDIMM is envisioned to support more than two ranks and is being designed to utilize standard DDR5 DIMM components ensuring compatibility with conventional RDIMM systems.

Last week, we got confirmation from the highest levels of Dell and NVIDIA that the latter is making a client PC processor for the Windows on Arm (WoA) AI PC ecosystem that only has one player in it currently, Qualcomm. Michael Dell hinted that this NVIDIA AI PC processor would be ready in 2025. Since then, speculation has been rife about the various IP blocks NVIDIA could use in the development of this chip, the two key areas of debate have been the CPU cores and the process node.

Given that NVIDIA is gunning toward a 2025 launch of its AI PC processor, the company could implement reference Arm IP CPU cores, such as the Arm Cortex X5 "Blackhawk," and not venture out toward developing its own CPU cores on the Arm machine architecture, unlike Apple. Depending on how the market recieves its chips, NVIDIA could eventually develop its own cores. Next up, the company could use the most advanced 3 nm-class foundry node available in 2025 for its chip, such as the TSMC N3P. Given that even Apple and Qualcomm will build their contemporary notebook chips on this node, it would be a logical choice of node for NVIDIA. Then there's graphics and AI acceleration hardware.

Yesterday we reported on DDR6 memory hitting new heights of performance and it looks like LPDDR6 will follow suit, at least based on details in a JEDEC presentation. LPDDR6 will just like LPDDR5 be available as solder down memory, but it will also be available in a new LPCAMM2 module. The bus speed of LPDDR5 on LPCAMM2 modules is expected to peak at 9.2 GT/s based on JEDEC specifications, but LPDDR6 will extend this to 14.4 GT/s or roughly a 50 percent increase. However, today the fastest and only LPCAMM2 modules on the retail market which are using LPDDR5X, comes in at 7.5 GT/s, which suggests that launch speeds of LPDDR6 will end up being quite far from the peak speeds.

There will be some other interesting changes to LPDDR6 CAMM2 modules as there will be a move from 128-bit per module to 192-bit per module and each channel will go from 32-bits to 48-bits. Part of the reason for this is that LPDDR6 is moving to a 24-bit channel width, consisting of two 12-bit sub channels, as mentioned in yesterday's news post. This might seem odd at first, but in reality is fairly simple, LPDDR6 will have native ECC (Error Correction Code) or EDC (Error Detection Code) support, but it's currently not entirely clear how this will be implemented on a system level. JEDEC is also looking at developing a screwless solution for the CAMM2 and LPCAMM2 memory modules, but at the moment there's no clear solution in sight. We might also get to see LPDDR6 via LPCAMM2 modules on the desktop, although the presentation only mentions CAMM2 for the desktop, something we've already seen that MSI is working on.

The next-generation PC DDR6 memory standard (not to be confused with GDDR6), will offer a 10-times increase in bandwidth over DDR4, according to a presentation by Synopsys, a major vendor of memory controller and PHY IP blocks. The initial draft of DDR6 specification by JEDEC is expected to be ready within 2024, with version 1.0 of the spec ready by mid-2025. Speeds (data-rates) of DDR6 start at DDR6-8800, and range up to DDR6-17600 in the first generation; with future generations of DDR6 going all the way up to DDR6-21333 (or 21 Gbps). This is exactly 10 times the bandwidth of DDR4-2133, the initial speed of DDR4 that debuted with 6th Gen Core "Skylake" processors, almost a decade ago. It hence makes sense for a memory specification 10 years since to offer such a linear scaling in bandwidth.

Synopsys also talks about LPDDR6 in this presentation, the future low power memory standard for thin-and-light computing devices and smartphones. LPDDR6 will have an introductory data-rate of LPDDR6-10667 over a 24-bit memory channel, with two 12-bit sub-channels. The highest defined data-rate for LPDDR6 is expected to be LPDDR6-14400 (likely 14466 MT/s). Besides generational increases in bandwidth, both PC DDR6 and LPDDR6 are expected to introduce several security and energy-efficiency features, including an "efficiency mode" that reduces idle power draw for the memory devices.