Last week, we got confirmation from the highest levels of Dell and NVIDIA that the latter is making a client PC processor for the Windows on Arm (WoA) AI PC ecosystem that only has one player in it currently, Qualcomm. Michael Dell hinted that this NVIDIA AI PC processor would be ready in 2025. Since then, speculation has been rife about the various IP blocks NVIDIA could use in the development of this chip, the two key areas of debate have been the CPU cores and the process node.

Given that NVIDIA is gunning toward a 2025 launch of its AI PC processor, the company could implement reference Arm IP CPU cores, such as the Arm Cortex X5 "Blackhawk," and not venture out toward developing its own CPU cores on the Arm machine architecture, unlike Apple. Depending on how the market recieves its chips, NVIDIA could eventually develop its own cores. Next up, the company could use the most advanced 3 nm-class foundry node available in 2025 for its chip, such as the TSMC N3P. Given that even Apple and Qualcomm will build their contemporary notebook chips on this node, it would be a logical choice of node for NVIDIA. Then there's graphics and AI acceleration hardware.

Yesterday we reported on DDR6 memory hitting new heights of performance and it looks like LPDDR6 will follow suit, at least based on details in a JEDEC presentation. LPDDR6 will just like LPDDR5 be available as solder down memory, but it will also be available in a new LPCAMM2 module. The bus speed of LPDDR5 on LPCAMM2 modules is expected to peak at 9.2 GT/s based on JEDEC specifications, but LPDDR6 will extend this to 14.4 GT/s or roughly a 50 percent increase. However, today the fastest and only LPCAMM2 modules on the retail market which are using LPDDR5X, comes in at 7.5 GT/s, which suggests that launch speeds of LPDDR6 will end up being quite far from the peak speeds.

There will be some other interesting changes to LPDDR6 CAMM2 modules as there will be a move from 128-bit per module to 192-bit per module and each channel will go from 32-bits to 48-bits. Part of the reason for this is that LPDDR6 is moving to a 24-bit channel width, consisting of two 12-bit sub channels, as mentioned in yesterday's news post. This might seem odd at first, but in reality is fairly simple, LPDDR6 will have native ECC (Error Correction Code) or EDC (Error Detection Code) support, but it's currently not entirely clear how this will be implemented on a system level. JEDEC is also looking at developing a screwless solution for the CAMM2 and LPCAMM2 memory modules, but at the moment there's no clear solution in sight. We might also get to see LPDDR6 via LPCAMM2 modules on the desktop, although the presentation only mentions CAMM2 for the desktop, something we've already seen that MSI is working on.

The next-generation PC DDR6 memory standard (not to be confused with GDDR6), will offer a 10-times increase in bandwidth over DDR4, according to a presentation by Synopsys, a major vendor of memory controller and PHY IP blocks. The initial draft of DDR6 specification by JEDEC is expected to be ready within 2024, with version 1.0 of the spec ready by mid-2025. Speeds (data-rates) of DDR6 start at DDR6-8800, and range up to DDR6-17600 in the first generation; with future generations of DDR6 going all the way up to DDR6-21333 (or 21 Gbps). This is exactly 10 times the bandwidth of DDR4-2133, the initial speed of DDR4 that debuted with 6th Gen Core "Skylake" processors, almost a decade ago. It hence makes sense for a memory specification 10 years since to offer such a linear scaling in bandwidth.

Synopsys also talks about LPDDR6 in this presentation, the future low power memory standard for thin-and-light computing devices and smartphones. LPDDR6 will have an introductory data-rate of LPDDR6-10667 over a 24-bit memory channel, with two 12-bit sub-channels. The highest defined data-rate for LPDDR6 is expected to be LPDDR6-14400 (likely 14466 MT/s). Besides generational increases in bandwidth, both PC DDR6 and LPDDR6 are expected to introduce several security and energy-efficiency features, including an "efficiency mode" that reduces idle power draw for the memory devices.