Next-generation consumer and automotive audio is becoming increasingly sophisticated, and market drivers such as generative AI-based audio processing, immersive soundscapes, and advanced infotainment in software-defined vehicles demand stepped-up audio DSP performance. However, a single DSP can no longer meet escalating compute needs, while multiple DSPs pose significant programming challenges.

Today, OEMs and SoC vendors must perform all multicore hardware design and software development on their own while facing increased time-to-market pressures. At the same time, programmers are grappling with the complexity of software-based synchronization of shared memory regions and the proper partitioning of tasks across the multicore cluster. This can result in designs falling short of performance expectations.

Cadence today announced an expansion of its collaboration with Samsung Foundry, including a new multi-year IP agreement to broaden Cadence memory and interface IP solutions in Samsung Foundry's SF4X, SF5A and SF2P advanced process nodes. Furthering their ongoing technology collaboration, the companies are leveraging Cadence's AI-driven design solutions and Samsung's advanced SF4X, SF4U and SF2P process nodes to deliver high-performance, low-power solutions for AI data center, automotive—including advanced driver-assistance systems (ADAS)—and next-generation RF connectivity applications.

Cadence's AI-driven design solutions and comprehensive portfolio of IP and silicon solutions enhance designers' productivity and accelerate time to market (TTM) for leading-edge SoCs, chiplets and 3D-ICs on advanced Samsung Foundry processes. "We support a full portfolio of IP, subsystems and chiplets on the Samsung Foundry process nodes, and our latest multi-year IP agreement strengthens our ongoing collaboration," said Boyd Phelps, senior vice president and general manager of the Silicon Solutions Group at Cadence. "By combining Cadence's AI-driven design and silicon solutions with Samsung's advanced processes, we're delivering the leading-edge technologies our mutual customers need to innovate and bring their products to market faster."

Cadence today announced the Cadence Tensilica NeuroEdge 130 AI Co-Processor (AICP), a new class of processor designed to complement any neural processing unit (NPU) and enable end-to-end execution of the latest agentic and physical AI networks on advanced automotive, consumer, industrial and mobile SoCs. Based on the proven architecture of the highly successful Tensilica Vision DSP family, the NeuroEdge 130 AICP delivers more than 30% area savings and over 20% savings in dynamic power and energy without impacting performance. It also leverages the same software, AI compilers, libraries and frameworks to deliver faster time to market. Multiple customer engagements are currently underway, and customer interest is strong.

"With the rapid proliferation of AI processing in physical AI applications such as autonomous vehicles, robotics, drones, industrial automation and healthcare, NPUs are assuming a more critical role," said Karl Freund, founder and principal analyst of Cambrian AI Research. "Today, NPUs handle the bulk of the computationally intensive AI/ML workloads, but a large number of non-MAC layers include pre- and post-processing tasks that are better offloaded to specialized processors. However, current CPU, GPU and DSP solutions involve tradeoffs, and the industry needs a low-power, high-performance solution that is optimized for co-processing and allows future proofing for rapidly evolving AI processing needs."

At its annual flagship user event, CadenceLIVE Silicon Valley 2025, Cadence (Nasdaq: CDNS) today announced a major expansion of its Cadence Millennium Enterprise Platform with the introduction of the new Millennium M2000 Supercomputer featuring NVIDIA Blackwell systems, which delivers AI-accelerated simulation at unprecedented speed and scale across engineering and drug design workloads.

The new supercomputer integrates Cadence's industry-leading solvers with NVIDIA HGX B200 systems, NVIDIA RTX PRO 6000 Blackwell Server Edition GPUs and NVIDIA CUDA-X libraries and solver software. This powerful combination delivers dramatic reductions in simulation run times and up to 80X higher performance versus CPU-based systems for electronic design automation (EDA), system design and analysis (SDA), and drug discovery applications. The supercomputer provides a tightly co-optimized hardware-software stack that enables breakthrough performance with up to 20X lower power across multiple disciplines, accelerating the build-out of AI infrastructure, advancing physical AI machine design and pushing the frontiers of drug design.

Cadence today announced a significant expansion of its portfolio of design IP optimized for Intel 18A and Intel 18A-P technologies and certification of Cadence digital and analog/custom design solutions for the latest Intel 18A process design kit (PDK). These advancements are being showcased today at Intel Foundry Direct Connect, underscoring Cadence's continued leadership in driving industry innovation for artificial intelligence and machine learning (AI/ML), high-performance computing (HPC) and advanced mobility applications through its strategic partnership with Intel Foundry.

Cadence has collaborated closely with Intel Foundry to design and optimize a comprehensive range of solutions that fully leverage the innovative features of the Intel 18A/18A-P nodes, including RibbonFET Gate-all-around transistors and PowerVia backside power delivery network. With this collaboration, joint customers can achieve exceptional power, performance and area (PPA) efficiencies, accelerating time to market for cutting-edge system-on-chip (SoC) designs.

Cadence today announced it is furthering its longstanding collaboration with TSMC to accelerate time to silicon for 3D-IC and advanced-node technologies through certified design flows, silicon-proven IP and ongoing technology collaboration. As a leading provider of IP for TSMC N2P, N5 and N3 process nodes, Cadence continues to deliver cutting-edge AI-driven design solutions to the TSMC ecosystem for multiple horizontal applications from chiplets and SoCs to advanced packaging and 3D-ICs. The deep collaboration encompasses certified tools and flows for TSMC's N2P and A16 technologies, paves the way for TSMC's A14 and further unlocks 3D-IC possibilities by extending support for TSMC 3DFabric design and packaging. In addition, Cadence and TSMC are extending tool certification for newly announced TSMC N3C technology based on available N3P design solutions.

Cadence is driving innovation in AI chip design with certified tools and optimized IP for TSMC's advanced N2P and A16 process technologies. Reinforcing its memory IP leadership, Cadence offers TSMC9000 pre-silicon-certified DDR5 12.8G IP for N2P. Cadence digital, custom/analog design and thermal analysis solutions are certified for TSMC N2P and A16 technologies. Combined with continued collaboration on AI-driven digital design solutions for N2P, including leveraging large language models (LLMs), these advancements play an important role in improving digital design flows for future process nodes.

Cadence today announced the industry's first DDR5 12.8 Gbps MRDIMM Gen 2 memory IP system solution on the TSMC N3 process. The new solution addresses the need for greater memory bandwidth to accommodate unprecedented AI processing demands in enterprise and data center applications, including AI in the cloud. The Cadence DDR5 MRDIMM IP boasts a new high-performance, scalable and adaptable architecture based on Cadence's proven and highly successful DDR5 and GDDR6 product lines. With multiple engagements underway with leading AI, HPC and data center customers, this IP solution is already demonstrating its early leadership.

The new Cadence DDR5 IP offers a PHY and a high-performance controller as a complete memory subsystem. The design is validated in hardware using the most recently available MRDIMMs (Gen 2), achieving a best-in-class 12.8 Gbps data rate that doubles the bandwidth using current DDR5 6400 Mbps DRAM parts. The DDR5 IP memory subsystem is based on Cadence's silicon-proven, high-performance architecture, ultra-low latency encryption and industry-leading RAS features. The DDR5 MRDIMM Gen 2 IP is designed to enable advanced SoCs and chiplets with flexible floor plan design options, while the new architecture allows fine-tuning of power and performance based on individual application requirements.

Cadence today announced that it has entered into a definitive agreement with Arm to acquire Arm's Artisan foundation IP business, consisting of standard cell libraries, memory compilers, and general-purpose I/Os (GPIOs) optimized for advanced process nodes at the leading foundries. The transaction will augment Cadence's expanding design IP offerings, anchored by a leading portfolio of protocol and interface IP, memory interface IP, SerDes IP at the most advanced nodes, and embedded security IP from the pending Secure-IC acquisition.

By increasing its footprint in SoC designs, Cadence is reinforcing its commitment to continuously accelerate customers' time to market and to optimize their cost, power and performance on the world's leading foundry processes. Cadence will acquire the Arm Artisan foundation IP business through an asset purchase agreement with a concurrent technology license agreement, to be signed at closing and subject to any existing rights. As part of the transaction, Cadence will acquire a highly talented and experienced engineering team that is well respected in the industry and can help accelerate development of both related and new IP products.

Is this week even real?! After 3+ years of pouring our hearts into each beat, and a DECADE after launching Crypt of the NecroDancer, we've hit the launch button! Rift of the NecroDancer is Out Now! 3...2...1... LET'S GO! The Rift is fully open for battle! The NecroDancer's back in an all-new rhythm game! Dragged into a strange new world, Cadence must engage in musical combat with monsters surging through the Rift! Face pulse-pounding Rhythm Rifts where every beat is a battle, all set to an original soundtrack by Danny Baranowsky and friends.

What YOU Think
We really wanna know! Come join our Discord for maximum launch hype vibes! We're also on Bluesky now too! We'll also be closely monitoring in-game bug reports. This is just the beginning for Rift, and we're so excited to be on this journey with y'all! You can also hang with us during our livestreams. P.S. The best way to support us is to grab the game during launch week, but if you wanna go the extra mile, we've also released a Supporter Upgrade with a couple cute cosmetics

Cadence today announced that MediaTek has adopted the AI-driven Cadence Virtuoso Studio and Spectre X Simulator on the NVIDIA accelerated computing platform for its 2 nm development. As design size and complexity continue to escalate, advanced-node technology development has become increasingly challenging for SoC providers. To meet the aggressive performance and turnaround time (TAT) requirements for its 2 nm high-speed analog IP, MediaTek is leveraging Cadence's proven custom/analog design solutions, enhanced by AI, to achieve a 30% productivity gain.

"As MediaTek continues to push technology boundaries for 2 nm development, we need a trusted design solution with strong AI-powered tools to achieve our goals," said Ching San Wu, corporate vice president at MediaTek. "Closely collaborating with Cadence, we have adopted the Cadence Virtuoso Studio and Spectre X Simulator, which deliver the performance and accuracy necessary to achieve our tight design turnaround time requirements. Cadence's comprehensive automation features enhance our throughput and efficiency, enabling our designers to be 30% more productive."

The search for a new Chief Executive Officer (CEO) of Intel has begun following Pat Gelsinger's departure on Monday. And it is not exactly an easy role to be filled. The tech giant's board is primarily considering external candidates to lead the company through one of its most challenging periods. Among the potential successors is Lip-Bu Tan, a former Intel board member and semiconductor industry veteran. Tan, who previously served as CEO of Cadence Design, left Intel's board in August 2023 after disagreements with Gelsinger over the company's strategic direction. Despite these past tensions, Intel's board has reportedly recently approached Tan to gauge his interest in the position. The search for new leadership is extremely difficult, considering the requirements and massive problems the new CEO would face.

Coming at a critical moment for Intel, which has experienced significant financial challenges under Gelsinger's tenure, the new CEO would need to get the Foundry business to pick up and maintain a solid product roadmap. The company's revenue dropped to $54 billion in 2023, marking a nearly one-third decline since Gelsinger took the helm in 2021. Analysts project Intel's first annual net loss since 1986 this year, with long-term signs of recovery. Gelsinger's exit, which came after the board presented him with the option to retire or be removed, reflects growing impatience with the pace of his ambitious turnaround strategy. The company has appointed CFO David Zinsner and senior executive Michelle Johnston Holthaus as interim co-CEOs while the search committee works to identify a permanent replacement.

Rambus Inc., a premier chip and silicon IP provider making data faster and safer, today announced the industry's first HBM4 Memory Controller IP, extending its market leadership in HBM IP with broad ecosystem support. This new solution supports the advanced feature set of HBM4 devices, and will enable designers to address the demanding memory bandwidth requirements of next-generation AI accelerators and graphics processing units (GPUs).

"With Large Language Models (LLMs) now exceeding a trillion parameters and continuing to grow, overcoming bottlenecks in memory bandwidth and capacity is mission-critical to meeting the real-time performance requirements of AI training and inference," said Neeraj Paliwal, SVP and general manager of Silicon IP, at Rambus. "As the leading silicon IP provider for AI 2.0, we are bringing the industry's first HBM4 Controller IP solution to the market to help our customers unlock breakthrough performance in their state-of-the-art processors and accelerators."

Intel today announced that its lead products on Intel 18A, Panther Lake (AI PC client processor) and Clearwater Forest (server processor), are out of the fab and have powered-on and booted operating systems. These milestones were achieved less than two quarters after tape-out, with both products on track to start production in 2025. The company also announced that the first external customer is expected to tape out on Intel 18A in the first half of next year.

"We are pioneering multiple systems foundry technologies for the AI era and delivering a full stack of innovation that's essential to the next generation of products for Intel and our foundry customers. We are encouraged by our progress and are working closely with customers to bring Intel 18A to market in 2025." -Kevin O'Buckley, Intel senior vice president and general manager of Foundry Services

Intel Corporation today reported second-quarter 2024 financial results. "Our Q2 financial performance was disappointing, even as we hit key product and process technology milestones. Second-half trends are more challenging than we previously expected, and we are leveraging our new operating model to take decisive actions that will improve operating and capital efficiencies while accelerating our IDM 2.0 transformation," said Pat Gelsinger, Intel CEO. "These actions, combined with the launch of Intel 18A next year to regain process technology leadership, will strengthen our position in the market, improve our profitability and create shareholder value."

"Second-quarter results were impacted by gross margin headwinds from the accelerated ramp of our AI PC product, higher than typical charges related to non-core businesses and the impact from unused capacity," said David Zinsner, Intel CFO. "By implementing our spending reductions, we are taking proactive steps to improve our profits and strengthen our balance sheet. We expect these actions to meaningfully improve liquidity and reduce our debt balance while enabling us to make the right investments to drive long-term value for shareholders."

During the European Technology Symposium 2024, TSMC has announced its readiness to manufacture next-generation HBM4 base dies using both 12 nm and 5 nm nodes. This significant development is expected to substantially improve the performance, power consumption, and logic density of HBM4 memory, catering to the demands of high-performance computing (HPC) and artificial intelligence (AI) applications. The shift from a traditional 1024-bit interface to an ultra-wide 2048-bit interface is a key aspect of the new HBM4 standard. This change will enable the integration of more logic and higher performance while reducing power consumption. TSMC's N12FFC+ and N5 processes will be used to produce these base dies, with the N12FFC+ process offering a cost-effective solution for achieving HBM4 performance and the N5 process providing even more logic and lower power consumption at HBM4 speeds.

The company is collaborating with major HBM memory partners, including Micron, Samsung, and SK Hynix, to integrate advanced nodes for HBM4 full-stack integration. TSMC's base die, fabricated using the N12FFC+ process, will be used to install HBM4 memory stacks on a silicon interposer alongside system-on-chips (SoCs). This setup will enable the creation of 12-Hi (48 GB) and 16-Hi (64 GB) stacks with per-stack bandwidth exceeding 2 TB/s. TSMC's collaboration with EDA partners like Cadence, Synopsys, and Ansys ensures the integrity of HBM4 channel signals, thermal accuracy, and electromagnetic interference (EMI) in the new HBM4 base dies. TSMC is also optimizing CoWoS-L and CoWoS-R for HBM4 integration, meaning that massive high-performance chips are already utilizing this technology and getting ready for volume manufacturing.

Quantum computing. Drug discovery. Fusion energy. Scientific computing and physics-based simulations are poised to make giant steps across domains that benefit humanity as advances in accelerated computing and AI drive the world's next big breakthroughs. NVIDIA unveiled at GTC in March the NVIDIA Blackwell platform, which promises generative AI on trillion-parameter large language models (LLMs) at up to 25x less cost and energy consumption than the NVIDIA Hopper architecture.

Blackwell has powerful implications for AI workloads, and its technology capabilities can also help to deliver discoveries across all types of scientific computing applications, including traditional numerical simulation. By reducing energy costs, accelerated computing and AI drive sustainable computing. Many scientific computing applications already benefit. Weather can be simulated at 200x lower cost and with 300x less energy, while digital twin simulations have 65x lower cost and 58x less energy consumption versus traditional CPU-based systems and others.

Cadence's digital and custom/analog flows are certified on the Intel 18A process technology. Cadence design IP supports this node from Intel Foundry, and the corresponding process design kits (PDKs) are delivered to accelerate the development of a wide variety of low-power consumer, high-performance computing (HPC), AI and mobile computing designs. Customers can now begin using the production-ready Cadence design flows and design IP to achieve design goals and speed up time to market.

"Intel Foundry is very excited to expand our partnership with Cadence to enable key markets for the leading-edge Intel 18A process technology," said Rahul Goyal, Vice President and General Manager, Product and Design Ecosystem, Intel Foundry. "We will leverage Cadence's world-class portfolio of IP, AI design technologies, and advanced packaging solutions to enable high-volume, high-performance, and power-efficient SoCs in Intel Foundry's most advanced process technology. Cadence is an indispensable partner supporting our IDM2.0 strategy and the Intel Foundry ecosystem."

During his keynote address today at Intel Foundry Direct Connect, Intel's inaugural foundry event, CEO Pat Gelsinger introduced four members of the company's Foundry Advisory Committee. The committee advises Intel on its IDM 2.0 strategy, including creation and development of a thriving systems foundry for the AI era.
The advisory committee includes leaders from the semiconductor industry and academia, two of whom are also members of Intel's board of directors:

• Chi-Foon Chan, former Co-CEO of Synopsys; former Microprocessor Group general manager at NEC; director at PDF Solutions.
• Joe Kaeser, former CEO of Siemens; supervisory board chair at Siemens Energy and Daimler Truck; supervisory board member at Linde; former member of the board of NXP semiconductor; member of the board of trustees at the World Economic Forum.
• Tsu-Jae King Liu, vice chair of the Foundry Advisory Committee; dean of College of Engineering at the University of California, Berkeley; Intel director; and director at MaxLinear.
• Lip-Bu Tan, chair of the Foundry Advisory Committee; former CEO of Cadence Design Systems; chairman of Walden International; and Intel director; director at Credo Technology Group and Schneider Electric.

TSMC today announced the new 3Dblox 2.0 open standard and major achievements of its Open Innovation Platform (OIP) 3DFabric Alliance at the TSMC 2023 OIP Ecosystem Forum. The 3Dblox 2.0 features early 3D IC design capability that aims to significantly boost design efficiency, while the 3DFabric Alliance continues to drive memory, substrate, testing, manufacturing, and packaging integration. TSMC continues to push the envelope of 3D IC innovation, making its comprehensive 3D silicon stacking and advanced packaging technologies more accessible to every customer.

"As the industry shifted toward embracing 3D IC and system-level innovation, the need for industry-wide collaboration has become even more essential than it was when we launched OIP 15 years ago," said Dr. L.C. Lu, TSMC fellow and vice president of Design and Technology Platform. "As our sustained collaboration with OIP ecosystem partners continues to flourish, we're enabling customers to harness TSMC's leading process and 3DFabric technologies to reach an entirely new level of performance and power efficiency for the next-generation artificial intelligence (AI), high-performance computing (HPC), and mobile applications."

Arm's impending IPO, valued between $60 billion and $70 billion, has reportedly garnered substantial backing from industry giants such as Apple, NVIDIA, Intel, and Samsung, as per sources cited in a Bloomberg report. This much-anticipated public offering serves as a litmus test for investor interest in new chip-related stocks and could reshape the tech industry landscape. While the information remains unofficial, it underscores the significant support Arm has received from major licensees, including Apple, AMD, Cadence, Intel, Google, NVIDIA, Samsung, and Synopsys, with each potentially contributing between $25 million and $100 million, a testament to their confidence in Arm's future prospects. Originally, SoftBank aimed to raise $8 billion to $10 billion through the IPO, but a strategic shift to retain a larger Arm stake revised the target to $5 billion to $7 billion.

This IPO's success holds paramount importance for SoftBank and its CEO, Masayoshi Son, particularly following the Vision Fund's substantial $30 billion loss in the previous fiscal year. Masayoshi Son is reportedly committed to maintaining significant control over Arm, planning to release no more than 10% of the company's shares during this initial phase, aligning with SoftBank's recent acquisition of the Vision Fund's Arm stake and reinforcing their belief in Arm's long-term potential. Arm has enlisted renowned global financial institutions such as Barclays, Goldman Sachs Group, JPMorgan Chase & Co., and Mizuho Financial Group to prepare for the IPO, highlighting the widespread interest in the offering and the anticipated benefits for these financial institutions.

Cadence Design Systems, Inc. and Rambus Inc., a premier chip and silicon IP provider making data faster and safer, today announced that they have entered into a definitive agreement for Cadence to acquire the Rambus SerDes and memory interface PHY IP business. Rambus will retain its digital IP business, including memory and interface controllers and security IP. The expected technology asset purchase also brings Cadence proven and experienced PHY engineering teams in the United States, India and Canada, further expanding Cadence's domain-rich talent base.

"Memory and SerDes IP design and integration continues to be integral to the design of AI, data center and hyperscale applications, CPU architectures and networking devices, and the addition of the Rambus IP and seasoned team further accelerates Cadence's Intelligent System Design strategy, which drives design excellence," said Boyd Phelps, senior vice president and general manager of the IP Group at Cadence. "The acquisition of the Rambus PHY IP broadens Cadence's well-established enterprise IP portfolio and expands its reach across geographies and vertical markets, such as the aerospace and defense market, providing complete subsystem solutions that meet the demands of our worldwide customers."

Last week Micron Technology CEO, Sanjay Mehrotra, announced during an investors meeting that the company's next generation GPU memory—GDDR7—will be arriving next year: "In graphics, industry analysts continue to expect graphics' TAM compound annual growth rate (CAGR) to outpace the broader market, supported by applications across client and data center. We expect customer inventories to normalize in calendar Q3. We plan to introduce our next-generation G7 product on our industry-leading 1ß node in the first half of calendar year 2024." His proposed launch window seems to align with information gleaned from previous reports—with NVIDIA and AMD lined up to fit GDDR7 SGRAM onto their next-gen mainstream GPUs, although Team Green could be delaying their Ada Lovelace successor into 2025.

Micron already counts these big players as key clients for its current GDDR6 and GDDR6X video memory offerings, but Samsung could be vying for some of that action with its own GDDR7 technology (as announced late last year). Presentation material indicated that Samsung is anticipating data transfer rates in the range of 36 Gbps, with usage of PAM3 signalling. Cadence has also confirmed similar numbers for its (industry first) GDDR7 verification solution, but the different encoding standard will require revising of memory controllers and physical interfaces.

Cadence Design Systems, Inc. today announced that it has collaborated with TSMC to optimize the Cadence Virtuoso platform for the 79 GHz mmWave design reference flow on TSMC's N16 process. With this latest development in Cadence and TSMC's long history of collaboration, joint customers now have access to a complete 79 GHz mmWave design reference flow on the N16 process for developing optimized, highly reliable, next-generation RFIC designs for use in radar, 5G and other wireless applications for the mobile, automotive, healthcare and aerospace markets. Customers have already started using the corresponding TSMC PDKs for RFIC design work.

The Cadence RFIC solution that supports TSMC's N16 process technology features automation capabilities to help customers spend less time integrating critical RF functionality into their designs. The solution supports all aspects of RF design, including passive device modeling, assisted layout automation, block-level optimization and EM signoff simulations.

Amid the US sanctions, Chinese technology giant Huawei has reportedly developed tools to create processors with 14 nm and above lithography. According to Chinese media Yicai, Huawei and its semiconductor partners have teamed up to create replacement tools in place of US chip toolmakers like Cadence, Synopsys, and Mentor/Siemens. These three companies control all of the world's Electronic Design Automation (EDA) tools used for every step of chip design, from architecture to placement and routing to the final physical layout. Many steps need to be taken before making a tapeout of a physical chip, and Huawei's newly developed EDA tools will help the Chinese industry with US sanctions which crippled Huawei for a long time.

Having no access to US-made chipmaking tools, Huawei has invested substantial time into making these EDA tools. However, with competing EDA makers supporting lithography way below 14 nm, Huawei's job still needs to be completed. Chinese semiconductor factories are currently capable of 7 nm chip production, and Huawei itself is working on making a sub-7 nm EUV scanner to aid manufacturing goals and compete with the latest from TSMC and other. If Huawei can create EUV scanners that can achieve transistor sizes smaller than 7 nm, we expect to see their EDA tools keep pace as well. It is only a matter of time before they announce adaptation for smaller nodes.

With Samsung Electronics announcing that the next-generation GDDR7 memory standard is in development, and Cadence, a vital IP provider for DRAM PHY, EDA software, and validation tools announcing its latest validation solution, the decks are clear for the new memory standard to debut with the next-generation of GPUs. GDDR7 would succeed GDDR6, which had debuted in 2018, and has been around for nearly 5 years now. GDDR6 launched with speeds of 14 Gbps, and its derivatives are now in production with speeds as high as 24 Gbps. It provided a generational doubling in speeds from the preceding GDDR5.

The new GDDR7 promises the same, with its starting speeds said to be as high as 36 Gbps, going beyond the 50 Gbps mark in its lifecycle. A MyDrivers report says that NVIDIA's next-generation GeForce RTX 50-series, probably slated for a late-2024 debut, as well as AMD's competing RDNA4 graphics architecture, could introduce GDDR7 at its starting speeds of 36 Gbps. A GPU with a 256-bit wide GDDR7 interface would enjoy 1.15 TB/s of bandwidth, and one with 384-bit would have a cool 1.7 TB/s to play with. We still don't know what is the codename of NVIDIA's next graphics architecture, it could be any of the ones NVIDIA hasn't used from the image below.