Friday, May 17th 2024
TSMC Unveils Next-Generation HBM4 Base Dies, Built on 12 nm and 5 nm Nodes
During the European Technology Symposium 2024, TSMC has announced its readiness to manufacture next-generation HBM4 base dies using both 12 nm and 5 nm nodes. This significant development is expected to substantially improve the performance, power consumption, and logic density of HBM4 memory, catering to the demands of high-performance computing (HPC) and artificial intelligence (AI) applications. The shift from a traditional 1024-bit interface to an ultra-wide 2048-bit interface is a key aspect of the new HBM4 standard. This change will enable the integration of more logic and higher performance while reducing power consumption. TSMC's N12FFC+ and N5 processes will be used to produce these base dies, with the N12FFC+ process offering a cost-effective solution for achieving HBM4 performance and the N5 process providing even more logic and lower power consumption at HBM4 speeds.
The company is collaborating with major HBM memory partners, including Micron, Samsung, and SK Hynix, to integrate advanced nodes for HBM4 full-stack integration. TSMC's base die, fabricated using the N12FFC+ process, will be used to install HBM4 memory stacks on a silicon interposer alongside system-on-chips (SoCs). This setup will enable the creation of 12-Hi (48 GB) and 16-Hi (64 GB) stacks with per-stack bandwidth exceeding 2 TB/s. TSMC's collaboration with EDA partners like Cadence, Synopsys, and Ansys ensures the integrity of HBM4 channel signals, thermal accuracy, and electromagnetic interference (EMI) in the new HBM4 base dies. TSMC is also optimizing CoWoS-L and CoWoS-R for HBM4 integration, meaning that massive high-performance chips are already utilizing this technology and getting ready for volume manufacturing.
Source:
AnandTech
The company is collaborating with major HBM memory partners, including Micron, Samsung, and SK Hynix, to integrate advanced nodes for HBM4 full-stack integration. TSMC's base die, fabricated using the N12FFC+ process, will be used to install HBM4 memory stacks on a silicon interposer alongside system-on-chips (SoCs). This setup will enable the creation of 12-Hi (48 GB) and 16-Hi (64 GB) stacks with per-stack bandwidth exceeding 2 TB/s. TSMC's collaboration with EDA partners like Cadence, Synopsys, and Ansys ensures the integrity of HBM4 channel signals, thermal accuracy, and electromagnetic interference (EMI) in the new HBM4 base dies. TSMC is also optimizing CoWoS-L and CoWoS-R for HBM4 integration, meaning that massive high-performance chips are already utilizing this technology and getting ready for volume manufacturing.
13 Comments on TSMC Unveils Next-Generation HBM4 Base Dies, Built on 12 nm and 5 nm Nodes
Or is this old architecture about to change substantially? The guys at SemiEngineering have a thorough understanding of what they write about, and they say, "SK hynix said the collaboration will enable breakthroughs in memory performance with increased density of the memory controller at the base of the HBM stack."
It's a shame AI is eating up all the HBM, can you imagine what that new Strix Halo APU would be capable of with 16GB of HBM on package?
And if a GPU is rated for over 150W of power, what do you keep left for the CPU? Your starting to get into absurd cooling territory here if it was just for an APU.
upcommons.upc.edu/bitstream/handle/2117/362010/HBM.pdf
HBM STRUCTURE AND FEATURES
Point B
I wonder then if they are going to move from the 1024bit interface to say 1536 or 2048 per die? This just means you can go >8 "stacks" per die is what SK Hynix was alluding to?
AMD's 8000g series seem to scale pretty linearly with memory bandwidth. I know HBM4 would be massive overkill for this but fast ram does help.
Consumer cards don't need anywhere near the latest HBM either. They'd be fine with going with last gen to save money. People are mad at the unjustified inflation of GPU prices, which makes sense given performance per dollar metrics have hardly been improving (particularly on the "low" end). Meanwhile game requirements are increasing, which has translated to a regression in how much performance people's budgets get them in new games.
Demeaning these complaints as "billow biting" and "tantrums" is simply ignoring these facts and is nothing more than a Ad Hominen attack designed to discredit anyone that disagrees with your argument without actually having to debate the facts.
I really don't think a price increase would be required at all given Nvidia operates at a gross margin of 64% (vastly higher than even Apple) but I also don't think people would be mad at a $30 price increase on their $1,000 GPU if it meant more memory bandwidth and lower power usage. Nvidia has already make the argument that new nodes are a large part of why pricing has increased (an argument that is dubious in part because their profit margins have increased in tune with their price increases and the fact that wafer cost is only a portion of their total expenses). Following Nvidia's own logic, nodes are expensive and therefore the cost to implment HBM becomes increasingly trivial as compared to the rising cost of nodes. Especially when you consider a cash starved AMD did it back when they were only making 1/3rd of the margins Nvidia is now.
P.S.: Intel used to make Kaby Lake-G with single HBM2 stack on board. These still being used in specific embedded systems, like this, for around $300. This is obvious, that these APU's are old, and the HBM2 stacks have been installed more than five years ago, when the HBM prices were nowhere as expensive. But there's nothing wrong in this concept, and the NUCs based on KBL-G used to have impressive performance. I don't see why AMD can't revive this approach, since they benefit from it like no one else.
HBM now due to the AI craze etc now cannot keep up with demand. I mean all of SKs 2025 production has been purchased if I remember correctly from a few weeks ago plus
www.trendforce.com/news/2024/05/14/news-samsung-and-sk-hynix-urgently-reallocate-20-of-dram-production-capacity-to-support-rising-hbm-demand/
So that "cheap" HBM that was offered back at the HBM1/2 days is NOT there anymore and it asks a hell of a premium vs GDDR.
Do you want to sell a $70k B200 or a $3k 5090........ You see where I am getting at.
Of course, HMB isn't viable inside desktop APUs, and it's clear, as those are direct derivatives of mobile silicon. But still, there could be some laptops and mini-PCs, where the there's plenty of space for bigger package substrate/die area (and it isn't restricted by IHS/socket), which would benefit such devices, since it will lower (not remove) the need of fast and expensive SODIMMs, at least for an iGPU.
But it's hard to tell if this approach is worth or not, since neither AMD, nor Intel got any consumer grade products on the market right now, that would have had an APU+HBM concept, even in limited amounts. Because, yeah, the entire HBM stocks went solely into the enterprise stuff.
But that's my take.
P.S.: "3K for 5090" is still too overpriced. There's no reason consumer cards with GDDR having such price tags. I doubt, that even with that that pricey exclusive GDD6x, costs a grand. And it's even more ridiculous, to see AMD cards being neck-and-neck in price with nVidia counterparts, while having "regular" slower GRDDR6.
Consider also that HBM allocation is secured years in advance to ensure partners are able to build out production to meet customer requirements. The current shortfall is due to unexpected demand and that's where you start seeing supply constraints in the semi-conductor industry as production cannot just be picked up willy-nilly. IF Nvidia wanted some 4000 series cards to have HBM, it would have secured allocation at least 1 year or more ahead of time. They would have signed a contract agreeing to reasonable rates and allotment at that time, meaning they would have gotten much better pricing than you do in the current market. Pretty much what you are saying would only be relevant if Nvidia wanted some 5000 series cards to have HBM, which indeed is unlikely due to the pricing increase and short supply. That said it doesn't apply to the 4000 series, were Nvidia signed contracts securing their wafers and memory way before HBM supply became an issue. I'd assume this is indeed the reason why Nvidia is putting everything into enterprise / AI. The price they are fetching for those cards is insane.
So what do you do. Make it a halo only product again? 69xx maybe having HBM? So you either go for the top end of HBM2 which was available at the time as it was limited to 8Gb per package or your looking at 4 dies of the more common 4Gb layout to make it up to the 16Gb of the eventual 6900xt. So now you are talking a 4096bit bus on a consumer GPU. How big is this die going to end up? HBM2e/HBM3 upped the dies per package to 12 drastically increasing the memory density available hence why were are now seeing insane memory on the MI250/H100 and their upcoming replacements but they had only really just been announced when the 6900xt was being released. AI went into HYPERDRIVE at that point but there was a build up of AI focus since 2016 when nVidia gifted their 1st DGX1 to OpenAI and it was always going to happen but was a question of when it would become viable outside of supercomputer. 3080 and especially the 3090s gave people the ability to do LLM on their home systems and the 4080/90s are even better at it due to increased power and VRAM. Its why everyone not just nVidia is focusing so heavily on it. Its got similar demand as the crypto boom but the difference is that people are willing to add 000s to cheques to guarantee they get what they want when they want it. Its why your seeing things like AMD helping TinyCorp trying to get RDNA3 into the datacenter as getting more AMD products into the datacenter means more EPYC and Instinct accelerators in there as well in the longer term.