Synopsys, Inc. today announced its continued, close collaboration with TSMC to deliver advanced EDA and IP solutions on TSMC's most advanced process and 3DFabric technologies to accelerate innovation for AI and multi-die designs. The relentless computational demands in AI applications require semiconductor technologies to keep pace. From an industry leading AI-driven EDA suite, powered by Synopsys.ai for enhanced productivity and silicon results to complete solutions that facilitate the migration to 2.5/3D multi-die architectures, Synopsys and TSMC have worked closely for decades to pave the path for the future of billion to trillion-transistor AI chip designs.

"TSMC is excited to collaborate with Synopsys to develop pioneering EDA and IP solutions tailored for the rigorous compute demands of AI designs on TSMC advanced process and 3DFabric technologies," said Dan Kochpatcharin, head of the Ecosystem and Alliance Management Division at TSMC. "The results of our latest collaboration across Synopsys' AI-driven EDA suite and silicon-proven IP have helped our mutual customers significantly enhance their productivity and deliver remarkable performance, power, and area results for advanced AI chip designs.

Synopsys, Inc. today announced the industry's first complete UCIe IP solution operating at up to 40 Gbps per pin to address the increased compute performance requirements of the world's fastest AI data centers. The UCIe interconnect, the de facto standard for die-to-die connectivity, is critical for high-bandwidth, low-latency die-to-die connectivity in multi-die packages, enabling more data to travel efficiently across heterogeneous and homogeneous dies, or chiplets, in today's AI data center systems.

Synopsys' 40G UCIe IP supports both organic substrate and high-density, advanced packaging technologies to give designers the flexibility to explore the packaging options that best fit their needs. The complete Synopsys 40G UCIe IP solution, including PHY, controller, and verification IP, is a key component of Synopsys' comprehensive and scalable multi-die solution for fast heterogeneous integration from early architecture exploration to manufacturing.

Samsung Electronics is set to make a significant leap in semiconductor manufacturing technology with the introduction of its first High-NA 0.55 EUV lithography tool. The company plans to install the ASML Twinscan EXE:5000 system at its Hwaseong campus between Q4 2024 and Q1 2025, marking a crucial step in developing next-generation process technologies for logic and DRAM production. This move positions Samsung about a year behind Intel but ahead of rivals TSMC and SK Hynix in adopting High-NA EUV technology. The system is expected to be operational by mid-2025, primarily for research and development purposes. Samsung is not just focusing on the lithography equipment itself but is building a comprehensive ecosystem around High-NA EUV technology.

The company is collaborating with several key partners like Lasertec (developing inspection equipment for High-NA photomasks), JSR (working on advanced photoresists), Tokyo Electron (enhancing etching machines), and Synopsys (shifting to curvilinear patterns on photomasks for improved circuit precision). The High-NA EUV technology promises significant advancements in chip manufacturing. With an 8 nm resolution capability, it could make transistors about 1.7 times smaller and increase transistor density by nearly three times compared to current Low-NA EUV systems. However, the transition to High-NA EUV comes with challenges. The tools are more expensive, costing up to $380 million each, and have a smaller imaging field. Their larger size also requires chipmakers to reconsider fab layouts. Despite these hurdles, Samsung aims for commercial implementation of High-NA EUV by 2027.

Intel today announced that its lead products on Intel 18A, Panther Lake (AI PC client processor) and Clearwater Forest (server processor), are out of the fab and have powered-on and booted operating systems. These milestones were achieved less than two quarters after tape-out, with both products on track to start production in 2025. The company also announced that the first external customer is expected to tape out on Intel 18A in the first half of next year.

"We are pioneering multiple systems foundry technologies for the AI era and delivering a full stack of innovation that's essential to the next generation of products for Intel and our foundry customers. We are encouraged by our progress and are working closely with customers to bring Intel 18A to market in 2025." -Kevin O'Buckley, Intel senior vice president and general manager of Foundry Services

Intel Corporation today reported second-quarter 2024 financial results. "Our Q2 financial performance was disappointing, even as we hit key product and process technology milestones. Second-half trends are more challenging than we previously expected, and we are leveraging our new operating model to take decisive actions that will improve operating and capital efficiencies while accelerating our IDM 2.0 transformation," said Pat Gelsinger, Intel CEO. "These actions, combined with the launch of Intel 18A next year to regain process technology leadership, will strengthen our position in the market, improve our profitability and create shareholder value."

"Second-quarter results were impacted by gross margin headwinds from the accelerated ramp of our AI PC product, higher than typical charges related to non-core businesses and the impact from unused capacity," said David Zinsner, Intel CFO. "By implementing our spending reductions, we are taking proactive steps to improve our profits and strengthen our balance sheet. We expect these actions to meaningfully improve liquidity and reduce our debt balance while enabling us to make the right investments to drive long-term value for shareholders."

Today marks a new milestone in the growth of Intel Foundry's design ecosystem as key partners Ansys, Cadence, Siemens, and Synopsys have announced the availability of reference flows for Intel's embedded multi-die interconnect bridge (EMIB) advanced packaging technology. This comes on the heels of recent announcements where those same partners declared readiness for Intel 18A designs. "Today's news shows how Intel Foundry continues to combine the best of Intel with the best of our ecosystem to help our customers realize their AI systems ambitions," said Suk Lee, vice president for Ecosystem Development, Intel Foundry.

The success of Intel Foundry is rooted in collaboration with a vibrant design ecosystem. This ensures customers can access our leading process and packaging technologies. Now, in collaboration with our ecosystem partners, we are making it as easy and as fast as possible for companies to optimize, fabricate and assemble their system-on-chip designs through our foundries, while enabling their designers with validated EDA tools, design flows and IP portfolios for silicon-through-package design. This systems foundry approach allows our customers to innovate at every layer of the stack so they can meet the complex computing demands of the AI era, where chip architectures increasingly rely on multiple CPUs, GPUs and NPUs in a package to achieve performance requirements.

The next-generation PC DDR6 memory standard (not to be confused with GDDR6), will offer a 10-times increase in bandwidth over DDR4, according to a presentation by Synopsys, a major vendor of memory controller and PHY IP blocks. The initial draft of DDR6 specification by JEDEC is expected to be ready within 2024, with version 1.0 of the spec ready by mid-2025. Speeds (data-rates) of DDR6 start at DDR6-8800, and range up to DDR6-17600 in the first generation; with future generations of DDR6 going all the way up to DDR6-21333 (or 21 Gbps). This is exactly 10 times the bandwidth of DDR4-2133, the initial speed of DDR4 that debuted with 6th Gen Core "Skylake" processors, almost a decade ago. It hence makes sense for a memory specification 10 years since to offer such a linear scaling in bandwidth.

Synopsys also talks about LPDDR6 in this presentation, the future low power memory standard for thin-and-light computing devices and smartphones. LPDDR6 will have an introductory data-rate of LPDDR6-10667 over a 24-bit memory channel, with two 12-bit sub-channels. The highest defined data-rate for LPDDR6 is expected to be LPDDR6-14400 (likely 14466 MT/s). Besides generational increases in bandwidth, both PC DDR6 and LPDDR6 are expected to introduce several security and energy-efficiency features, including an "efficiency mode" that reduces idle power draw for the memory devices.

During the European Technology Symposium 2024, TSMC has announced its readiness to manufacture next-generation HBM4 base dies using both 12 nm and 5 nm nodes. This significant development is expected to substantially improve the performance, power consumption, and logic density of HBM4 memory, catering to the demands of high-performance computing (HPC) and artificial intelligence (AI) applications. The shift from a traditional 1024-bit interface to an ultra-wide 2048-bit interface is a key aspect of the new HBM4 standard. This change will enable the integration of more logic and higher performance while reducing power consumption. TSMC's N12FFC+ and N5 processes will be used to produce these base dies, with the N12FFC+ process offering a cost-effective solution for achieving HBM4 performance and the N5 process providing even more logic and lower power consumption at HBM4 speeds.

The company is collaborating with major HBM memory partners, including Micron, Samsung, and SK Hynix, to integrate advanced nodes for HBM4 full-stack integration. TSMC's base die, fabricated using the N12FFC+ process, will be used to install HBM4 memory stacks on a silicon interposer alongside system-on-chips (SoCs). This setup will enable the creation of 12-Hi (48 GB) and 16-Hi (64 GB) stacks with per-stack bandwidth exceeding 2 TB/s. TSMC's collaboration with EDA partners like Cadence, Synopsys, and Ansys ensures the integrity of HBM4 channel signals, thermal accuracy, and electromagnetic interference (EMI) in the new HBM4 base dies. TSMC is also optimizing CoWoS-L and CoWoS-R for HBM4 integration, meaning that massive high-performance chips are already utilizing this technology and getting ready for volume manufacturing.

NVIDIA today announced that TSMC and Synopsys are going into production with NVIDIA's computational lithography platform to accelerate manufacturing and push the limits of physics for the next generation of advanced semiconductor chips. TSMC, the world's leading foundry, and Synopsys, the leader in silicon to systems design solutions, have integrated NVIDIA cuLitho with their software, manufacturing processes and systems to speed chip fabrication, and in the future support the latest-generation NVIDIA Blackwell architecture GPUs.

"Computational lithography is a cornerstone of chip manufacturing," said Jensen Huang, founder and CEO of NVIDIA. "Our work on cuLitho, in partnership with TSMC and Synopsys, applies accelerated computing and generative AI to open new frontiers for semiconductor scaling." NVIDIA also introduced new generative AI algorithms that enhance cuLitho, a library for GPU-accelerated computational lithography, dramatically improving the semiconductor manufacturing process over current CPU-based methods.

During his keynote address today at Intel Foundry Direct Connect, Intel's inaugural foundry event, CEO Pat Gelsinger introduced four members of the company's Foundry Advisory Committee. The committee advises Intel on its IDM 2.0 strategy, including creation and development of a thriving systems foundry for the AI era.
The advisory committee includes leaders from the semiconductor industry and academia, two of whom are also members of Intel's board of directors:

• Chi-Foon Chan, former Co-CEO of Synopsys; former Microprocessor Group general manager at NEC; director at PDF Solutions.
• Joe Kaeser, former CEO of Siemens; supervisory board chair at Siemens Energy and Daimler Truck; supervisory board member at Linde; former member of the board of NXP semiconductor; member of the board of trustees at the World Economic Forum.
• Tsu-Jae King Liu, vice chair of the Foundry Advisory Committee; dean of College of Engineering at the University of California, Berkeley; Intel director; and director at MaxLinear.
• Lip-Bu Tan, chair of the Foundry Advisory Committee; former CEO of Cadence Design Systems; chairman of Walden International; and Intel director; director at Credo Technology Group and Schneider Electric.

Intel Corp. today launched Intel Foundry as a more sustainable systems foundry business designed for the AI era and announced an expanded process roadmap designed to establish leadership into the latter part of this decade. The company also highlighted customer momentum and support from ecosystem partners - including Synopsys, Cadence, Siemens and Ansys - who outlined their readiness to accelerate Intel Foundry customers' chip designs with tools, design flows and IP portfolios validated for Intel's advanced packaging and Intel 18A process technologies.

The announcements were made at Intel's first foundry event, Intel Foundry Direct Connect, where the company gathered customers, ecosystem companies and leaders from across the industry. Among the participants and speakers were U.S. Secretary of Commerce Gina Raimondo, Arm CEO Rene Haas, Microsoft CEO Satya Nadella, OpenAI CEO Sam Altman and others.

The sneak peeks from the upcoming IEEE Solid State Circuit Conference continues, as the agenda items unveil interesting tech that will be either unveiled or demonstrated there. Intel, Synopsys, and Marvell, are leading providers of DRAM physical layer interface (PHY) IP. Various processor, GPU, and SoC manufacturers license PHY and memory controller IP from these companies, to integrate with their designs. All three companies are ready with over 200 Gbps around the 2.69 to 3 petajoule per bit range. This energy cost is as important as the data-rate on offer; as it showcases the viability of the PHY for a specific application (for example, a smartphone SoC has to conduct its memory sub-system at a vastly more constrained energy budget compared to an HPC processor).

Intel is the first in the pack to showcase a 224 Gbps sub-picojoule/bit PHY transmitter that supports PAM4 and PAM6 signaling, and is designed for 3 nm-class FinFET foundry nodes. If you recall, Intel 3 will be the company's final FinFET node before it transitions to nanosheets with the Intel 20A node. At the physical layer, all digital memory signal is analogue, and Intel's IP focuses on the DAC aspect of the PHY. Next up, is a somewhat similar transceiver IP by Synopsys. This too claims 224 Gbps speeds at 3 pJ/b, but at a 40 dB insertion loss; and is designed for 3 nm class FinFET nodes such as the TSMC N3 family and Intel 3. Samsung's 3 nm node uses the incompatible GAAFET technology for its 3 nm EUV node. Lastly, there's Marvell, with a 212 Gb/s DSP-based transceiver for optical direct-detect applications on the 5 nm FinFET nodes, which is relevant for high speed network switching fabrics.

Synopsys (NASDAQ: SNPS) and Ansys (NASDAQ: ANSS) today announced that they have entered into a definitive agreement under which Synopsys will acquire Ansys. Under the terms of the agreement, Ansys shareholders will receive $197.00 in cash and 0.3450 shares of Synopsys common stock for each Ansys share, representing an enterprise value of approximately $35 billion based on the closing price of Synopsys common stock on December 21, 2023. Bringing together Synopsys' pioneering semiconductor electronic design automation (EDA) with Ansys' broad simulation and analysis portfolio will create a leader in silicon to systems design solutions.

"The megatrends of AI, silicon proliferation and software-defined systems are requiring more compute performance and efficiency in the face of growing, systemic complexity. Bringing together Synopsys' industry-leading EDA solutions with Ansys' world-class simulation and analysis capabilities will enable us to deliver a holistic, powerful and seamlessly integrated silicon to systems approach to innovation to help maximize the capabilities of technology R&D teams across a broad range of industries," said Sassine Ghazi, President and CEO of Synopsys. "This is the logical next step for our successful, seven-year partnership with Ansys and I look forward to working closely with Ajei and the talented Ansys team to realize the benefits of this combination for our customers, shareholders and employees."

Synopsys, Inc. (Nasdaq: SNPS) today announced it has extended its ARC Processor IP portfolio to include new RISC-V ARC-V Processor IP, enabling customers to choose from a broad range of flexible, extensible processor options that deliver optimal power-performance efficiency for their target applications. Synopsys leveraged decades of processor IP and software development toolkit experience to develop the new ARC-V Processor IP that is built on the proven microarchitecture of Synopsys' existing ARC Processors, with the added benefit of the expanding RISC-V software ecosystem.

Synopsys ARC-V Processor IP includes high-performance, mid-range, and ultra-low power options, as well as functional safety versions, to address a broad range of application workloads. To accelerate software development, the Synopsys ARC-V Processor IP is supported by the robust and proven Synopsys MetaWare Development Toolkit that generates highly efficient code. In addition, the Synopsys.ai full-stack AI-driven EDA suite is co-optimized with ARC-V Processor IP to provide an out-of-the-box development and verification environment that helps boost productivity and quality-of-results for ARC-V-based SoCs.

Synopsys today announced it has expanded its collaboration with Arm to provide optimized IP and EDA solutions for the newest Arm technology, including the Arm Neoverse V2 platform and Arm Neoverse Compute Subsystem (CSS). Synopsys has joined Arm Total Design where Synopsys will leverage their deep design expertise, the Synopsys.ai full-stack AI-driven EDA suite, and Synopsys Interface, Security, and Silicon Lifecycle Management IP to help mutual customers speed development of their Arm-based CSS solutions. The expanded partnership builds on three decades of collaboration to enable mutual customers to quickly develop specialized silicon at lower cost, with less risk and faster time to market.

"With Arm Total Design, our aim is to enable rapid innovation on Arm Neoverse CSS and engage critical ecosystem expertise at every stage of SoC development," said Mohamed Awad, senior vice president and general manager, Infrastructure Line of Business at Arm. "Our deep technical collaboration with Synopsys to deliver pre-integrated and validated IP and EDA tools will help our mutual customers address the industry's most complex computing challenges with specialized compute."

TSMC today announced the new 3Dblox 2.0 open standard and major achievements of its Open Innovation Platform (OIP) 3DFabric Alliance at the TSMC 2023 OIP Ecosystem Forum. The 3Dblox 2.0 features early 3D IC design capability that aims to significantly boost design efficiency, while the 3DFabric Alliance continues to drive memory, substrate, testing, manufacturing, and packaging integration. TSMC continues to push the envelope of 3D IC innovation, making its comprehensive 3D silicon stacking and advanced packaging technologies more accessible to every customer.

"As the industry shifted toward embracing 3D IC and system-level innovation, the need for industry-wide collaboration has become even more essential than it was when we launched OIP 15 years ago," said Dr. L.C. Lu, TSMC fellow and vice president of Design and Technology Platform. "As our sustained collaboration with OIP ecosystem partners continues to flourish, we're enabling customers to harness TSMC's leading process and 3DFabric technologies to reach an entirely new level of performance and power efficiency for the next-generation artificial intelligence (AI), high-performance computing (HPC), and mobile applications."

Synopsys, Inc. today announced it is extending its collaboration with TSMC to advance multi-die system designs with a comprehensive solution supporting the latest 3Dblox 2.0 standard and TSMC's 3DFabric technologies. The Synopsys Multi-Die System solution includes 3DIC Compiler, a unified exploration-to-signoff platform that delivers the highest levels of design efficiency for capacity and performance. In addition, Synopsys has achieved first-pass silicon success of its Universal Chiplet Interconnect Express (UCIe) IP on TSMC's leading N3E process for seamless die-to-die connectivity.

"TSMC has been working closely with Synopsys to deliver differentiated solutions that address designers' most complex challenges from early architecture to manufacturing," said Dan Kochpatcharin, head of the Design Infrastructure Management Division at TSMC. "Our long history of collaboration with Synopsys benefits our mutual customers with optimized solutions for performance and power efficiency to help them address multi-die system design requirements for high-performance computing, data center, and automotive applications."

Intel Foundry Services (IFS) and Tower Semiconductor, a leading foundry for analog semiconductor solutions, today announced an agreement where Intel will provide foundry services and 300 mm manufacturing capacity to help Tower serve its customers globally. Under the agreement, Tower will utilize Intel's advanced manufacturing facility in New Mexico. Tower will invest up to $300 million to acquire and own equipment and other fixed assets to be installed in the New Mexico facility, providing a new capacity corridor of over 600,000 photo layers per month for Tower's future growth, enabling capacity to support forecasted customer demand for 300 mm advanced analog processing.

This agreement demonstrates the commitment from both Intel and Tower to expand their respective foundry footprints with unparalleled solutions and scaled capabilities. Intel will manufacture Tower's highly differentiated 65-nanometer power management BCD (bipolar-CMOS-DMOS) flows, among other flows at Intel's Fab 11X in Rio Rancho, New Mexico.

Arm's impending IPO, valued between $60 billion and $70 billion, has reportedly garnered substantial backing from industry giants such as Apple, NVIDIA, Intel, and Samsung, as per sources cited in a Bloomberg report. This much-anticipated public offering serves as a litmus test for investor interest in new chip-related stocks and could reshape the tech industry landscape. While the information remains unofficial, it underscores the significant support Arm has received from major licensees, including Apple, AMD, Cadence, Intel, Google, NVIDIA, Samsung, and Synopsys, with each potentially contributing between $25 million and $100 million, a testament to their confidence in Arm's future prospects. Originally, SoftBank aimed to raise $8 billion to $10 billion through the IPO, but a strategic shift to retain a larger Arm stake revised the target to $5 billion to $7 billion.

This IPO's success holds paramount importance for SoftBank and its CEO, Masayoshi Son, particularly following the Vision Fund's substantial $30 billion loss in the previous fiscal year. Masayoshi Son is reportedly committed to maintaining significant control over Arm, planning to release no more than 10% of the company's shares during this initial phase, aligning with SoftBank's recent acquisition of the Vision Fund's Arm stake and reinforcing their belief in Arm's long-term potential. Arm has enlisted renowned global financial institutions such as Barclays, Goldman Sachs Group, JPMorgan Chase & Co., and Mizuho Financial Group to prepare for the IPO, highlighting the widespread interest in the offering and the anticipated benefits for these financial institutions.

Intel and Synopsys announced that they have entered into a definitive agreement to expand the companies' long-standing IP (intellectual property) and EDA (electronic design automation) strategic partnership with the development of a portfolio of IP on Intel 3 and Intel 18A for Intel's foundry customers. The availability of key IP on Intel advanced process nodes will create a more robust offering for new and existing Intel Foundry Services (IFS) customers.

"Marking another important step in our IDM 2.0 strategy, this transaction will foster a vibrant foundry ecosystem by allowing designers to fully realize the advantages of Intel 3 and Intel 18A process technologies and quickly bring differentiated products to market," said Stuart Pann, senior vice president and general manager of IFS. "Synopsys brings a strong track record of delivering high-quality IP to a broad customer base, and this agreement will help accelerate the availability of IP on advanced IFS nodes for mutual customers."

Artificial intelligence (AI) has emerged as a transformative force in chip design, with recent examples from China and the United States showcasing its potential. Jensen Huang, CEO of Nvidia, believes that AI can empower individuals to become programmers, while Lisa Su, CEO of AMD, predicts an era where AI dominates chip design. During the 2023 World Artificial Intelligence Conference (WAIC) in Shanghai, Su emphasized the importance of interdisciplinary collaboration for the next generation of chip designers. To excel in this field, engineers must possess a holistic understanding of hardware, software, and algorithms, enabling them to create superior chip designs that meet system usage, customer deployment, and application requirements.

The integration of AI into chip design processes has gained momentum, fueled by the AI revolution catalyzed by large language models (LLMs). Both Huang and Mark Papermaster, CTO of AMD, acknowledge the benefits of AI in accelerating computation and facilitating chip design. AMD has already started leveraging AI in semiconductor design, testing, and verification, with plans to expand its use of generative AI in chip design applications. Companies are now actively exploring the fusion of AI technology with Electronic Design Automation (EDA) tools to streamline complex tasks and minimize manual intervention in chip design. Despite limited data and accuracy challenges, the "EDA+AI" approach holds great promise. For instance, Synopsys has invested significantly in AI tool research and recently launched Synopsys.ai, the industry's first end-to-end AI-driven EDA solution. This comprehensive solution empowers developers to harness AI at every stage of chip development, from system architecture and design to manufacturing, marking a significant leap forward in AI's integration into chip design workflows.

Synopsys, Inc. today announced an expanded agreement with Samsung Foundry to develop a broad portfolio of IP to reduce design risk and accelerate silicon success for automotive, mobile, high-performance computing (HPC) and multi-die designs. This agreement expands Synopsys' collaboration with Samsung to enhance the Synopsys IP offering for Samsung's advanced 8LPU, SF5, SF4 and SF3 processes and includes Foundation IP, USB, PCI Express, 112G Ethernet, UCIe, LPDDR, DDR, MIPI and more. In addition, Synopsys will optimize IP for Samsung's SF5A and SF4A automotive process nodes to meet stringent Grade 1 or Grade 2 temperature and AEC-Q100 reliability requirements, enabling automotive chip designers to reduce their design effort and accelerate AEC-Q100 qualification. The auto-grade IP for ADAS SoCs will include design failure mode and effect analysis (DFMEA) reports that can save months of development effort for automotive SoC applications.

"Our extensive co-optimization efforts with Samsung across both EDA and IP help automotive, mobile, HPC, and multi-die system architects cope with the inherent challenges of designing chips for advanced process technologies," said John Koeter, senior vice president of product management and strategy for IP at Synopsys. "This extension of our decades-long collaboration provides designers with a low-risk path to achieving their design requirements and quickly launching differentiated products to the market."

In its recent Second Quarter of the Fiscal Year 2023 conference, Synopsys issued interesting information about the recent moves of chip developers and their usage of artificial intelligence. As the call notes, over 200+ chips have been taped out using Synopsys DSO.ai place-and-route (PnR) tool, making it a successful commercially proven AI chip design tool. The DSO.ai uses AI to optimize the placement and routing of the chip's transistors so that the layout is compact and efficient with regard to the strict timing constraints of the modern chip. According to Aart J. de Geus, CEO of Synopsys, "By the end of 2022, adoption, including 9 of the top 10 semiconductor vendors have moved forward at great speed with 100 AI-driven commercial tape-outs. Today, the tally is well over 200 and continues to increase at a very fast clip as the industry broadly adopts AI for design from Synopsys."

This is an interesting fact that means that customers are seeing the benefits of AI-assisted tools like DSO.ai. However, the company is not stopping there, and a whole suite of tools is getting an AI makeover. "We unveiled the industry's first full-stack AI-driven EDA suite, sydnopsys.ai," noted the CEO, adding that "Specifically, in parallel to second-generation advances in DSO.ai we announced VSO.ai, which stands for verification space optimization; and TSO.ai, test space optimization. In addition, we are extending AI across the design stack to include analog design and manufacturing." Synopsys' partners in this include NVIDIA, TSMC, MediaTek, Renesas, and IBM Research, all of which used AI-assisted tools for chip design efforts. A much wider range of industry players is expected to adopt these tools as chip design costs continue to soar as we scale the nodes down. With future 3 nm GPU costing an estimated $1.5 billion, 40% of that will account for software, and Synopsys plans to take a cut in that percentage.

Accelerating the integration of heterogeneous dies to enable the next level of system scalability and functionality, Synopsys, Inc. (Nasdaq: SNPS) has strengthened its collaboration with TSMC and Ansys for multi-die system design and manufacturing. Synopsys provides the industry's most comprehensive EDA and IP solutions for multi-die systems on TSMC's advanced 7 nm, 5 nm and 3 nm process technologies with support for TSMC 3DFabric technologies and 3Dblox standard. The integration of Synopsys implementation and signoff solutions and Ansys multi-physics analysis technology on TSMC processes allows designers to tackle the biggest challenges of multi-die systems, from early exploration to architecture design with signoff power, signal and thermal integrity analysis.

"Multi-die systems provide a way forward to achieve reduced power and area and higher performance, opening the door to a new era of innovation at the system-level," said Dan Kochpatcharin, head of Design Infrastructure Management Division at TSMC. "Our long-standing collaboration with Open Innovation Platform (OIP) ecosystem partners like Synopsys and Ansys gives mutual customers a faster path to multi-die system success through a full spectrum of best-in-class EDA and IP solutions optimized for our most advanced technologies."

Amid the US sanctions, Chinese technology giant Huawei has reportedly developed tools to create processors with 14 nm and above lithography. According to Chinese media Yicai, Huawei and its semiconductor partners have teamed up to create replacement tools in place of US chip toolmakers like Cadence, Synopsys, and Mentor/Siemens. These three companies control all of the world's Electronic Design Automation (EDA) tools used for every step of chip design, from architecture to placement and routing to the final physical layout. Many steps need to be taken before making a tapeout of a physical chip, and Huawei's newly developed EDA tools will help the Chinese industry with US sanctions which crippled Huawei for a long time.

Having no access to US-made chipmaking tools, Huawei has invested substantial time into making these EDA tools. However, with competing EDA makers supporting lithography way below 14 nm, Huawei's job still needs to be completed. Chinese semiconductor factories are currently capable of 7 nm chip production, and Huawei itself is working on making a sub-7 nm EUV scanner to aid manufacturing goals and compete with the latest from TSMC and other. If Huawei can create EUV scanners that can achieve transistor sizes smaller than 7 nm, we expect to see their EDA tools keep pace as well. It is only a matter of time before they announce adaptation for smaller nodes.