Synopsys, Inc. (Nasdaq: SNPS) today announced it has extended its ARC Processor IP portfolio to include new RISC-V ARC-V Processor IP, enabling customers to choose from a broad range of flexible, extensible processor options that deliver optimal power-performance efficiency for their target applications. Synopsys leveraged decades of processor IP and software development toolkit experience to develop the new ARC-V Processor IP that is built on the proven microarchitecture of Synopsys' existing ARC Processors, with the added benefit of the expanding RISC-V software ecosystem.

Synopsys ARC-V Processor IP includes high-performance, mid-range, and ultra-low power options, as well as functional safety versions, to address a broad range of application workloads. To accelerate software development, the Synopsys ARC-V Processor IP is supported by the robust and proven Synopsys MetaWare Development Toolkit that generates highly efficient code. In addition, the Synopsys.ai full-stack AI-driven EDA suite is co-optimized with ARC-V Processor IP to provide an out-of-the-box development and verification environment that helps boost productivity and quality-of-results for ARC-V-based SoCs."The increasing numbers of chips in automotive systems demand resilience in the semiconductor ecosystem, and to that end the industry is pushing for the adoption of open standards like RISC-V," said Thomas Boehm, senior vice president, Automotive Microcontroller at Infineon. "By developing safety-certified RISC-V based processor IP, Synopsys is supporting us to expand the architecture choices with an open standard to build high-performance automotive systems with the highest levels of functional safety, and we look forward to continuing to partner with them in our future products."

"The global adoption of the open-standard RISC-V ISA is defining the future of semiconductor design, and it's through the commitment and advancements from technology innovators like Synopsys that RISC-V continues to accelerate the future of computing," said Calista Redmond, CEO, RISC-V International. "Synopsys ARC-V Processor IP, combined with the company's co-optimized EDA and verification solutions, contribute to greater flexibility and choice in the RISC-V ecosystem for the benefit of chip design across industries."

Decades of Expertise in Processor IP Development for Unique Market Requirements
Synopsys has delivered multiple generations of power-efficient, highly scalable ARC Processors used in billions of automotive, storage, consumer, and IoT SoCs. It is leveraging its deep experience in commercial processor IP development, delivery, and support to expand the portfolio to support the RISC-V ISA. With ARC-V IP, Synopsys is delivering ultra-configurable, extensible processors that enable developers to differentiate their SoCs and optimize for the best power, performance, and area (PPA) balance.

"RISC-V processors are gaining in popularity as more designers look for greater design flexibility and more options," said John Koeter, senior vice president of product management and strategy for IP at Synopsys. "Synopsys answered this call by evolving the ARC Processor IP portfolio to provide our customers with a wider choice for their processing needs based on the proven, scalable RISC-V ISA to help them meet their diverse workload requirements."

Synopsys ARC-V Functional Safety (FS) Processor IP has integrated hardware safety features to detect system errors, support ASIL B and ASIL D safety levels, and accelerate ISO 26262 functional safety and ISO 21434 automotive cybersecurity qualifications. ARC-V FS Processor IP is developed based on Synopsys' ISO 9001-certified Quality Management System (QMS), enabling designers to meet challenging ASIL D systematic development standards. In addition, the MetaWare Development Toolkit for Safety helps software developers accelerate the development of ISO 26262-compliant code.

Portfolio of Solutions to Design and Fully Verify Synopsys ARC-V SoCs
Synopsys offers a variety of tools and technologies to accelerate the design and verification of SoCs using its RISC-V ARC-V Processor IP, including:

• Synopsys.ai, a full-stack AI-driven EDA suite that leverages the power of AI from system architecture through manufacturing to optimize PPA and speed time to market
• Synopsys Fusion QuickStart Implementation Kits, which offer scripts, reference guides, and a baseline floorplan to help customers maximize PPA for ARC-V based designs
• Synopsys verification solutions, including architecture design for system-level analysis and optimization of power and performance, virtual prototypes with Synopsys ARC-V models, hardware-assisted verification, and verification IP to speed verification and software development
• Synopsys Cloud SaaS platform with browser-based access to unlimited EDA licenses, pre-optimized compute, and complete license management automation, enabling designers to deliver higher quality chips ahead of schedule
• Synopsys also announced it has joined the RISC-V International Board of Directors and Technical Steering Committee to support industry adoption of the RISC-V instruction set architecture (ISA) and participate in defining the future of computing architecture standards.

Availability
The Synopsys ARC-V Processor IP portfolio has received industry support in anticipation of its general availability, which will begin in 2024. The 32-bit Synopsys ARC-V RMX embedded processor IP is scheduled to be available in Q2 of 2024. The 32-bit Synopsys ARC-V RHX real-time processor IP and 64-bit Synopsys ARC-V RPX host processor IP are scheduled to be available in the second half of 2024.