According to a Reuters technology report, Meta's engineering department is engaged in the testing of their "first in-house chip for training artificial intelligence systems." Two inside sources have declared this significant development milestone; involving a small-scale deployment of early samples. The owner of Facebook could ramp up production, upon initial batches passing muster. Despite a recent-ish showcasing of an open-architecture NVIDIA "Blackwell" GB200 system for enterprise, Meta leadership is reported to be pursuing proprietary solutions. Multiple big players—in the field of artificial intelligence—are attempting to breakaway from a total reliance on Team Green. Last month, press outlets concentrated on OpenAI's alleged finalization of an in-house design, with rumored involvement coming from Broadcom and TSMC.

One of the Reuters industry moles believes that Meta has signed up with TSMC—supposedly, the Taiwanese foundry was responsible for the production of test batches. Tom's Hardware reckons that Meta and Broadcom were working together with the tape out of the social media giant's "first AI training accelerator." Development of the company's "Meta Training and Inference Accelerator" (MTIA) series has stretched back a couple of years—according to Reuters, this multi-part project: "had a wobbly start for years, and at one point scrapped a chip at a similar phase of development...Meta last year, started using an MTIA chip to perform inference, or the process involved in running an AI system as users interact with it, for the recommendation systems that determine which content shows up on Facebook and Instagram news feeds." Leadership is reportedly aiming to get custom silicon solutions up and running for AI training by next year. Past examples of MTIA hardware were deployed with open-source RISC-V cores (for inference tasks), but is not clear whether this architecture will form the basis of Meta's latest AI chip design.

Codasip, the European RISC-V leader, announced that it has been selected to provide a general purpose, high-end processor as part of the large-scale European supercomputing project Digital Autonomy with RISC-V in Europe (DARE).

DARE is set to build a supercomputing compute stack, featuring high-performance and energy-efficient RISC-V-based processors and accelerators designed and developed in Europe. The European Union has committed 240 million Euros in funding for the first 3-year program phase. The selected partners will leverage hardware/software co-design to achieve competitive performance and efficiency.

Damo Academy—a research and development wing of Alibaba—launched its debut "server-grade processor" design late last week, in Beijing. According to a South China Morning Post (SCMP) news article, the C930 model is a brand-new addition to the e-commerce platform's XuanTie RISC-V CPU series. Company representatives stated that their latest product is designed as a server-level and high-performance computing (HPC) solution. Going back to March 2024, TechPowerUp and other Western hardware news outlets picked up on Alibaba's teasing of the Xuantie C930 SoC, and a related Xuantie 907 matrix processing unit. Fast-forward to the present day; Damo Academy has disclosed that initial shipments—of finalized C930 units—will be sent out to customers this month.

The newly released open-source RISC-V architecture-based HPC chip is an unknown quantity in terms of technical specifications. Damo Academy reps did not provide any detailed information during last Friday's conference (February 28). SCMP's report noted the R&D division's emphasizing of "its role in advancing RISC-V adoption" within various high-end fields. Apparently, the XuanTie engineering team has: "supported the implementation of more than thirty percent of RISC-V high-performance processors." Upcoming additions will arrive in the form of the C908X for AI acceleration, R908A for automotive processing solutions, and an XL200 model for high-speed interconnection. These XuanTie projects are reportedly still deep in development.

On February 27-28, the 2025 China RISC-V Ecosystem Conference was grandly held at the Zhongguancun International Innovation Center in Beijing. As a core promoter in the RISC-V field, SOPHGO was invited to deliver a speech and prominently launch a series of new products based on the SG2044 chip, sharing the company's cutting-edge practices in the heterogeneous fusion of AI and RISC-V, and contributing to the vigorous development of the global open-source instruction set ecosystem. During the conference, SOPHGO set up a distinctive exhibition area that attracted many attendees from the industry to stop and watch.

Focusing on AI Integration, Leading Breakthroughs in RISC-V Technology
At the main forum of the conference, the Vice President of SOPHGO RISC-V delivered a speech titled "RISC-V Breakthroughs Driven by AI: Integration + Heterogeneous Innovation," where he elaborated on SOPHGO's innovative achievements in the deep integration of RISC-V architecture and artificial intelligence technology. He pointed out that current AI technological innovations are driving market changes, and the emergence of DeepSeek has ignited a trillion-level computing power market. The innovation of technical paradigms and the penetration of large models into various sectors will lead to an explosive growth in inference demand, resulting in changes in the structure of computing power demand. This will also reshape the landscape of the computing power market, bringing significant business opportunities to domestic computing power enterprises, while RISC-V high-performance computing is entering a fast track of development driven by AI.

AheadComputing today announced it has secured $21.5M in seed funding to rapidly develop and commercialize its breakthrough microprocessor architecture designed to meet the new, unique computing demands across AI, cloud, and edge devices. The funding was led by Eclipse, with participation from Maverick Capital, Fundomo, EPIQ Capital Group, LLC, and legendary CPU architect and current Tenstorrent CEO Jim Keller, who developed cutting-edge semiconductors for Apple, AMD, Tesla, and Intel.

Today, general-purpose computing faces unprecedented challenges due to the rapid expansion of AI and machine learning workloads. A recent report found that 82% of organizations experienced performance issues with their AI workloads over the past year, primarily due to bandwidth shortages and data processing limitations. While specialized accelerators dominate headlines, they rely heavily on general-purpose processors for critical tasks before, after, and in-between AI operations. Existing architectures have struggled to keep pace with the demands of these emerging workloads, creating a bottleneck in compute performance that impacts industries ranging from cloud to edge computing. AheadComputing addresses this critical gap by providing innovative solutions designed to transform how general-purpose computing meets modern demands.

Baya Systems, a leader in system IP technology that empowers the acceleration of intelligent compute, and Semidynamics, a provider of fully customizable high-bandwidth and high-performance RISC-V processor IP, today announced a collaboration to boost innovation in development of hyper-efficient, next-generation platforms for artificial intelligence (AI), machine learning (ML) and high-performance computing (HPC) applications.

The collaboration integrates Semidynamics' family of 64-bit RISC-V processor IP cores, known for their exceptional memory bandwidth and configurability, with Baya Systems' innovative WeaveIP Network on Chip (NoC) system IP. WeaveIP is engineered for ultra-efficient, high-bandwidth, and low-latency data transport, crucial for the demands of modern workloads. Complementing this is Baya Systems' software-driven WeaverPro platform, which enables rapid system-level optimization, ensuring that key performance indicators (KPIs) are met based on real-world workloads while providing unparalleled design flexibility for future advancements.

We're happy to share that DeepComputing's DC-ROMA RISC-V Mainboard for Framework Laptop 13 is now in stock and shipping in the Framework Marketplace. This is very much a developer-focused board to help accelerate maturing the software ecosystem around RISC-V, so we recommend waiting for future RISC-V products if you're looking for a consumer-ready experience. We shared more detail on the Mainboard in an earlier blog post and video, but as a quick summary, this is powered by a StarFive JH7110 processor that uses the open source RISC-V ISA. The team at DeepComputing designed it to drop directly into a Framework Laptop 13 chassis or Cooler Master Mainboard Case. They have published setup guides for the hardware and for installing Ubuntu and Fedora.

To make it easier to jump into using a new partner-developed Mainboard or reusing an old one, we're also introducing the Framework Laptop 13 Shell today. This is a complete Framework Laptop 13 chassis with everything except for the Mainboard, memory, storage, and Wi-Fi. We're eager to continue making Framework products excellent platforms to extend on. Modularity and open source documentation is good for everyone!

Recently, SpacemiT, a RISC-V AI CPU company from China, announced breakthrough progress in the development of its server CPU chip SpacemiT Vital Stone V100. It now provides a complete RISC-V CPU chip hardware and software platform that fully supports server specifications.

RISC-V CPU core X100, AIA and APLIC supporting interrupt virtualization, IOMMU supporting memory virtualization, IOPMP supporting security functions, LPC and eSPI supporting communication with mainstream BMCs, etc.

• The 64-bit server-grade RISC-V CPU core X100 delivers a single-core performance of >9 points/GHz on SPECINT2006 at 2.5 GHz 12 nm. X100 supports the RVA23 Profile, full virtualization (Hypervisor 1.0, AIA 1.0, IOMMU), RAS features, Vector 1.0 extension, vector encryption and decryption, security, 64-core interconnect, and more.
• The IOMMU IP adheres to the RISC-V IOMMU architecture specification and the AXI4-Stream DTI interface, supporting configurable DID, PID, virtual address, physical address width, and various levels of translation cache sizes. It can be flexibly integrated into different locations within the SoC bus system to enable distributed peripheral virtualization and accelerator acceleration.

Axelera AI - a leading edge-inference company - and Arduino, the global leader in open-source hardware and software, today announced a strategic partnership to make high-performance AI at the edge more accessible than ever, building advanced technology solutions based on inference and an open ecosystem. This furthers Axelera AI's strategy to democratize artificial intelligence everywhere.

The collaboration will combine the strengths of Axelera AI's Metis AI Platform with the powerful SOMs from the Arduino Pro range to provide customers with easy-to-use hardware and software to innovate around AI. Users will enjoy the freedom to dictate their own AI journey, thanks to tools that provide unique digital in-memory computing and RISC-V controlled dataflow technology, delivering high performance and usability at a fraction of the cost and power of other solutions available today.

Santa Clara, CA: Tenstorrent is announcing that it has closed over $693M in its Series D funding round at a pre-money valuation of $2B. Samsung Securities and AFW Partners led the round, which was oversubscribed due to strong demand from investors. Samsung and AFW both have deep relationships with Tenstorrent, and a strong history of investing in pioneering technology companies.

In addition to the leads, many notable investors joined the round including XTX Markets, Corner Capital, MESH, Export Development Canada, Healthcare of Ontario Pension Plan, LG Electronics, Hyundai Motor Group, Fidelity, Baillie Gifford, Bezos Expeditions, and more.

For over half a century, general-purpose processors have been built on the Tomasulo algorithm, developed by IBM engineer Robert Tomasulo in 1967. It's a $500B industry built on specialized CPU, GPU and other chips for different computing tasks. Hardware startup Ubitium has shattered this paradigm with a breakthrough universal processor that handles all computing workloads on a single, efficient chip - unlocking simpler, smarter, and more cost-effective devices across industries - while revolutionizing a 57-year-old industry standard.

Alongside this, Ubitium is announcing a $3.7 million in seed funding round, co-led by Runa Capital, Inflection, and KBC Focus Fund. The investment will be used to develop the first prototypes and prepare initial development kits for customers, with the first chips planned for 2026.

LG Electronics (LG) and Tenstorrent are pleased to announce an expanded collaboration, building on their initial chiplet project to develop System-on-Chips (SoCs) and systems for the global market. Through this partnership, LG aims to enhance its design and development capabilities for AI chips tailored to its products and services, aligning with its vision of "Affectionate Intelligence." LG is dedicated to advancing AI-driven innovation, with a focus on enhancing its AI-powered home appliances and smart home solutions, as well as expanding its capabilities in future mobility and commercial applications.

Recognizing the critical role of high-performance AI semiconductors in implementing AI technology, LG plans to strengthen its in-house development capabilities while collaborating with leading global companies, including Tenstorrent, to boost its AI competitiveness.

RISC-V is an industry standard instruction set architecture (ISA) born in UC Berkeley. RISC-V is the fifth iteration in the lineage of historic RISC processors. The core value of the RISC-V ISA is the freedom of usage it offers. Any organization can leverage the ISA to design the best possible core for their specific needs, with no regional restrictions or licensing costs. It attracts a massive ecosystem of developers and companies building systems using the RISC-V ISA. To support these efforts and grow the ecosystem, the brains behind RISC decided to form RISC-V International—a non-profit foundation that governs the ISA and guides the ecosystem.

We had the privilege of talking with Andrea Gallo, Vice President of Technology at RISC-V International. Andrea oversees the technological advancement of RISC-V, collaborating with vendors and institutions to overcome challenges and expand its global presence. Andrea's career in technology spans several influential roles at major companies. Before joining RISC-V International, he worked at Linaro, where he pioneered Arm data center engineering initiatives, later overseeing diverse technological sectors as Vice President of Segment Groups, and ultimately managing crucial business development activities as executive Vice President. During his earlier tenure as a Fellow at ST-Ericsson, he focused on smartphone and application processor technology, and at STMicroelectronics he optimized hardware-software architectures and established international development teams.

During the 2024 RISC-V Summit in Santa Clara, California, NVIDIA was one of the presenting members. RISC-V, being a free and open-source instruction set architecture, is an interesting choice for many companies looking to develop custom solutions. NVIDIA designs accelerators for AI and graphics processing, all of which are equipped with up to tens of thousands of cores. To manage these cores, NVIDIA has developed a custom RISC-V processor called "NV-RISCV," which is a replacement for its predecessor "Falcon." Unlike Falcon, NV-RISCV is based on an open-source ISA and is customized much more deeply, with features like more customized caches and special instructions. Initially, the company reported better performance over its Falcon GPU System Processor (GSP), and NV-RISCV is now running in millions of NVIDIA chips.

Thanks to a post on X by Nick Brown, we learn that NVIDIA is shipping roughly one billion RISC-V cores in the year 2024. Each NVIDIA chip includes between 10 and 40 RISC-V cores, depending on the chip size and complexity. Some more complex designs, like GB200, require massive data coordination, meaning that more cores are needed to handle these requests and distribute them. This includes chip-to-chip interfaces, context switching, memory controller, camera handling, video codecs, display output, resource management, power management, and more. NVIDIA has developed a total of over 20 custom extensions for RISC-V cores, which all serve their specific use cases.

DeepComputing, a pioneer in RISC-V innovation, today announced a strategic partnership with Andes Technology Corporation, a leading provider of high-efficiency, low-power 32/64-bit RISC-V processor cores. Together, the two companies collaborate to develop the world's first RISC-V AI PC, powered by Andes' 7 nm QiLai SoC. This innovated low-power PC will come equipped with Ubuntu Desktop and aims to redefine AI computing by combining industry-leading hardware and software designed specifically for RISC-V.

The collaboration marks a significant milestone in the evolution of AI PCs, which utilize artificial intelligence to enhance productivity, creativity, entertainment, security, and more. The power-efficient RISC-V AI PC, based on the QiLai SoC, integrates a multi-core CPU, vector processor, GPU, and various peripherals for optimal performance, and AI workload handling. This product is designed to cater to developers and enterprises looking for advanced, open-standard RISC-V solutions.

RISC-V International, the global standards organization, today announced that the RVA23 Profile is now ratified. RVA Profiles align implementations of RISC-V 64-bit application processors that will run rich operating systems (OS) stacks from standard binary OS distributions. RVA Profiles are essential to software portability across many hardware implementations and help to avoid vendor lock-in. The newly ratified RVA23 Profile is a major release for the RISC-V software ecosystem and will help accelerate widespread implementation among toolchains and operating systems.

As the steward of the RISC-V standard, RISC-V has more than 80 technical working groups that collectively advance the capabilities of the RISC-V ISA. RISC-V addresses the need for portability across vendors with standard ISA Profiles for applications and systems software. Each Profile specifies which ISA features are mandatory or optional, providing a common target for software developers. Mandatory extensions can be assumed to be present, and optional extensions can be discovered at runtime and leveraged by optimized middleware, libraries, and applications. To be ratified, the RVA23 Profile underwent a lengthy development, review, and approval process across numerous working groups, before receiving the final ratification vote by the RISC-V Board of Directors.

SiFive, Inc., the gold standard for RISC-V computing, today announced the availability of its state-of-the-art HiFive Premier P550 development board. An initial pre-release batch of 100 Yocto Linux-based boards, called the "Early Access Edition," is available for purchase through Arrow Electronics. A broader release with Canonical Ubuntu 24.04 pre-installed is scheduled for December, providing developers with an unparalleled out-of-box experience.

"Since announcing the HiFive Premier P550 boards in April, we've worked closely with Canonical to deliver a best-in-class hardware and software experience," said Martyn Stroeve, Head of the HiFive board program at SiFive. "We know many developers are eager to get their hands on this powerful new board, so we decided to release a limited Early Access Edition. At the same time, we are finalizing the software stack for the December release, which we believe will deliver powerful performance and usability for developers. We're excited to see the innovation and creativity that will come from this."

AVX-512 was proposed by Intel more than a decade ago—in 2013 to be precise. A decade later, the implementation of this instruction set on CPU cores remains wildly spotty—Intel implemented it first on an HPC accelerator, then its Xeon server processors, then its client processors, before realizing that hardware hasn't caught up with the technology to execute AVX-512 instructions in an energy-efficient manner, before deprecating it on the client. AMD implemented it just a couple of years ago with Zen 4 with a dual-pumped 256-bit FPU on 5 nm, before finally implementing a true 512-bit FPU on 4 nm. AVX-512 is a microcosm of what's wrong with the x86 ecosystem.

There are only two x86 CPU core vendors, the IP owner Intel, and its only surviving licensee capable of contemporary CPU cores, AMD. Any new additions to the ISA introduced by either of the two have to go through the grind of their duopolistic competition before software vendors could assume that there's a uniform install base to implement something new. x86 is a net-loser of this, and Arm is a net-winner. Arm Holdings makes no hardware of its own, except continuously developing the Arm machine architecture, and a first-party set of reference-design CPU cores that any licensee can implement. Arm's great march began with tiny embedded devices, before its explosion into client computing with smartphone SoCs. There are now Arm-based server processors, and the architecture is making inroads to the last market that x86 holds sway over—the PC. Apple's M-series processors compete with all segments of PC processors—right from the 7 W class, to the HEDT/workstation class. Qualcomm entered this space with its Snapdragon Elite family, and now Dell believes NVIDIA will take a swing at client processors in 2025. Then there's RISC-V. Intel finally did something it should have done two decades ago—set up a multi-brand Ecosystem Advisory Group. Here's what it is, and more importantly, what it's not.

Altera, an Intel Company, today unveiled an array of FPGA hardware, software and development tools that make its programmable solutions more accessible across a broader range of use cases and markets. At its annual developer's conference, Altera revealed new details on its next-generation, power- and cost-optimized Agilex 3 FPGAs and announced new development kits and software support for its Agilex 5 FPGAs.

"Working closely with our ecosystem and distribution partners, Altera remains committed to delivering FPGA-based solutions that empower innovators with leading-edge programmable technologies that are easy to design and deploy. With these key announcements, we continue to execute on our vision of shaping the future by using programmable logic to help customers unlock greater value across a broad range of use cases within the data center, aerospace and defense sectors, communications infrastructure, automotive, industrial, test, medical and embedded markets," said Sandra Rivera, CEO of Altera.

Microsoft's Direct3D and HLSL teams have unveiled plans to integrate SPIR-V support into DirectX 12 with the upcoming release of Shader Model 7. This significant transition marks a new era in GPU programmability, as it aims to unify the intermediate representation for graphical-shader stages and compute kernels. SPIR-V, an open standard intermediate representation for graphics and compute shaders, will replace the proprietary DirectX Intermediate Language (DXIL) as the shader interchange format for DirectX 12. The adoption of SPIR-V is expected to ease development processes across multiple GPU runtime environments. By embracing this open standard, Microsoft aims to enhance HLSL's position as the premier language for compiling graphics and compute shaders across various devices and APIs. This transition is part of a multi-year development process, during which Microsoft will work closely with The Khronos Group and the LLVM Project. The company has joined Khronos' SPIR and Vulkan working groups to ensure smooth collaboration and rapid feature adoption.

While the transition will take several years, Microsoft is providing early notice to allow developers and partners to plan accordingly. The company will offer translation tools between SPIR-V and DXIL to facilitate a gradual transition for both application and driver developers. For those not familiar with graphics development, graphics APIs ship with virtual instruction set architectures (ISA) that abstracts standard hardware features at a higher level. As GPUs don't follow the same ISA as CPUs (x86, Arm, RISC-V), this virtual ISA is needed to define some generics in the GPU architecture and allow various APIs like DirectX and Vulkan to run. Instead of focusing support on several formats like DXIL, Microsoft is embracing the open SPIR-V standard, which will become de facto for API developers in the future, allowing focus on more features instead of constantly replicating each other's functions. While DXIL is used mainly for gaming environments, SPIR-V has adoption in high-performance computing as well, with OpenCL and SYCL. Gaming presence is also there with Vulkan API, and we expect to see SPIR-V join DirectX 12 games.

In a notable step forward for the RISC-V architecture, the Box86 and Box64 emulator developers have successfully run The Witcher 3 on a RISC-V processor. While performance is far from optimal, even on a Milk-V Pioneer with a 64-core processor and an AMD Radeon RX 5500 XT graphics card, the achievement is remarkable.

RISC-V, a free and open-source instruction set architecture, is still in its early stages compared to established platforms like ARM and x86/x64. Despite this, the Box86/Box64 team, known for creating environments to run Windows programs on Linux, has demonstrated that AAA gaming is possible on RISC-V hardware. To accomplish this feat, the developers utilized Box64 with Wine and DXVK to emulate the necessary instructions.

Today SiFive, Inc., the gold standard for RISC-V computing, announced its new SiFive Performance P870-D datacenter processor to meet customer requirements for highly parallelizable infrastructure workloads including video streaming, storage, and web appliances. When used in combination with products from the SiFive Intelligence product family, datacenter architects can also build an extremely high-performance, energy efficient compute subsystem for AI-powered applications.

Building on the success of the P870, the P870-D supports the open AMBA CHI protocol so customers have more flexibility to scale the number of clusters. This scalability allows customers to boost performance while minimizing power consumption. By harnessing a standard CHI bus, the P870-D enables SiFive's customers to scale up to 256 cores while harnessing industry-standard protocols, including Compute Express Link (CXL) and CHI chip to chip (C2C), to enable coherent high core count heterogeneous SoCs and chiplet configurations.

Akeana, the company committed to driving dramatic change in semiconductor IP innovation and performance, has announced its official company launch approximately three years after its foundation, having raised over $100 million in capital, with support from A-list investors including Kleiner Perkins, Mayfield, and Fidelity. Today's launch marks the formal availability of the company's expansive line of IP solutions that are uniquely customizable for any workload or application.

Formed by the same team that designed Marvell's ThunderX2 server chips, Akeana offers a variety of IP solutions, including microcontrollers, Android clusters, AI vector cores and subsystems, and compute clusters for networking and data centers. Akeana moves the industry beyond the status quo of legacy vendors and architectures, like Arm, with equitable licensing options and processors that fill and exceed current performance gaps.

DeepComputing partners with Canonical to unveil a huge boost to the DC-ROMA RISC-V Laptop family. The DC-ROMA RISC-V Laptop II is the world's first RISC-V laptop pre-installed and powered by Ubuntu, which is one of the most popular Linux distributions in the world, providing developers with an outstanding mix of usability and reliability, as well as a rich ecosystem with security and support.

Equipped with octa-core 64-bit RISC-V AI CPU
Adding to a long list of firsts, the new DC-ROMA laptop II is the first to feature SpacemiT's SoC K1 - with its 8-cores RISC-V CPU running at up to 2.0 GHz with 16 GB of memory. This significantly doubled its overall performance and energy efficiency over the previous generation's 4-cores SoC running at 1.5 GHz. Moreover, SpacemiT's SoC K1 is also the world's first SoC to support RISC-V high performance computing RVA 22 Profile RVV 1.0 with 256 bit width, and to have powerful AI capabilities with its customised matrix operation instruction based on IME Group design principle!

MIPS, a leading developer of efficient and configurable IP compute cores, will showcase the company's latest innovations and suite of system deployments at Computex 2024. As part of its activities at Computex 2024, MIPS will highlight its latest solutions demonstrating the company's differentiation around data movement to enable customers to achieve Edge AI innovation. MIPS' architecture enables a bespoke solution with tight integration of the CPU to the overall System-on-Chip (SoC) architecture, managing data movement and memory balancing to predict and solve bottlenecks caused by the increasing throughput demands of new use-cases in AI.

"We are excited to participate in Computex 2024 where we will show how we've evolved as a company and are developing RISC-V tools that give edge AI Embedded customers the freedom to innovate compute," said Durgesh Srivastava, CTO of MIPS. "We remain committed to providing our customers and partners with the innovative solutions they need to succeed in today's rapidly evolving accelerated computing markets. We are anticipating a lot of interest in our technology at the show and look forward to connecting with ecosystem partners, our customers and fellow industry leaders."