Thursday, July 10th 2025
AMD Sampling Next-Gen Ryzen Desktop "Medusa Ridge," Sees Incremental IPC Upgrade, New cIOD
AMD is reportedly sampling its next-generation Ryzen desktop processor powered by the "Zen 6" microarchitecture, codenamed "Medusa Ridge," to close industry partners, such as platform designers and OEMs, says Yuri Bubliy, aka 1usmus, author of the Hydra tuning software, and the now-retired DRAM Calculator for Ryzen. The processor sees AMD update both the CCDs and client I/O die, he says. AMD confirmed that it is building the "Zen 6" CCD on the TSMC N2 (2 nm) node, which entered risk production earlier this year. The node is expected to be ready for mass-production of 2 nm chips later this year. The 2 nm node presents a significant jump in transistor densities from the current TSMC N4P node on which AMD builds its 8-core "Zen 5" CCD, which 1usmus and other sources say, that AMD will use to increase CPU core counts per CCD.
Sources point to the possibility of AMD increasing core counts per CCD to 12, and giving the CCD 48 MB of L3 cache. At this point we don't know if all 12 cores will be arranged in a single CCX with a monolithic slab of 48 MB L3 cache, or if there's a dual-CCX layout with 6 cores per CCX sharing 24 MB of L3 cache, each. The other big upgrade with "Medusa Ridge" is its client I/O die (cIOD). AMD is expected to build its new generation cIOD on a newer EUV node such as 5 nm N5 or 4 nm N4P, a significant upgrade from the current 6 nm N6. 1usmus says that the biggest reason for AMD to update its cIOD is the memory controller architecture. AMD is expected to give "Medusa Point" a new dual memory controller architecture. There are still two DDR5 channels per socket, but this is redesigned for increased memory speeds, letting AMD catch up with Intel in this area. As for the CPU frequency boosting technologies, such as PBO and Curve Optimizer, there are no updates expected, and 1usmus concludes that it Hydra support should be straightforward.
Source:
Wccftech
Sources point to the possibility of AMD increasing core counts per CCD to 12, and giving the CCD 48 MB of L3 cache. At this point we don't know if all 12 cores will be arranged in a single CCX with a monolithic slab of 48 MB L3 cache, or if there's a dual-CCX layout with 6 cores per CCX sharing 24 MB of L3 cache, each. The other big upgrade with "Medusa Ridge" is its client I/O die (cIOD). AMD is expected to build its new generation cIOD on a newer EUV node such as 5 nm N5 or 4 nm N4P, a significant upgrade from the current 6 nm N6. 1usmus says that the biggest reason for AMD to update its cIOD is the memory controller architecture. AMD is expected to give "Medusa Point" a new dual memory controller architecture. There are still two DDR5 channels per socket, but this is redesigned for increased memory speeds, letting AMD catch up with Intel in this area. As for the CPU frequency boosting technologies, such as PBO and Curve Optimizer, there are no updates expected, and 1usmus concludes that it Hydra support should be straightforward.
97 Comments on AMD Sampling Next-Gen Ryzen Desktop "Medusa Ridge," Sees Incremental IPC Upgrade, New cIOD
Bonus X3D get 96mb +48mb for 144mb total L3 this is 50% more than 9800X3D
I hope for the 12-core single CCX CPU though, to replace my aging 8 core 3700X.
Desktop apps need CPUs with high IPC per core, not CPUs with dozens of weak cores.
Also, please learn what an E core is, and what a ryzen C core is. These are not the same thing.CAMM2 modules are having the same signal integrity issues that DIMM modules have trying to push past 6000 mhz.It'd be a lot easier to simply put a x3d cache on their APUs instead of another memory controller. Not to mention that a triple bus system is going to be significantly more expensive for the end consumer than a dual pus system like we have now.
What dual memory controller architecture mean? Support two diffirent memory types? Which? I remember that AMD said that current 9800X3D don't supprt CKD memory and it can't be added without redisign.
Tell us what desktop applications need dozens of cores other than video encoding by the CPU?
As per the explanation, i suspect this will allow each memory controller to be smaller so the signal will have less area/distance to propagate, allowing higher frequency. This could also help with signal integrity.
The goal would be to support higher DDR5 clock allowing more bandwidth.
I have a hard time believing this will be all there is to zen 6
Finally
IntelAMD is increasing core counts.A lot but it doesn't matter, dozens of cores on the desktop mean that the half a dozen core CPU would be cheaper (although this is amd we are talking about, they might as well keep charging you 400$ for 8 cores).