Shipping manifests have served as fairly reliable sources of pre-launch information—Everest (aka Olrak29) has discovered many juicy details in recent times. Their latest sleuthing session—combing through NBD documents—has indicated AMD's (alleged) prepping of a larger socket design for next-generation mobile processors. A leaked document alludes to the existence of various "MEDUSA01" jig and block "FP10" socket validation parts. Current-generation Ryzen AI "Strix Point" 300 series APUs utilize the FP8 socket format. Based on the "MEDUSA01" shipping manifest, it seems that a successor will arrive with a larger footprint—measurements of 25 mm x 42.5 mm are repeated throughout the leaked description list. Industry watchdogs surmise that "Medusa Point's" BGA FP10 socket will be approximately 6% larger than its predecessor.

Mid-way through last month, insider theorizations pointed to "Medusa Point" being a chiplet-based design. A "single 12-core Zen 6 CCD" was linked to a TSMC 3 nm-class node, with "N4P" reportedly selected for a separate mobile client I/O die. Readily available 4 nm Ryzen AI "Strix Point" processors are monolithic in nature. Initial inside track info mentioned RDNA 4 technology in the same equation as "Medusa Point," but recent Team Red's recent-ish targeting of "GFX1153" places RDNA 3.5 as the de facto choice.

At the tail end of 2024, AMD technical staffers added the "GFX1153" target to their first-party GPU supported chip list. Almost three months later, PC hardware news outlets and online enthusiasts have just picked up on this development. "GFX1150" family IPs were previously linked to Team Red's RDNA 3.5 architecture. This graphics technology debuted with the launch of Ryzen AI "Strix Halo," "Strix Point" and "Krackan Point" mobile processors. Recent leaks have suggested that Team Red is satisfied with the performance of RDNA 3.5-based Radeon iGPUs; warranting a rumored repeat rollout with next-gen "Medusa Point" APU designs.

Both "Medusa Point" and "Gorgon Point" mobile CPU families are expected to launch next year, with leaks pointing to the utilization of "Zen 6" and "Zen 5" processor cores (respectively) and RDNA 3.5 graphics architecture. RDNA 4 seems to be a strictly desktop-oriented generation. AMD could be reserving the "further out" UDNA tech for truly next-generation integrated graphics solutions. In the interim, Team Red's "GFX1153" IP will likely serve as "Medusa Point's" onboard GPU, according to the latest logical theories. Last year, the "GFX1152" target was associated with Ryzen AI 7 300-series "Krackan Point" APUs.

AMD's next-generation Zen 6-based "Medusa Point" mobile APUs will not feature RDNA 4 graphics as previously speculated, according to recent code discoveries in AMD GPUOpen Drivers on GitHub. The Device ID "GfxIp12" associated with RDNA 4 architecture has been reserved only for discrete GPUs, confirming that the current Radeon RX 9000 series will exclusively implement AMD's latest graphics architecture. Current technical documentation indicates AMD will instead extend RDNA 3.5 implementation beyond the Zen 5 portfolio while potentially positioning UDNA as the successor technology for integrated graphics.

The chiplet-based Medusa Point design will reportedly pair a single 12-core Zen 6 CCD manufactured on TSMC's 3 nm-class node with a mobile client I/O die likely built on N4P. This arrangement is significantly different from current monolithic mobile solutions. Earlier speculation indicates the Medusa Point platform may support 3D V-Cache variants, leveraging the same vertical stacking methodology employed in current Zen 5 implementations. The mobile processor's memory controllers and neural processing unit are expected to receive substantial updates. However, compatibility limitations with AMD's latest graphics features, like FSR 4 technology, remain a concern due to the absence of RDNA 4 silicon. The Zen 6-powered Medusa Point processor family is scheduled for release in 2026, targeting premium mobile computing applications with a performance profile that builds upon AMD's current Strix Halo positioning.

The "Medusa" or "Medusa Point" codename started to appear online over the past couple of months. These mysterious AMD projects were linked to next-generation "Zen 6" Ryzen desktop and mobile processor families (respectively). Initially, insiders reckoned that Team Red had selected an RDNA 4-based graphics solution for integration their futuristic new-gen laptop APU design. Two days ago, Golden Pig Upgrade weighed in with a different theory—the veteran leaker believes that provisions have regressed on the "Medusa Point" iGPU front.

Previous reports have suggested that the "Medusa Point" processor's iGPU aspect will utilize up to 16 compute units (CU), based on a theorized count of eight workgroup processors (WGPs) from leaked imagery. The latest insider tip points to the utilization of a non-specific "RDNA 3.x" branch, instead of conjectured RDNA 4 graphics technology. Industry watchdogs hold the belief that AMD will be sticking with RDNA 3.5 for a while—as featured on their current-gen "Zen 5" mobile-oriented Strix Point, Strix Halo and Krackan Point chips. As pointed out by Notebookcheck, Team Red leadership disclosed that RDNA 4 is exclusive to discrete card families (for the time being). RDNA 3.5-equipped APUs have—so far—received a warm welcome; AMD engineers could be reserving development resources for a distant future project.

AMD is readying two important client segment processors powered by the next-generation "Zen 6" microarchitecture, according to a sensational new report by Moore's Law is Dead. These are the "Medusa Point" mobile processor, and the "Olympic Ridge" desktop. The former is a BGA roughly the size and Z-Height of the current "Strix Point," but the latter is being designed for the existing Socket AM5, making it the third (and probably final) microarchitecture to do so. If you recall, Socket AM4 served three generations of Zen, not counting the refreshed "Zen+." At the heart of the effort is a new CPU complex die (CCD) that AMD plans to use across its client and server lineup.

The "Zen 6" performance CCD is being designed for a 3 nm-class node, likely the TSMC N3E. This node promises a significant increase in transistor density, power, and clock speed improvements over the current TSMC N4P node being used to build the "Zen 5" CCD. Here's where it gets interesting. The CCD contains twelve full-sized "Zen 6" cores, marking the first increase in core-counts of AMD's performance cores since its very first "Zen" CCD. All 12 of these cores are part of a single CPU core complex (CCX), and share a common L3 cache. There could be a proportionate increase in cache size to 48 MB. AMD is also expected to improve the way the CCDs communicate with the I/O die and among each other.