Over the past weekend Jukanlosreve declared via social media that Samsung's: "Exynos 2600 (mobile SoC) is definitely back, and it will be used in the Galaxy S26 series. But the chip volume is so limited that it'll likely be similar to the Exynos 990 situation. I'm not sure if SF2 is actually any good." Mid-way through March, the keen observer of semiconductor industry conditions posited that Samsung's Foundry business could abandon a 1.4 nm (SF1.4) process node. SF2 (aka 2 nm GAA) seems to be in a healthier place, according to insiders—thanks to rumored assistance from an external AI-specialist partner. The development of next-generation flagship Exynos smartphone processors are allegedly closely tied with Samsung Foundry's 2 nm GAA manufacturing process.

As alluded to by Jukanlosreve's recent prediction, the statuses of leaked 2 nm-based "Exynos 2600" and "Exynos 2500" chips were often questioned by industry watchdogs in the past. The latter is purportedly destined for rollout in forthcoming affordable "Galaxy Z Flip FE" models, albeit in mature 4 nm form. Vhsss_God—another source of inside track info—has weighed in on the topic of Samsung's next-gen chipset roadmap. Compared to Jukanlosreve's musings, their similarly-timed weekend projection seemed to be quite fanciful: "exclusive leak...Samsung doesn't want to use Exynos or Qualcomm Snapdragon chips anymore. S26 line is targeted to launch with the new Samsung developed chip (2 nm)—formerly referred to as Exynos 2600. (The company) will try its hardest to ditch Snapdragon on the entire Galaxy line next year." Perhaps there is too much of a negative stigma attached to Samsung's long-running chipset nomenclature, but the majority of foundry moles continue to label incoming designs as Exynos processors.

Rapidus Corporation today announced that its plans and budget for fiscal year 2025 have been approved by Japan's New Energy and Industrial Technology Development Organization (NEDO). The approval covers two commissioned projects under NEDO's "Post-5G Information and Communication Systems Infrastructure Enhancement R&D Project / Development of Advanced Semiconductor Manufacturing Technology (Commissioned)." These projects are the "Research and Development of 2 nm-Generation Semiconductor Integration Technology and short TAT (turnaround time) Manufacturing Technology Based on Japan-U.S. Collaboration" and "Development of Chiplet, Package Design and Manufacturing Technology for 2 nm-Generation Semiconductors."

The first of these projects, focused on front-end processes, was launched in November 2022 as part of Japan's next-generation semiconductor R&D effort. Under this program, Rapidus has continued construction of the Innovative Integration for Manufacturing (IIM) facility in Chitose, Hokkaido, which will serve as its production base. It also sent engineers to IBM in the U.S. to jointly develop 2 nm logic semiconductor mass production technologies and continued to achieve target performance as planned. Furthermore, Rapidus has installed EUV lithography and other production equipment at the IIM facility, and started cleanroom operation. As a result of these efforts, the company achieved its performance targets for FY2024.

Going back to the start of this year, TSMC's trial run of a cutting-edge 2 nm (N2) node process was reportedly progressing beyond initial expectations. According to industry moles, two flagship fabrication facilities are "optimistically" tipped to pump out 80,000 units per month (by the end of 2025). This cross-facility total figure was linked to TSMC's Baoshan—located near the Northern Taiwanese city of Hsinchu—and Kaohsiung (in the South) plants. The latest regional reports suggest that the aforementioned trial phase was a resounding success, with pleasing results pointing to an "ahead of schedule" transfer to mass production phases. Insiders previously heard about the Kaohsiung production hub's schedule; with mass production set to start by early 2026—according to fresh rumors, revised calendars have a kick-off window repositioned somewhere in late 2025. Apparently a special "2 nm plant expansion ceremony" took place in that location, earlier today.

A noted semiconductor business analyst—Ming-Chi Kuo—reckons that recent 2 nm pilot yields have progressed well over the 60% mark, meaning that the involved foundry teams are more than ready to move onto kicking things into high gear. Taiwan's Economic News Daily anticipates significant financial gains, due to TSMC N2 products already being in high demand: "the quarterly revenue in the second half of the year is expected to reach one trillion yuan (~US$30.1 billion) for the first time, and it is poised to challenge the goal of earning twice the share capital in a quarter and rewrite the record for a single quarter." The local publication claims that TSMC Baoshan's "first batch of production capacity" is fully reserved for Apple, while Kaohsiung will take care of orders for other (i.e. less) important customers.

Rapidus Corporation, a manufacturer of advanced logic semiconductors, today announced that it signed a Memorandum of Cooperation with Quest Global Services PTE. Ltd. As part of the agreement, Rapidus will become Quest Global's new semiconductor foundry partner, enabling it to provide a wide range of solutions to its customers. Quest Global customers will be able to leverage Rapidus' 2 nm gate-all-around (GAA) manufacturing process to develop engineering design and manufacturing solutions that will support growing industry demand for low-power artificial intelligence (AI) semiconductors. Together, the two companies will deliver transformational silicon solutions as a virtual integrated device manufacturer (IDM) model for fabless companies.

The AI semiconductor industry is in its early stages, with applications just beginning to emerge and new entrants quickly coming to market. Customers will shift from general-purpose AI semiconductors to dedicated designs that reduce power consumption and maximize performance. To support these industry requirements, customers will engage design firms focused on providing custom solutions, such as Quest Global, while also collaborating with semiconductor foundries, like Rapidus, that can manufacture dedicated semiconductors with a short turnaround time.

Earlier in the week, Apple specialist press outlets picked up on a noted industry analyst's technological forecast for a future iPhone processor design. Jeff Pu—of GF Industries, Hong Kong—predicted that the next-generation A20 SoC would be produced via a TSMC 3 nm (N3P) nodes process. Despite rumors of Apple gaining front row seats at the "2 nm ballgame," the partnership between fabless chip designer and foundry could potentially revisit already covered ground. The A19 chipset was previously linked to N3P (by insiders), with Pu expressing the belief that A20 would utilize the same fundamental lithographic underpinnings; albeit enhanced with TSMC's Chip on Wafer on Substrate (CoWoS) packaging technology (for AI improvements).

This morning, MacRumors followed up on their initial news article—they reported that "wires were crossed" at GF Industries, regarding projections for the (2026) iPhone 18 generation. The publication received direct feedback from the man of the hour: "Jeff Pu (lead Apple analyst) has since clarified that he believes the A20 chip will be manufactured with the N2 process, so the information about the chip using the N3P process should be disregarded. Earlier reports had said the A20 chip would be 2 nm, so rumors align again. This is ultimately good news, as it means the A20 chip should have more substantial performance and power efficiency improvements over the A19 chip." Cutting-edge smartphone processor enthusiasts expressed much disappointment when A20 was (regressively) linked to N3P; the latest revisement should instill some joy. According to industry moles, TSMC is making good progress with its cutting-edge 2 nm node process—mass production is expected to start at some point within the second half of 2025.

Over a year ago, industry watchdogs posited that Apple was patiently waiting in line at the front of TSMC's 2 Nanometer GAA "VVIP queue." The securing of cutting-edge manufacturing processes seems to be a consistent priority for the Cupertino, California-headquartered fabless chip designer. Current generation Apple chipsets—at best—utilize TSMC 3 nm (N3E) wafers. Up until very recently, many insiders believed that the projected late 2026 launch of A20 SoC-powered iPhone 18 smartphones would signal a transition to the Taiwanese foundry's advanced 2 nm (N2) node process. Officially, TSMC has roadmapped the start of 2 nm mass production around the second half of 2025.

According to Jeff Pu—a Hong Kong-based analyst at GF Securities—the speculated A20 (2026) chipset could stick with N3P. Leaks suggest that aspects of Apple's next in line "A19" and "A19 Pro" mobile SoCs could be produced via a 3 nm TSMC process. MacRumors has picked up on additional inside track whispers; about Apple M5 processors (for next-gen iPad Pro models) being based on N3P—"likely due to increased wafer costs." Pu reckons that Apple's engineering team has provisioned a major generational improvement with A20's AI capabilities, courtesy of TSMC's Chip on Wafer on Substrate (CoWoS) packaging technology. This significant upgrade is touted to tighten integration between the chip's processor, unified memory, and Neural Engine segments. Revised insider forecasts have positioned A21 chip designs as natural candidates for a shift into 2 nm GAA territories.

According to The Korea Economic Daily, an unlikely alliance—involving Samsung Electronics and Palantir Technologies—was formed at the end of last year. Late last week, insiders posited that the South Korean megacorporation's Foundry business was going through troubled times. It is not clear whether the assistance provided by Palantir's AI-infused suite has produced pleasing results chez Samsung's flagship production hubs, but insiders reckon that utilization of the software started just before Christmas. Local media outlets view this unusual pairing as a "gamble"—reportedly, the new-ish initiative has targeted an improved "semiconductor yield (ratio of good products in total production), quality, and productivity."

The Samsung Foundry appears to be going "all-in" with its 2 nm GAA node process; industry moles picked up on signals transmitted by an alleged special "task force (TF)." This elite team is reportedly entrusted with a challenging two-pronged goal; get 2 nm GAA over the finish line by late 2025, alongside the (connected) finalization of a much-rumored "Exynos 2600" mobile chipset. The Korea Economic Daily news article mentions the expansion of a "Samsung DS Division AI Center" back in December (2025), but falls short of labelling this department as the aforementioned "special task force." Despite a previous reluctance to share sensitive data with external companies, the latest report suggests a significant change in strategy. Further details were disclosed: "(Samsung's) collaboration with Palantir is handled by the DS Division AI Center...The AI Center is an organization that merged the DS Division Innovation Center and SAIT (formerly Samsung Advanced Institute of Technology) AI Center, and is developing DS Division-specific technologies using AI, advancing development software, building AI platforms, and controlling and advancing facilities and infrastructure." Around late February, industry inside trackers predicted continued "smooth" progress with the 2 nm GAA node. Samsung Foundry's fully upgraded "S2" mass production line is expected to come online by Q4 2025.

Late last month, industry insiders posited that pleasing progress was being made with Samsung's cutting-edge 2 nm Gate-All-Around (GAA) node process. The rumored abandonment of an older 3 nm GAA-based project—in late 2024—has likely sent the South Korean foundry team into overdrive. A speculated Exynos 2500 flagship mobile processor was previously linked to said 3 nm node, but industry watchdogs believe that company engineers are experimenting with a 2 nm GAA manufacturing process. According to the latest insider report—from FN News SK—Samsung Foundry (SF) has assembled a special "task force (TF)." Allegedly, this elite team will be dedicated to getting a newer "Exynos 2600 chip" over the finish line—suggesting an abandonment of the older "2500" design, or a simple renaming.

Samsung's recent launch of Galaxy S25 series smartphones was reportedly viewed as a disappointing compromise—with all models being powered by Qualcomm's "first-of-its-kind customized Snapdragon 8 Elite Mobile Platform," instead of in-house devised chipsets. According to industry moles, one of the SF task force's main goals is a boosting of 2 nm GAA production yields up to "economically viable" levels (roughly 60-70%)—apparently last month's best result was ~30%. Mass production of prototype chipsets is tipped to start by May. Samsung's reported target of "stabilizing their Exynos 2600" SoC design will ensure that "Galaxy S26 series" devices will not become reliant on Qualcomm internals. Additionally, FN News proposes a bigger picture scenario: "the stabilization of 2 nm (SF2/GAA) products, is expected to speed up the acquisition of customers for Samsung Electronics' foundry division, which is thirsty for leading-edge process customers." A forthcoming rival next-gen mobile chip—Snapdragon 8 Elite Gen 2—is supposedly in the pipeline. The smartphone industry inside track reckons that Qualcomm has signed up with TSMC; with a 2 nm manufacturing process in mind.

ASML Holding N.V. (ASML) and imec, a leading research and innovation hub in nanoelectronics and digital technologies, today announce that they have signed a new strategic partnership agreement, focusing on research and sustainability. The agreement has a duration of five years and aims to deliver valuable solutions in two areas by bringing together ASML's and imec's respective knowledge and expertise. First, to develop solutions that advance the semiconductor industry and second, to develop initiatives focused on sustainable innovation.

The collaboration incorporates ASML's whole product portfolio, with a focus on developing high-end nodes, using ASML systems including 0.55 NA EUV, 0.33 NA EUV, DUV immersion, YieldStar optical metrology and HMI single- and multi-beam technologies. These tools will be installed in imec's state-of-the-art pilot line and incorporated in the EU- and Flemish-funded NanoIC pilot line, providing the most advanced infrastructure for sub-2 nm R&D to the international semiconductor ecosystem. Focus areas for R&D will also include silicon photonics, memory and advanced packaging, offering full stack innovation for future semiconductor-based AI applications in diverse markets.

Marvell Technology, Inc., a leader in data infrastructure semiconductor solutions, has demonstrated its first 2 nm silicon IP for next-generation AI and cloud infrastructure. Produced on TSMC's 2 nm process, the working silicon is part of the Marvell platform for developing custom XPUs, switches and other technology to help cloud service providers elevate the performance, efficiency, and economic potential of their worldwide operations.

Given a projected 45% TAM growth annually, custom silicon is expected to account for approximately 25% of the market for accelerated compute by 20281.

Samsung's foundry operation has experienced many setbacks over the past six months, according to a steady feed of insider reports. Last November, industry moles leaked details of an apparent abandonment of the company's 3 nm Gate-All-Around (GAA) process. Significant yield problems prompted an alleged shift into 2 nm territories, with a next-gen flagship Exynos mobile processor linked to this cutting-edge node. According to a mid-week Chosun Daily article, Samsung and its main rival—TSMC—are in a race to establish decent yields of 2 nm wafers, ahead of predicted "late 2025" mass production kick-offs. The publication's inside track points to the Taiwanese foundry making the most progress (with an estimated 60%), but watchdogs warn that it is too early to bet against the South Korean competitor.

Despite murmurs of current 20 - 30% yields, the Samsung's Hwaseong facility is touted to make "smooth" progress over the coming months. Chosun's sources believe that Samsung engineers struggled to get 3 nm GAA "up to snuff," spending around three years on development endeavors (in vain). In comparison, the making of 2 nm GAA is reported to be less bumpy. A fully upgraded "S3" foundry line is expected to come online by the fourth quarter of this year. An unnamed insider commented on rumors of better than anticipated forward motion chez Samsung Electronics: "there are positive aspects to this as it has shown technological improvements, such as the recent increase in the yield of its 4 nm process by up to 80%." Recent-ish reports suggest that foundry teams have dealt with budget cuts, as well as mounting pressure from company leadership to hit deadlines.

Earlier in the year, we heard about TSMC being ahead of the game with its speculated trial production run of cutting-edge 2 nm (N2) silicon. Taiwan's premier foundry company is reportedly prepping its Baoshan and Kaohsiung plants for full-on manufacturing of next-gen chips. The latest insider whispers propose that TSMC is making "rapid" progress on the 2 nm (N2) front, as company engineers have moved onto an "intensive" trial production phase. Taiwan's Economic Daily News has picked up on compelling projections from industry moles; the Hsinchu Baoshan facility's current monthly production capacity is (allegedly) around 5000 to 10,000 2 nm wafers. The other 2 nm-specialist site—Kaohsiung—has reportedly moved into a small-scale appraisal phase.

TSMC declined to comment on recently leaked data points, but they released a general statement (to UDN), emphasizing that: "(our) 2 nm process technology is progressing well and will go into mass production as scheduled in the second half of this year." The Baoshan plant could ramp up to 25,000 2 nm wafers per month, once it moves into a mass production phase. Combined with the same estimated output from its sister site (Kaohsiung), insiders reckon that the combined total could reach 50,000 units per month. Following a predicted successful "second phase" transition, TSMC's most advanced facilities have a "chance" to pump out 80,000 2 nm parts (combined total). The latest murmurs suggest that this milestone could be achieved by the end of 2025. Industry watchdogs believe that Apple will have first access dibs on TSMC's upcoming cutting-edge offerings.

The late 2024 news cycle suggested that Samsung's semiconductor business was going through tough times. Alleged yield problems—affecting the 3 nm Gate-All-Around (GAA) process—were highlighted last November. Fast-forward to January 2025; the South Korean megacorp has launched its cutting-edge Galaxy S25 smartphone series. The entire lineup of newly unveiled flagship smartphones contains Qualcomm's Snapdragon 8 Elite mobile chipsets; the Southern Californian chip designer is reportedly pulling in a tidy sum from this partnership. Fresh reports from South Korean news outlets indicate that Samsung System LSI employees have received an "encouraging" email from their boss, regarding current production predicaments.

Businesskorea and Sedaily reports include quotes extracted from the (apparently) leaked internal memo. LSI division president, Park Yong-in, reportedly stated: "we are currently in a situation where we have to develop two flagship products at the same time." Both articles allege that Samsung's semiconductor teams are expected to "cultivate roots and withstand storms." Industry watchdogs believe that the aforementioned "flagship products" are the Exynos 2500 mobile chipset, and Samsung Electronic's next-gen Galaxy S26 smartphone family. Earlier this month, we heard whispers about the much-delayed in-house chip design being readied (with a 2 nm process) for a possible late 2025 launch, inside unannounced Galaxy Z Flip 7 and Fold 7 devices. Park disclosed anticipated incoming obstacles in 2025: "last year's business division profit was higher than expected, but this was a temporary phenomenon...Looking at the entire business division, there will be monthly surpluses and deficits." Last month, inside sources proposed the notion that foundry investments were slashed in half.

TSMC has unveiled today its board meeting decisions, the chip giant has greenlit a massive US$17 billion investment to boost production capacity. According to TSMC, to meet long-term capacity plans based on market demand forecasts and TSMC's technology development roadmap, the board approved capital appropriations of approximately US$17.14 billion for installation and upgrade of advanced technology capacity, installation and upgrade of advanced packaging, mature and/or specialty technology capacity, fab construction, and installation of fab facility systems.

Previous reports by MoneyDJ suggested that TSMC might unveil plans for a third Arizona fab, a potential fourth fab, or its first advanced packaging plant after the board meeting. However, no updates have been confirmed yet. Industry sources suggested that TSMC's second Arizona fab, featuring 3 nm, will likely go ahead of schedule, providing a temporary response to U.S. pressures. According to the same report, TSMC's second Arizona fab is expected to begin equipment installation in mid-2026, with mass production expected by 2027. Notably, this progress would exceed TSMC's projections which expected the second plant to start 3 nm and 2 nm production in 2028, with a third plant potentially for the 2 nm process by the late 2030s. The MoneyDJ report further notes that initially, TSMC's second Arizona plant will offer 25K-30K 3 nm wafers per month. TSMC's first Arizona plant, initially slated for 2025, started 4 nm production ahead of schedule in Q4 2024.

Intel's freshly uploaded fourth-quarter 2024 "CEO/CFO earnings call comments" document has revealed grand CPU-related plans for 2025 and beyond. One of Team Blue's interim leaders—Michelle Johnston Holthaus—believes that "Nova Lake" processors (a next-generation client family) will arrive in 2026, following a comprehensive rollout of "Panther Lake" CPU products. This official timeline matches previously leaked and rumored development schedules—most notably, in a shipping manifest that was discovered last week. In recent times, industry watchdogs have linked "Nova Lake" to Intel's own 14A node and a TSMC 2 nm process node. Additionally, tipsters pointed to an apparent selection of Coyote Cove performance cores and Arctic Wolf efficiency-oriented cores.

Following yesterday's official announcements, a leaker shared several insights—theorized core configurations and manufacturing details were posted on the Hardware subreddit. Community members were engaged in a debate over Intel's "killing of Falcon Shore," but a plucky contributor—going under the moniker "Exist50"—redirected conversation to all-things "Nova Lake." They believe that Intel has shifted all "compute dies to TSMC" for manufacturing, after a change in plans—initial designs had the "8+16 die" on TSMC's N2P, and the "4+8 die on Intel 18A." Exist50 seemed to have inside track knowledge of product ranges: "Nova Lake (NVL) has a unified HUB/SoC die across mobile and desktop. So yeah, the baseline there is 4+8+4. But there's at least one more die for mobile." The flagship desktop (NVL-S or NVL-SK) chip's configuration could feature as many as sixteen performance cores and thirty-two efficiency cores, due to tile reuse—2x (8P+16E). Exist50 advised Intel CPU enthusiasts to forgo current generation offerings. "Nova Lake" should be: "quite a jump from Arrow Lake (ARL) in terms of MT performance, to say the least. I think anyone who buys ARL will end up regretting it, big time!"

Samsung Electronics today reported financial results for the fourth quarter and the fiscal year 2024. The Company posted KRW 75.8 trillion in consolidated revenue and KRW 6.5 trillion in operating profit in the quarter ended December 31, 2024. For the full year, it reported KRW 300.9 trillion in annual revenue and KRW 32.7 trillion in operating profit.

Although fourth quarter revenue and operating profit decreased on a quarter-on-quarter (QoQ) basis, annual revenue reached the second-highest on record, surpassed only in 2022. Meanwhile, operating profit was down KRW 2.7 trillion QoQ, due to soft market conditions especially for IT products, and an increase in expenditures including R&D. In the first quarter of 2025, while overall earnings improvement may be limited due to weakness in the semiconductors business, the Company aims to pursue growth through increased sales of smartphones with differentiated AI experiences, as well as premium products in the Device eXperience (DX) Division.

Cadence today announced that MediaTek has adopted the AI-driven Cadence Virtuoso Studio and Spectre X Simulator on the NVIDIA accelerated computing platform for its 2 nm development. As design size and complexity continue to escalate, advanced-node technology development has become increasingly challenging for SoC providers. To meet the aggressive performance and turnaround time (TAT) requirements for its 2 nm high-speed analog IP, MediaTek is leveraging Cadence's proven custom/analog design solutions, enhanced by AI, to achieve a 30% productivity gain.

"As MediaTek continues to push technology boundaries for 2 nm development, we need a trusted design solution with strong AI-powered tools to achieve our goals," said Ching San Wu, corporate vice president at MediaTek. "Closely collaborating with Cadence, we have adopted the Cadence Virtuoso Studio and Spectre X Simulator, which deliver the performance and accuracy necessary to achieve our tight design turnaround time requirements. Cadence's comprehensive automation features enhance our throughput and efficiency, enabling our designers to be 30% more productive."

Shipping manifests at NBD.ltd have revealed the presence of Intel's "Nova Lake" test chips, providing insight into the development timeline of the company's 2026 processor platform. The discovery comes as Intel prepares for the launch of its "Panther Lake" CPUs on the 18A process node in late 2025. Nova Lake is positioned to replace both Panther Lake for mobile devices and "Arrow Lake" for desktop systems. The manufacturing process remains unconfirmed, with Intel potentially using either its in-house 14A node or TSMC's 2 nm technology. Following recent practices, Intel may split production between its own facilities and TSMC for different components. Rumored specifications show that Nova Lake will use Coyote Cove performance cores and Arctic Wolf efficiency cores.

Unlike Lunar Lake, it will not incorporate on-package memory, maintaining a more conventional design approach. The test chip's appearance suggests Intel is adhering to its development schedule. This timing aligns with the company's plans for Panther Lake's mass production in the second half of 2025, a structured transition between generations. Documents point to "Razor Lake" as Nova Lake's eventual successor, though detailed specifications are not yet available. Panther Lake, the immediate predecessor to Nova Lake, will focus primarily on mobile computing, with desktop variants limited to Mini PC implementations. This approach mirrors the Meteor Lake generation, which saw limited desktop release through the "PS" series for Edge platforms. The Nova Lake platform is expected to support DDR5 memory and may introduce PCIe Gen 6.0 compatibility, with final specifications unconfirmed.

Last November, Taiwan's National Science and Technology Council indicated that it was considering a relaxation of "legal restrictions on transferring leading-edge process technology overseas." TSMC is the nation's most prized chip foundry, but new manufacturing operations are spreading across the globe. The very best node processes—currently TSMC's advanced 2 nm (N2)—have been restricted to home turf, yet global tensions have prompted the Taiwanese government to reconsider its guarded approach. A freshly published Taipei Times report has focused on an important announcement made at a recent government press conference. Taiwan's Minister of Economic Affairs of Taiwan, J.W. Kuo, stated that TSMC is now allowed to manufacture 2 nm chips on foreign soil—according to him, the foundry behemoth is "cautiously" evaluating an investment of roughly $28 to 30 (USD) billion into 2-nanometer production facilities Stateside.

His colleagues have worked hard—in the past—on preserving the country's "Silicon Shield," but fresh adjustments are sweeping in. Kuo commented: "those were old-time rules. Times have changed." TSMC's—allegedly costly—North American hub is reportedly marked down for a "by 2030" push into 2 nm process territories. Taiwan's Economic Affairs minister continued with his reasonings: "Private businesses should make their own business decisions based on their own technological progress...The basic principle is that businesses can make profits from their overseas investments. TSMC is building factories in the US with the aim of serving its US customers, as 60 percent of the world's chip-designing companies are based in the US." He also downplayed concerns regarding possible upcoming shifts in US trade policy making—Taiwan's "strong technological capabilities" are expected to weather the storm. Newly implemented US trade tariffs are expected to have only a "minor impact."

TSMC is reportedly making decent progress with its advanced 2 nm (N2) node—industry news pieces from earlier this month pointed to the initiation of production lines across three fabrication sites. Taiwan's Economic Daily News has kept close tabs on these trial runs—insiders have indicated that TSMC's Kaohsiung plant is capable of matching the Baoshan location's targeted manufacturing output (5000 wafers per month, 60 percent yield). Reports suggest that the Kaohsiung 2 nm trial production will start up later this month—much earlier than anticipated.

The Taiwanese chip foundry giant is taking on the challenge of meeting "greater than expected" demand for its new generation 2 nm product—TSMC chairman C.C. Wei has previously stated that its latest and greatest is more popular (pre-launch) with customers than older 3 nm lines. Apple is rumored to be first in line—not a big surprise since TSMC has (supposedly) rolled out the VVIP red carpet for them in recent times. The Economic Daily News article also mentions Qualcomm and MediaTek being next in the queue for N2. TSMC's best foundries are expected to initiate mass production by the end of 2025.

Lam Research Corporation today announced that its innovative dry photoresist (dry resist) technology has been qualified for direct-print 28 nm pitch back end of line (BEOL) logic at 2 nm and below by imec, a leading research and innovation hub in nanoelectronics and digital technologies. An advanced patterning technique introduced by Lam, dry resist enhances the resolution, productivity and yield of extreme ultraviolet (EUV) lithography, a pivotal technology used in the production of next-generation semiconductor devices.

"Lam's dry photoresist technology provides unparalleled low-defectivity, high-resolution patterning," said Vahid Vahedi, chief technology and sustainability officer at Lam Research. "We are excited to offer this technology to imec and its partners as a critical process in the design and manufacturing of leading-edge semiconductor devices."

TSMC is making progress with its most advanced 2 nm (N2) node, a recent report from MoneyDJ quoting industry sources indicates that the company is setting up a test production line at the Hsinchu Baoshan fab (Fab 20) in Taiwan. In the early stages, TSMC aims for small monthly outputs with about 3,000-3,500 wafers. However, the company has big plans to combine production from two factories in Hsinchu and Kaohsiung, TSMC expects to deliver more than 50,000 wafers monthly by the end of 2025 and by the end of 2026 projecting a production of around 125,000 wafers per month. Breaking it down by location, the Hsinchu factory should reach 20,000-25,000 wafers monthly by late 2025, growing to about 60,000-65,000 by early 2027. Meanwhile, the Kaohsiung factory is expected to produce 25,000-30,000 wafers monthly by late 2025, also increasing to 60,000-65,000 by early 2027.

TSMC's chairman C.C. Wei says there's more demand for these 2 nm chips than there was for the 3 nm. This increased "appetite" for 2 nm chips is likely due to the significant improvements this technology brings: it uses 24-35% less power, can run 15% faster at the same power level, and can fit 15% more transistors in the same space compared to the 3 nm chips. Apple will be the first company to use these chips, followed by other major tech companies like MediaTek, Qualcomm, Intel, NVIDIA, AMD, and Broadcom.

Rapidus Corporation, a manufacturer of advanced logic semiconductors, today announced the delivery and installation of ASML's EUV lithography equipment at its Innovative Integration for Manufacturing (IIM-1) foundry, an advanced semiconductor development and manufacturing fab currently under construction in Chitose, Hokkaido. To commemorate the installation, a ceremony was held at Portom Hall in the New Chitose Airport.

This is a significant milestone for Japan's semiconductor industry, marking the first time that an EUV lithography tool will be used for mass production in the country. In addition to the EUV lithography machinery, Rapidus will install additional complementary advanced semiconductor manufacturing equipment, as well as full automated material handling systems in its IIM-1 foundry to optimize 2 nm generation gate-all-around (GAA) semiconductor manufacturing.

Dai Nippon Printing Co., Ltd. (DNP) has successfully achieved the fine pattern resolution required for photomasks for logic semiconductors of the beyond 2 nm (nm: 10-9 meter) generation that support Extreme Ultra-Violet (EUV) lithography, a cutting-edge process in semiconductor manufacturing.

DNP has also completed the criteria evaluation for photomasks compatible with High-Numerical Aperture, the application being considered for next-generation semiconductors beyond the 2 nm generation, and has commenced the supply of evaluation photomasks. High-NA EUV lithography makes it possible to form fine patterns on silicon wafers with a higher resolution than previously possible, and is expected to lead to the realization of high-performance, low-power semiconductors.

Being the leading-edge semiconductor manufacturing company, TSMC actively works on increasing the efficiency of its upcoming nodes, even when they are finalized and ready for high-volume manufacturing. According to a TSMC employee identified as Dr. Kim on X, recent test runs of the 2 nm N2 nodes show a 6% improvement in production yields compared to baseline expectations. This advancement could translate into substantial cost savings for the company's customers when mass production begins in late 2025. However, specific details about whether the gains were achieved in SRAM or logic test chips remain undisclosed. The timing is particularly noteworthy as TSMC prepares to launch its shuttle test wafer services for 2 nm technology in January. The N2 process represents a giant leap for TSMC, marking its first gate-all-around (GAA) nanosheet transistors implementation, the first step to derive from the classical FinFET design.

According to TSMC's projections, chips manufactured using the N2 process will consume 25-30% less power while maintaining the same transistor count and frequency as its N3E node. Additionally, the technology is expected to deliver 10-15% performance improvements and achieve a 15% increase in transistor density. A key innovation in the N2 process is the enhanced design of its GAA nanosheet transistors, which offers improved electrostatic control and reduced gate leakage compared to 3 nm FinFET transistors, given that the gate can be controlled from all sides. This advancement enables smaller high-density transistors to maintain reliable performance through better threshold voltage tuning capabilities. With approximately seven to eight months until full-scale volume production begins, the company has a substantial window to optimize the manufacturing process further and potentially achieve additional yield improvements, although that is less likely.