Rapidus Corporation, a manufacturer of advanced logic semiconductors, today announced the delivery and installation of ASML's EUV lithography equipment at its Innovative Integration for Manufacturing (IIM-1) foundry, an advanced semiconductor development and manufacturing fab currently under construction in Chitose, Hokkaido. To commemorate the installation, a ceremony was held at Portom Hall in the New Chitose Airport.

This is a significant milestone for Japan's semiconductor industry, marking the first time that an EUV lithography tool will be used for mass production in the country. In addition to the EUV lithography machinery, Rapidus will install additional complementary advanced semiconductor manufacturing equipment, as well as full automated material handling systems in its IIM-1 foundry to optimize 2 nm generation gate-all-around (GAA) semiconductor manufacturing.

Dai Nippon Printing Co., Ltd. (DNP) has successfully achieved the fine pattern resolution required for photomasks for logic semiconductors of the beyond 2 nm (nm: 10-9 meter) generation that support Extreme Ultra-Violet (EUV) lithography, a cutting-edge process in semiconductor manufacturing.

DNP has also completed the criteria evaluation for photomasks compatible with High-Numerical Aperture, the application being considered for next-generation semiconductors beyond the 2 nm generation, and has commenced the supply of evaluation photomasks. High-NA EUV lithography makes it possible to form fine patterns on silicon wafers with a higher resolution than previously possible, and is expected to lead to the realization of high-performance, low-power semiconductors.

Being the leading-edge semiconductor manufacturing company, TSMC actively works on increasing the efficiency of its upcoming nodes, even when they are finalized and ready for high-volume manufacturing. According to a TSMC employee identified as Dr. Kim on X, recent test runs of the 2 nm N2 nodes show a 6% improvement in production yields compared to baseline expectations. This advancement could translate into substantial cost savings for the company's customers when mass production begins in late 2025. However, specific details about whether the gains were achieved in SRAM or logic test chips remain undisclosed. The timing is particularly noteworthy as TSMC prepares to launch its shuttle test wafer services for 2 nm technology in January. The N2 process represents a giant leap for TSMC, marking its first gate-all-around (GAA) nanosheet transistors implementation, the first step to derive from the classical FinFET design.

According to TSMC's projections, chips manufactured using the N2 process will consume 25-30% less power while maintaining the same transistor count and frequency as its N3E node. Additionally, the technology is expected to deliver 10-15% performance improvements and achieve a 15% increase in transistor density. A key innovation in the N2 process is the enhanced design of its GAA nanosheet transistors, which offers improved electrostatic control and reduced gate leakage compared to 3 nm FinFET transistors, given that the gate can be controlled from all sides. This advancement enables smaller high-density transistors to maintain reliable performance through better threshold voltage tuning capabilities. With approximately seven to eight months until full-scale volume production begins, the company has a substantial window to optimize the manufacturing process further and potentially achieve additional yield improvements, although that is less likely.

Taiwanese political officials have agreed to discuss transferring TSMC's advanced 2 nm chip technology to allied democratic nations, but only after establishing the main mass production launch in late 2025 in Taiwan. This new stance comes amid growing international pressure and recent comments from upcoming US president Donald Trump about semiconductor manufacturing. The announcement by National Science and Technology Council Minister Cheng-Wen Wu marks a notable departure from earlier statements by Economic Affairs Minister J.W. Kuo, who had previously emphasized legal restrictions on transferring leading-edge process technology overseas. Interestingly, these different positions aren't so different from one point: timeline of node deployments. As TSMC produces latest nodes in Taiwan, overseas production will lag by a generation or two.

TSMC plans to implement its 2 nm technology in US facilities by 2030. The company's Arizona facility, Fab 21, will begin with less advanced N4 and N5 processes in early 2025 and progress to 3 nm technology by 2028. However, this timeline could face pressure for acceleration, mainly if new trade policies are implemented. Industry analyst Dan Nystedt points out significant challenges in transferring advanced chip production. Integrating research and development with manufacturing processes in Taiwan provides crucial advantages for initial production ramps, making simultaneous mass production launches in multiple locations technically challenging. Simply put, there aren't enough capable engineers, scientists, and factory workers capable of doing what TSMC accomplishes in Taiwan.

Apple is reportedly considering diversifying its chip manufacturing strategy with a new silicon manufacturer: Intel. While the upcoming iPhone 17 series, expected next year, will likely feature A19 chips produced by TSMC, a recent rumor from Chinese leaker Fixed Focus Digital hints at a potential switch to Intel for the A20 chipsets powering the 2026 iPhone 18 series. The A18 and A18 Pro chipsets debuted alongside the iPhone 16 series in September 2024, manufactured using TSMC's N3E node. Apple's A19 chips are expected to upgrade to TSMC's N3P node. According to the source, Apple is seeking an Intel 20A node. However, since the A20 node is canceled in favor of 18A, Apple could be an Intel Foundry customer for either 18A or 14A nodes.

Despite the buzz, skepticism persists. Intel has historically struggled with process node transitions and even outsourced production of its Arrow Lake CPUs to TSMC, raising questions about its readiness to deliver on Apple's demands. On the other hand, alternative reports suggest Apple might stick with TSMC's yet-unnamed 2 nm node for the A20, maintaining continuity in its supply chain. As the iPhone 18 series remains two years away, much can change. For now, we are left speculating whether this rumored collaboration with Intel represents a new chapter in Apple's chipset innovation or just a rumor with little substance. If the US government mandates more domestic production, chip designers could be looking at some of the more local manufacturing options, like Intel does on US soil. That could force Apple, NVIDIA, AMD, and Qualcomm to look into Intel's offerings.

The EUV lithography machine from ASML ordered by Rapidus is expected to arrive in Japan in mid-December, according to information from Nikkei cited by TrendForce. This marks the first deployment of EUV technology in Japan, an important step for the country's semiconductor industry as it seeks to establish itself as a major player. Rapidus is currently building a factory in Chitose, Hokkaido, and plans to start mass production of 2 nm chips in 2027. The company also plans to purchase several EUV devices if the 2-nanometer chip production is successful, and intends to build a second production facility specifically for 1.4 nm chips. To support these operations, ASML will establish a service center in Chitose City.

NVIDIA CEO Jensen Huang hinted at the possibility of outsourcing AI chip production to Rapidus. As of October, construction progress on the Rapidus facility, which began in September 2023, is up to 63% and remains on track. In addition to Rapidus, Micron's Hiroshima plant is scheduled to install EUV equipment in 2025, allowing for mass production in 2026. JASM, a TSMC subsidiary in Japan, plans to integrate EUV lithography with a second wafer plant in 2027 that will have a 6 nm production line.

Samsung's latest semiconductor manufacturing technology is falling short of expectations, as the company struggles to achieve acceptable production rates for its cutting-edge 3 nm chips. The latest rumors indicate that both versions of Samsung's 3 nm Gate-All-Around (GAA) process produce fewer viable chips than anticipated. The initial targets set by the South Korean tech giant were aimed at a 70% yield rate in volume production. However, the first "SF3E-3GAE" iteration of the technology has only managed to achieve between 50-60% viable yield output. More troubling is the performance of the second-generation process, which is reportedly yielding only 20% of usable chips—a figure that falls dramatically short of production goals. The timing is particularly challenging for Samsung as major clients begin to reevaluate their manufacturing partnerships.

Qualcomm has opted to produce its latest Snapdragon 8 Elite processors exclusively through rival TSMC's 3 nm facilities. Even more telling is the exodus of South Korean companies, traditionally loyal to Samsung, who are now turning to TSMC's more reliable manufacturing processes. While Samsung can claim the achievement of bringing 3 nm GAA technology to market before TSMC's competing N3B process, this technical victory rings hollow without the ability to mass-produce chips efficiently. The gap between Samsung's aspirations and manufacturing reality continues to widen. However, Samsung is shifting its focus toward its next technological milestone. Development efforts are reportedly intensifying around a 2 nm manufacturing process, with plans to debut this technology in a new Exynos processor (codenamed 'Ulysses') for the 2027 Galaxy S27 smartphone series.

Even with billions of US dollars being invested overseas, TSMC cannot legally manufacture its most advanced nodes outside of Taiwan. According to Taiwan's Minister of Economic Affairs J.W. Kuo, "Since Taiwan has regulations to protect its own technologies, TSMC cannot produce 2-nanometer chips overseas currently." He added, "Although TSMC plans to make 2-nanometer chips [abroad] in the future, its core technology will stay in Taiwan." This provides crucial insight into TSMC's strategic positioning, both in its US expansion plans and in navigating global geopolitical waters, especially with Taiwan being the major hub of silicon innovation. Taiwan's semiconductor industry follows strict regulations regarding overseas production capabilities, requiring companies to maintain their most advanced manufacturing processes within Taiwan.

The company's international expansion strategy includes significant developments in the United States. TSMC's Arizona facilities are central to these plans, with multiple fabs in different stages of development. The initial Arizona facility will begin producing 4 nm chips imminently, while a second facility, scheduled to open in 2028, will manufacture then mature 3 nm and 2 nm chips. A third planned facility aims to produce 2 nm or more sophisticated chips. Meanwhile, Taiwan-based facilities will produce more advanced chips at the same time, with volume production of A-16 chips planned for late 2026, following the rollout of 2 nm chip production in 2025. Furthermore, Taiwan-US semiconductor cooperation will continue regardless of political changes. Taiwan Semiconductor Industry Association (TSIA) Chairman and TSMC Senior Vice President Cliff Hou noted that historical evidence suggests US electoral outcomes have not significantly impacted this technological partnership, though some adjustments may occur.

Samsung Electronics today reported financial results for the third quarter ended Sept. 30, 2024. The Company posted KRW 79.1 trillion in consolidated revenue, an increase of 7% from the previous quarter, on the back of the launch effects of new smartphone models and increased sales of high-end memory products. Operating profit declined to KRW 9.18 trillion, largely due to one-off costs, including the provision of incentives in the Device Solutions (DS) Division. The strength of the Korean won against the U.S. dollar resulted in a negative impact on company-wide operating profit of about KRW 0.5 trillion compared to the previous quarter.

In the fourth quarter, while memory demand for mobile and PC may encounter softness, growth in AI will keep demand at robust levels. Against this backdrop, the Company will concentrate on driving sales of High Bandwidth Memory (HBM) and high-density products. The Foundry Business aims to increase order volumes by enhancing advanced process technologies. Samsung Display Corporation (SDC) expects the demand of flagship products from major customers to continue, while maintaining a quite conservative outlook on its performance. The Device eXperience (DX) Division will continue to focus on premium products, but sales are expected to decline slightly compared to the previous quarter.

Our latest front-page poll sheds light on what people want from the next generation of gaming GPUs. We asked our readers what mattered most to them, with answers including raster performance, ray tracing performance, energy efficiency, upscaling or frame-gen technologies, the size of video memory, and lastly, pricing. Our poll ran from September 19, and gathered close to 24,000 votes as of this writing. Pricing remains the king of our polls, with the option gathering 36.1% of the vote, or 8,620 votes. Our readers expect pricing of next-generation GPUs to remain flat, variant-for-variant, and not continue on the absurdly upward trend it has had for the past few generations, with the high-end being pushed beyond the $1,000-mark, and $500 barely bringing in a 1440p-class GPU, while 4K-capable game consoles exist.

Both AMD and NVIDIA know that Moore's Law is cooked, and that generational leaps in performance and transistor counts are only possible with increase in pricing for the latest foundry nodes. AMD even tried experimenting with disaggregated (chiplet-based) GPUs with its latest RDNA 3 generation, before calling it quits on the enthusiast-segment, so it could focus on the sub-$1000 performance segment. The second most popular response was Raster 3D performance (classic 3D rendering performance), which scored 27% or 6,453 votes.

Yesterday, Arm has announced significant progress in its Total Design initiative. The program, launched a year ago, aims to accelerate the development of custom silicon for data centers by fostering collaboration among industry partners. The ecosystem has now grown to include nearly 30 participating companies, with recent additions such as Alcor Micro, Egis, PUF Security, and SEMIFIVE. A notable development is a partnership between Arm, Samsung Foundry, ADTechnology, and Rebellions to create an AI CPU chiplet platform. This collaboration aims to deliver a solution for cloud, HPC, and AI/ML workloads, combining Rebellions' AI accelerator with ADTechnology's compute chiplet, implemented using Samsung Foundry's 2 nm Gate-All-Around (GAA) FET technology. The platform is expected to offer significant efficiency gains for generative AI workloads, with estimates suggesting a 2-3x improvement over the standard CPU design for LLMs like Llama3.1 with 405 billion parameters.

Arm's approach emphasizes the importance of CPU compute in supporting the complete AI stack, including data pre-processing, orchestration, and advanced techniques like Retrieval-augmented Generation (RAG). The company's Compute Subsystems (CSS) are designed to address these requirements, providing a foundation for partners to build diverse chiplet solutions. Several companies, including Alcor Micro and Alphawave, have already announced plans to develop CSS-powered chiplets for various AI and high-performance computing applications. The initiative also focuses on software readiness, ensuring that major frameworks and operating systems are compatible with Arm-based systems. Recent efforts include the introduction of Arm Kleidi technology, which optimizes CPU-based inference for open-source projects like PyTorch and Llama.cpp. Notably, as Google claims, most AI workloads are being inferenced on CPUs, so creating the most efficient and most performant CPUs for AI makes a lot of sense.

Samsung Electronics is speeding up its work on 2 nm production facilities, industry sources say. The company has started to install advanced equipment at its "S3" foundry line in Hwaseong to set up a 2 nm production line. This line aims to produce 7,000 wafers each month by the first quarter of next year. Also, Samsung plans to create a 1.4 nm production line at its "S5" foundry in Pyeongtaek Plant 2 by the second quarter of next year. This line has a goal to make 2,000 to 3,000 wafers each month. By the end of next year, Samsung will change all the remaining 3 nm production lines at "S3" to 2 nm.

As we reported earlier, Samsung has pushed back the start date for its Tyler, Texas foundry. The plant set to open by late 2024, won't install equipment until after 2026. Also, Samsung has changed its plans for the Pyeongtaek Fab 4 foundry line. Because of lower demand, it will now make DRAM instead, moreover, at Pyeongtaek Fab 3, which has a 4 nm line, Samsung has cut back production. These changes are part of Samsung's plan to make 2 nm chips next year and 1.4 nm chips by 2027. The company wants to catch up with its rival TSMC, right now, Samsung has 11.5% of the global foundry market in Q2, while TSMC leads with 62.3%. An industry expert stressed how crucial this is saying, "With the delay in 3 nm Exynos production and other issues, getting the 2 nm process right could make or break Samsung Foundry". The struggle for Samsung is real, with the company's top management, led by DS Division Vice Chairman Jeon Young-hyun, having recently issued a public apology for the division's underwhelming performance.

Samsung's foundry plans have again hit a major setback. The company notified staff at its Taylor, Texas facility that it was temporarily removing workers from the site because it is still experiencing challenges with 2 nm semiconductor yields, delaying mass production timelines from late 2024 to 2026. The Taylor site had been anticipated as the flagship facility for Samsung's sub-4 nm production, allowing access to potential customers near the facility. While Samsung has moved rapidly in terms of process development, its yields for advanced nodes have outstripped them, the company's yields for sub-3 nm processes hover around 50%, with Gate-All-Around (GAA) technology witnessing yields of only 10-20%, significantly lower than neighboring competitor TSMC's 60-70% for corresponding nodes.

The yield gaps that the company is experiencing have exacerbated the gap in market share, with TSMC capturing 62.3% of the global foundry market share in Q2 versus Samsung's 11.5%. The company is struggling to gain share despite efforts by Chairman Lee Jae-yong - including visits to component suppliers ASML, and Zeiss - and these yields put at risk as much as 9 trillion won in U.S. CHIP Act potential subsidies that are dependent upon operational milestones.

TSMC has reportedly managed to produce yields at its Arizona facility that are on par with yields back home in Taiwan, making its expansion efforts successful. According to Bloomberg, TSMC did a trial production, a multi-month effort, to produce N4 node wafers with low defect rates. With wafers now in TSMC's labs for testing, it is reported that Arizona facility yields have achieved parity with their Taiwanese facilities back home. This indicates that TSMC's efforts to expand in the US are so far considered a success, as advanced chipmaking is a very complex process that is only done by a few makers and in very few locations. With TSMC expanding in the US now and proving that its technology can work on US soil, the company has a green light to start volume production in the first half of 2025.

However, this is only the beginning of TSMC's Arizona expansion. The Taiwanese giant plans to have a second fab operational by 2028 and produce 2 nm and 3 nm chips in the state. Additionally, there will be a third facility for 2 nm and more advanced nodes in Phoenix, bringing the total value of TSMC's US expansion efforts to $65 billion, with $6.6 billion from the CHIPS Act grants and $5 billion in loans from the US government. If upcoming fabs follow the lead of the first facility, US-based production needs will possibly be satisfied.

Imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, presents patterned structures obtained after exposure with the 0.55NA EUV scanner in the joint ASML-imec High NA EUV Lithography Lab in Veldhoven, the Netherlands. Random logic structures down to 9,5 nm (19 nm pitch), random vias with 30 nm center-to-center distance, 2D features at 22 nm pitch, and a DRAM specific lay out at P32nm were printed after single exposure, using materials and baseline processes that were optimized for High NA EUV by imec and its partners in the framework of imec's Advanced Patterning Program. With these results, imec confirms the readiness of the ecosystem to enable single exposure high-resolution High NA EUV Lithography.

Following the recent opening of the joint ASML-imec High NA EUV Lithography Lab in Veldhoven, the Netherlands, customers now have access to the (TWINSCAN EXE:5000) High NA EUV scanner to develop private High NA EUV use cases leveraging the customer's own design rules and lay outs.

Samsung Electronics today reported financial results for the second quarter ended June 30, 2024. The Company posted KRW 74.07 trillion in consolidated revenue and operating profit of KRW 10.44 trillion as favorable memory market conditions drove higher average sales price (ASP), while robust sales of OLED panels also contributed to the results.

Memory Market Continues To Recover; Solid Second Half Outlook Centered on Server Demand
The DS Division posted KRW 28.56 trillion in consolidated revenue and KRW 6.45 trillion in operating profit for the second quarter. Driven by strong demand for HBM as well as conventional DRAM and server SSDs, the memory market as a whole continued its recovery. This increased demand is a result of the continued AI investments by cloud service providers and growing demand for AI from businesses for their on-premise servers.

Applied Materials, Inc. today introduced materials engineering innovations designed to increase the performance-per-watt of computer systems by enabling copper wiring to scale to the 2 nm logic node and beyond. "The AI era needs more energy-efficient computing, and chip wiring and stacking are critical to performance and power consumption," said Dr. Prabu Raja, President of the Semiconductor Products Group at Applied Materials. "Applied's newest integrated materials solution enables the industry to scale low-resistance copper wiring to the emerging angstrom nodes, while our latest low-k dielectric material simultaneously reduces capacitance and strengthens chips to take 3D stacking to new heights."

Overcoming the Physics Challenges of Classic Moore's Law Scaling
Today's most advanced logic chips can contain tens of billions of transistors connected by more than 60 miles of microscopic copper wiring. Each layer of a chip's wiring begins with a thin film of dielectric material, which is etched to create channels that are filled with copper. Low-k dielectrics and copper have been the industry's workhorse wiring combination for decades, allowing chipmakers to deliver improvements in scaling, performance and power-efficiency with each generation.

Samsung Electronics, a world leader in advanced semiconductor technology, today announced that it will provide turnkey semiconductor solutions using the 2-nanometer (nm) foundry process and the advanced 2.5D packaging technology Interposer-Cube S (I-Cube S) to Preferred Networks, a leading Japanese AI company.

By leveraging Samsung's leading-edge foundry and advanced packaging products, Preferred Networks aims to develop powerful AI accelerators that meet the ever-growing demand for computing power driven by generative AI.

Ansys power integrity solutions have been certified by Samsung Foundry for use with Samsung's new SF2Z 2 nm gate-all-around manufacturing technology. SF2Z includes advanced technology that moves the power distribution network to the backside of the chip — saving space, lowering costs, and improving performance. Ansys solutions enable early adopters of Samsung's technology to design leading-edge semiconductor products for HPC, smartphones, AI, data center communication, and graphics processors.

The certification includes RedHawk-SC, which provides predictively accurate signoff verification for electromigration and voltage drop (IR drop) on power distribution networks for digital designs. In addition, the Totem power integrity platform provides comprehensive evaluation for analog and mixed-signal designs. Both RedHawk-SC and Totem signoff capabilities can reduce project risk, improve reliability, and extend the longevity of chips.

Samsung Electronics is delaying construction at its planned new chip factory in Taylor, Texas. The company is considering upgrading the factory to produce more advanced 2 nm chips instead of the originally planned 4 nm chips. Samsung will make a final decision on this in Q3 2024. In April, the US government provided $6.4 billion to support Samsung's $40 billion investment in Texas chip facilities, including the Taylor factory. However, reports now suggest Samsung may skip 4 nm production at Taylor altogether.

The Taylor factory was expected to open by 2026, but equipment orders have been delayed while Samsung re-evaluates the plans. This upgrade consideration comes after Samsung recently appointed a new CEO for its semiconductor business (Device Solutions Division) to focus on new growth opportunities. While Samsung's memory chip profits surged in 2024, its previous 3 nm chip was not very successful. By going straight to 2 nm in Taylor, Samsung likely aims to leapfrog competitors in advanced chip manufacturing (TSMC, and Intel plan to produce 2 nm-class chips in the US by the end of this decade).

Samsung Electronics, a world leader in advanced semiconductor technology, today unveiled its latest foundry innovations and outlined its vision for the AI era during Samsung Foundry Forum (SFF) U.S., an annual event held at the company's Device Solutions America headquarters in San Jose, California. Under the theme "Empowering the AI Revolution," Samsung announced its reinforced process technology roadmap, including two new cutting-edge nodes—SF2Z and SF4U—as well as its integrated Samsung AI Solutions platform harnessing the unique strengths of its Foundry, Memory and Advanced Package (AVP) businesses.

"At a time when numerous technologies are evolving around AI, the key to its implementation lies in high-performance, low-power semiconductors," said Dr. Siyoung Choi, President and Head of Foundry Business at Samsung Electronics. "Alongside our proven GAA process optimized for AI chips, we plan to introduce integrated, co-packaged optics (CPO) technology for high-speed, low-power data processing, providing our customers with the one-stop AI solutions they need to thrive in this transformative era."

Apple is locked in a fierce competition to stay ahead in the client AI applications race, and needs access to the latest foundry process at TSMC to built its future-generation SoCs on. The company's COO, Jeff Williams, reportedly paid a visit to TSMC CEO CC Wei to discuss Apple's foundry allocation of the Taiwanese foundry's 2 nm-class silicon fabrication process, for its next-generation M-series and A-series SoCs powering its future generations of iPhone, iPad, and Macs. Taiwan based industry observer, Economic Daily, which broke this story, says that it isn't just an edge with performance and efficiency that Apple is after, but also leadership in generative AI, and client AI applications. The company has reportedly invested over $100 billion in generative AI research and development over the past 5 years.

Apple's latest silicon, the M4 SoC, which debuted with the iPad Pro earlier this month, is built on TSMC's N3E (3 nm-class) node, and it's widely expected that the rest of the M4 line of SoCs for Macs, and the "A18," could be built on the same process, which would cover Apple for the rest of 2024, going into the first half of 2025. TSMC is expected to commence mass-production of chips on its 2 nm node in 2025, which is why Apple is in the TSMC boss's office to seek the first foundry allocation.

Samsung Electronics today reported financial results for the first quarter ended March 31, 2024. The Company posted KRW 71.92 trillion in consolidated revenue on the back of strong sales of flagship Galaxy S24 smartphones and higher prices for memory semiconductors. Operating profit increased to KRW 6.61 trillion as the Memory Business returned to profit by addressing demand for high value-added products. The Mobile eXperience (MX) Business posted higher earnings and the Visual Display and Digital Appliances businesses also recorded increased profitability.

The weakness of the Korean won against major currencies resulted in a positive impact on company-wide operating profit of about KRW 0.3 trillion compared to the previous quarter. The Company's total capital expenditures in the first quarter stood at KRW 11.3 trillion, including KRW 9.7 trillion for the Device Solutions (DS) Division and KRW 1.1 trillion on Samsung Display Corporation (SDC). Spending on memory was focused on facilities and packaging technologies to address demand for High Bandwidth Memory (HBM), DDR5 and other advanced products, while foundry investments were concentrated on establishing infrastructure to meet medium- to long-term demand. Display investments were mainly made in IT OLED products and flexible display technologies.

According to the latest report from Bloomberg, the US government under Joe Biden's administration has announced plans to provide Taiwan Semiconductor Manufacturing Company (TSMC) with a substantial financial support package worth $11.6 billion. The package is composed of $6.6 billion in grants and up to $5 billion in loans. This represents the most significant financial assistance approved under the CHIPS and Science Act, a key initiative to resurrect the US chip industry. The funding will aid TSMC in establishing three cutting-edge semiconductor production facilities in Arizona, with the company's total investment in the state expected to exceed an impressive $65 billion. TSMC's multi-phase Arizona project will commence with the construction of a fab module near its existing Fab 21 facility. Production using 4 nm and 5 nm process nodes is slated to begin by early 2025. The second phase, scheduled for 2028, will focus on even more advanced 2 nm and 3 nm technologies.

TSMC has kept details about the third facility's production timeline and process node under wraps. The company's massive investment in Arizona is expected to profoundly impact the local economy, creating 6,000 high-tech manufacturing jobs and over 20,000 construction positions. Moreover, $50 million has been earmarked for training local workers, which aligns with President Joe Biden's goal of bolstering domestic manufacturing and technological independence. However, TSMC's Arizona projects have encountered obstacles, including labor disputes and uncertainties regarding government support, resulting in delays for the second facility's production timeline. Additionally, reports suggest that at least one TSMC supplier has abandoned plans to set up operations in Arizona due to workforce-related challenges.

One key takeaway from the ongoing GTC is that Nvidia's AI empire has taken shape with strong partnerships from TSMC and other Taiwanese makers, such as those major server ODMs.

According to the news report from the technology-focused media DIGITIMES Asia, during his keynote at GTC on March 18, Huang underscored his company's partnerships with TSMC, as well as the supply chain in Taiwan. Speaking to the press later, Huang said Nvidia will have a very strong demand for CoWoS, the advanced packaging services TSMC offers.