Samsung's foundry operation has experienced many setbacks over the past six months, according to a steady feed of insider reports. Last November, industry moles leaked details of an apparent abandonment of the company's 3 nm Gate-All-Around (GAA) process. Significant yield problems prompted an alleged shift into 2 nm territories, with a next-gen flagship Exynos mobile processor linked to this cutting-edge node. According to a mid-week Chosun Daily article, Samsung and its main rival—TSMC—are in a race to establish decent yields of 2 nm wafers, ahead of predicted "late 2025" mass production kick-offs. The publication's inside track points to the Taiwanese foundry making the most progress (with an estimated 60%), but watchdogs warn that it is too early to bet against the South Korean competitor.

Despite murmurs of current 20 - 30% yields, the Samsung's Hwaseong facility is touted to make "smooth" progress over the coming months. Chosun's sources believe that Samsung engineers struggled to get 3 nm GAA "up to snuff," spending around three years on development endeavors (in vain). In comparison, the making of 2 nm GAA is reported to be less bumpy. A fully upgraded "S3" foundry line is expected to come online by the fourth quarter of this year. An unnamed insider commented on rumors of better than anticipated forward motion chez Samsung Electronics: "there are positive aspects to this as it has shown technological improvements, such as the recent increase in the yield of its 4 nm process by up to 80%." Recent-ish reports suggest that foundry teams have dealt with budget cuts, as well as mounting pressure from company leadership to hit deadlines.

Earlier in the year, we heard about TSMC being ahead of the game with its speculated trial production run of cutting-edge 2 nm (N2) silicon. Taiwan's premier foundry company is reportedly prepping its Baoshan and Kaohsiung plants for full-on manufacturing of next-gen chips. The latest insider whispers propose that TSMC is making "rapid" progress on the 2 nm (N2) front, as company engineers have moved onto an "intensive" trial production phase. Taiwan's Economic Daily News has picked up on compelling projections from industry moles; the Hsinchu Baoshan facility's current monthly production capacity is (allegedly) around 5000 to 10,000 2 nm wafers. The other 2 nm-specialist site—Kaohsiung—has reportedly moved into a small-scale appraisal phase.

TSMC declined to comment on recently leaked data points, but they released a general statement (to UDN), emphasizing that: "(our) 2 nm process technology is progressing well and will go into mass production as scheduled in the second half of this year." The Baoshan plant could ramp up to 25,000 2 nm wafers per month, once it moves into a mass production phase. Combined with the same estimated output from its sister site (Kaohsiung), insiders reckon that the combined total could reach 50,000 units per month. Following a predicted successful "second phase" transition, TSMC's most advanced facilities have a "chance" to pump out 80,000 2 nm parts (combined total). The latest murmurs suggest that this milestone could be achieved by the end of 2025. Industry watchdogs believe that Apple will have first access dibs on TSMC's upcoming cutting-edge offerings.

The late 2024 news cycle suggested that Samsung's semiconductor business was going through tough times. Alleged yield problems—affecting the 3 nm Gate-All-Around (GAA) process—were highlighted last November. Fast-forward to January 2025; the South Korean megacorp has launched its cutting-edge Galaxy S25 smartphone series. The entire lineup of newly unveiled flagship smartphones contains Qualcomm's Snapdragon 8 Elite mobile chipsets; the Southern Californian chip designer is reportedly pulling in a tidy sum from this partnership. Fresh reports from South Korean news outlets indicate that Samsung System LSI employees have received an "encouraging" email from their boss, regarding current production predicaments.

Businesskorea and Sedaily reports include quotes extracted from the (apparently) leaked internal memo. LSI division president, Park Yong-in, reportedly stated: "we are currently in a situation where we have to develop two flagship products at the same time." Both articles allege that Samsung's semiconductor teams are expected to "cultivate roots and withstand storms." Industry watchdogs believe that the aforementioned "flagship products" are the Exynos 2500 mobile chipset, and Samsung Electronic's next-gen Galaxy S26 smartphone family. Earlier this month, we heard whispers about the much-delayed in-house chip design being readied (with a 2 nm process) for a possible late 2025 launch, inside unannounced Galaxy Z Flip 7 and Fold 7 devices. Park disclosed anticipated incoming obstacles in 2025: "last year's business division profit was higher than expected, but this was a temporary phenomenon...Looking at the entire business division, there will be monthly surpluses and deficits." Last month, inside sources proposed the notion that foundry investments were slashed in half.

TSMC has unveiled today its board meeting decisions, the chip giant has greenlit a massive US$17 billion investment to boost production capacity. According to TSMC, to meet long-term capacity plans based on market demand forecasts and TSMC's technology development roadmap, the board approved capital appropriations of approximately US$17.14 billion for installation and upgrade of advanced technology capacity, installation and upgrade of advanced packaging, mature and/or specialty technology capacity, fab construction, and installation of fab facility systems.

Previous reports by MoneyDJ suggested that TSMC might unveil plans for a third Arizona fab, a potential fourth fab, or its first advanced packaging plant after the board meeting. However, no updates have been confirmed yet. Industry sources suggested that TSMC's second Arizona fab, featuring 3 nm, will likely go ahead of schedule, providing a temporary response to U.S. pressures. According to the same report, TSMC's second Arizona fab is expected to begin equipment installation in mid-2026, with mass production expected by 2027. Notably, this progress would exceed TSMC's projections which expected the second plant to start 3 nm and 2 nm production in 2028, with a third plant potentially for the 2 nm process by the late 2030s. The MoneyDJ report further notes that initially, TSMC's second Arizona plant will offer 25K-30K 3 nm wafers per month. TSMC's first Arizona plant, initially slated for 2025, started 4 nm production ahead of schedule in Q4 2024.

Intel's freshly uploaded fourth-quarter 2024 "CEO/CFO earnings call comments" document has revealed grand CPU-related plans for 2025 and beyond. One of Team Blue's interim leaders—Michelle Johnston Holthaus—believes that "Nova Lake" processors (a next-generation client family) will arrive in 2026, following a comprehensive rollout of "Panther Lake" CPU products. This official timeline matches previously leaked and rumored development schedules—most notably, in a shipping manifest that was discovered last week. In recent times, industry watchdogs have linked "Nova Lake" to Intel's own 14A node and a TSMC 2 nm process node. Additionally, tipsters pointed to an apparent selection of Coyote Cove performance cores and Arctic Wolf efficiency-oriented cores.

Following yesterday's official announcements, a leaker shared several insights—theorized core configurations and manufacturing details were posted on the Hardware subreddit. Community members were engaged in a debate over Intel's "killing of Falcon Shore," but a plucky contributor—going under the moniker "Exist50"—redirected conversation to all-things "Nova Lake." They believe that Intel has shifted all "compute dies to TSMC" for manufacturing, after a change in plans—initial designs had the "8+16 die" on TSMC's N2P, and the "4+8 die on Intel 18A." Exist50 seemed to have inside track knowledge of product ranges: "Nova Lake (NVL) has a unified HUB/SoC die across mobile and desktop. So yeah, the baseline there is 4+8+4. But there's at least one more die for mobile." The flagship desktop (NVL-S or NVL-SK) chip's configuration could feature as many as sixteen performance cores and thirty-two efficiency cores, due to tile reuse—2x (8P+16E). Exist50 advised Intel CPU enthusiasts to forgo current generation offerings. "Nova Lake" should be: "quite a jump from Arrow Lake (ARL) in terms of MT performance, to say the least. I think anyone who buys ARL will end up regretting it, big time!"

Samsung Electronics today reported financial results for the fourth quarter and the fiscal year 2024. The Company posted KRW 75.8 trillion in consolidated revenue and KRW 6.5 trillion in operating profit in the quarter ended December 31, 2024. For the full year, it reported KRW 300.9 trillion in annual revenue and KRW 32.7 trillion in operating profit.

Although fourth quarter revenue and operating profit decreased on a quarter-on-quarter (QoQ) basis, annual revenue reached the second-highest on record, surpassed only in 2022. Meanwhile, operating profit was down KRW 2.7 trillion QoQ, due to soft market conditions especially for IT products, and an increase in expenditures including R&D. In the first quarter of 2025, while overall earnings improvement may be limited due to weakness in the semiconductors business, the Company aims to pursue growth through increased sales of smartphones with differentiated AI experiences, as well as premium products in the Device eXperience (DX) Division.

Cadence today announced that MediaTek has adopted the AI-driven Cadence Virtuoso Studio and Spectre X Simulator on the NVIDIA accelerated computing platform for its 2 nm development. As design size and complexity continue to escalate, advanced-node technology development has become increasingly challenging for SoC providers. To meet the aggressive performance and turnaround time (TAT) requirements for its 2 nm high-speed analog IP, MediaTek is leveraging Cadence's proven custom/analog design solutions, enhanced by AI, to achieve a 30% productivity gain.

"As MediaTek continues to push technology boundaries for 2 nm development, we need a trusted design solution with strong AI-powered tools to achieve our goals," said Ching San Wu, corporate vice president at MediaTek. "Closely collaborating with Cadence, we have adopted the Cadence Virtuoso Studio and Spectre X Simulator, which deliver the performance and accuracy necessary to achieve our tight design turnaround time requirements. Cadence's comprehensive automation features enhance our throughput and efficiency, enabling our designers to be 30% more productive."

Shipping manifests at NBD.ltd have revealed the presence of Intel's "Nova Lake" test chips, providing insight into the development timeline of the company's 2026 processor platform. The discovery comes as Intel prepares for the launch of its "Panther Lake" CPUs on the 18A process node in late 2025. Nova Lake is positioned to replace both Panther Lake for mobile devices and "Arrow Lake" for desktop systems. The manufacturing process remains unconfirmed, with Intel potentially using either its in-house 14A node or TSMC's 2 nm technology. Following recent practices, Intel may split production between its own facilities and TSMC for different components. Rumored specifications show that Nova Lake will use Coyote Cove performance cores and Arctic Wolf efficiency cores.

Unlike Lunar Lake, it will not incorporate on-package memory, maintaining a more conventional design approach. The test chip's appearance suggests Intel is adhering to its development schedule. This timing aligns with the company's plans for Panther Lake's mass production in the second half of 2025, a structured transition between generations. Documents point to "Razor Lake" as Nova Lake's eventual successor, though detailed specifications are not yet available. Panther Lake, the immediate predecessor to Nova Lake, will focus primarily on mobile computing, with desktop variants limited to Mini PC implementations. This approach mirrors the Meteor Lake generation, which saw limited desktop release through the "PS" series for Edge platforms. The Nova Lake platform is expected to support DDR5 memory and may introduce PCIe Gen 6.0 compatibility, with final specifications unconfirmed.

Last November, Taiwan's National Science and Technology Council indicated that it was considering a relaxation of "legal restrictions on transferring leading-edge process technology overseas." TSMC is the nation's most prized chip foundry, but new manufacturing operations are spreading across the globe. The very best node processes—currently TSMC's advanced 2 nm (N2)—have been restricted to home turf, yet global tensions have prompted the Taiwanese government to reconsider its guarded approach. A freshly published Taipei Times report has focused on an important announcement made at a recent government press conference. Taiwan's Minister of Economic Affairs of Taiwan, J.W. Kuo, stated that TSMC is now allowed to manufacture 2 nm chips on foreign soil—according to him, the foundry behemoth is "cautiously" evaluating an investment of roughly $28 to 30 (USD) billion into 2-nanometer production facilities Stateside.

His colleagues have worked hard—in the past—on preserving the country's "Silicon Shield," but fresh adjustments are sweeping in. Kuo commented: "those were old-time rules. Times have changed." TSMC's—allegedly costly—North American hub is reportedly marked down for a "by 2030" push into 2 nm process territories. Taiwan's Economic Affairs minister continued with his reasonings: "Private businesses should make their own business decisions based on their own technological progress...The basic principle is that businesses can make profits from their overseas investments. TSMC is building factories in the US with the aim of serving its US customers, as 60 percent of the world's chip-designing companies are based in the US." He also downplayed concerns regarding possible upcoming shifts in US trade policy making—Taiwan's "strong technological capabilities" are expected to weather the storm. Newly implemented US trade tariffs are expected to have only a "minor impact."

TSMC is reportedly making decent progress with its advanced 2 nm (N2) node—industry news pieces from earlier this month pointed to the initiation of production lines across three fabrication sites. Taiwan's Economic Daily News has kept close tabs on these trial runs—insiders have indicated that TSMC's Kaohsiung plant is capable of matching the Baoshan location's targeted manufacturing output (5000 wafers per month, 60 percent yield). Reports suggest that the Kaohsiung 2 nm trial production will start up later this month—much earlier than anticipated.

The Taiwanese chip foundry giant is taking on the challenge of meeting "greater than expected" demand for its new generation 2 nm product—TSMC chairman C.C. Wei has previously stated that its latest and greatest is more popular (pre-launch) with customers than older 3 nm lines. Apple is rumored to be first in line—not a big surprise since TSMC has (supposedly) rolled out the VVIP red carpet for them in recent times. The Economic Daily News article also mentions Qualcomm and MediaTek being next in the queue for N2. TSMC's best foundries are expected to initiate mass production by the end of 2025.

Lam Research Corporation today announced that its innovative dry photoresist (dry resist) technology has been qualified for direct-print 28 nm pitch back end of line (BEOL) logic at 2 nm and below by imec, a leading research and innovation hub in nanoelectronics and digital technologies. An advanced patterning technique introduced by Lam, dry resist enhances the resolution, productivity and yield of extreme ultraviolet (EUV) lithography, a pivotal technology used in the production of next-generation semiconductor devices.

"Lam's dry photoresist technology provides unparalleled low-defectivity, high-resolution patterning," said Vahid Vahedi, chief technology and sustainability officer at Lam Research. "We are excited to offer this technology to imec and its partners as a critical process in the design and manufacturing of leading-edge semiconductor devices."

TSMC is making progress with its most advanced 2 nm (N2) node, a recent report from MoneyDJ quoting industry sources indicates that the company is setting up a test production line at the Hsinchu Baoshan fab (Fab 20) in Taiwan. In the early stages, TSMC aims for small monthly outputs with about 3,000-3,500 wafers. However, the company has big plans to combine production from two factories in Hsinchu and Kaohsiung, TSMC expects to deliver more than 50,000 wafers monthly by the end of 2025 and by the end of 2026 projecting a production of around 125,000 wafers per month. Breaking it down by location, the Hsinchu factory should reach 20,000-25,000 wafers monthly by late 2025, growing to about 60,000-65,000 by early 2027. Meanwhile, the Kaohsiung factory is expected to produce 25,000-30,000 wafers monthly by late 2025, also increasing to 60,000-65,000 by early 2027.

TSMC's chairman C.C. Wei says there's more demand for these 2 nm chips than there was for the 3 nm. This increased "appetite" for 2 nm chips is likely due to the significant improvements this technology brings: it uses 24-35% less power, can run 15% faster at the same power level, and can fit 15% more transistors in the same space compared to the 3 nm chips. Apple will be the first company to use these chips, followed by other major tech companies like MediaTek, Qualcomm, Intel, NVIDIA, AMD, and Broadcom.

Rapidus Corporation, a manufacturer of advanced logic semiconductors, today announced the delivery and installation of ASML's EUV lithography equipment at its Innovative Integration for Manufacturing (IIM-1) foundry, an advanced semiconductor development and manufacturing fab currently under construction in Chitose, Hokkaido. To commemorate the installation, a ceremony was held at Portom Hall in the New Chitose Airport.

This is a significant milestone for Japan's semiconductor industry, marking the first time that an EUV lithography tool will be used for mass production in the country. In addition to the EUV lithography machinery, Rapidus will install additional complementary advanced semiconductor manufacturing equipment, as well as full automated material handling systems in its IIM-1 foundry to optimize 2 nm generation gate-all-around (GAA) semiconductor manufacturing.

Dai Nippon Printing Co., Ltd. (DNP) has successfully achieved the fine pattern resolution required for photomasks for logic semiconductors of the beyond 2 nm (nm: 10-9 meter) generation that support Extreme Ultra-Violet (EUV) lithography, a cutting-edge process in semiconductor manufacturing.

DNP has also completed the criteria evaluation for photomasks compatible with High-Numerical Aperture, the application being considered for next-generation semiconductors beyond the 2 nm generation, and has commenced the supply of evaluation photomasks. High-NA EUV lithography makes it possible to form fine patterns on silicon wafers with a higher resolution than previously possible, and is expected to lead to the realization of high-performance, low-power semiconductors.

Being the leading-edge semiconductor manufacturing company, TSMC actively works on increasing the efficiency of its upcoming nodes, even when they are finalized and ready for high-volume manufacturing. According to a TSMC employee identified as Dr. Kim on X, recent test runs of the 2 nm N2 nodes show a 6% improvement in production yields compared to baseline expectations. This advancement could translate into substantial cost savings for the company's customers when mass production begins in late 2025. However, specific details about whether the gains were achieved in SRAM or logic test chips remain undisclosed. The timing is particularly noteworthy as TSMC prepares to launch its shuttle test wafer services for 2 nm technology in January. The N2 process represents a giant leap for TSMC, marking its first gate-all-around (GAA) nanosheet transistors implementation, the first step to derive from the classical FinFET design.

According to TSMC's projections, chips manufactured using the N2 process will consume 25-30% less power while maintaining the same transistor count and frequency as its N3E node. Additionally, the technology is expected to deliver 10-15% performance improvements and achieve a 15% increase in transistor density. A key innovation in the N2 process is the enhanced design of its GAA nanosheet transistors, which offers improved electrostatic control and reduced gate leakage compared to 3 nm FinFET transistors, given that the gate can be controlled from all sides. This advancement enables smaller high-density transistors to maintain reliable performance through better threshold voltage tuning capabilities. With approximately seven to eight months until full-scale volume production begins, the company has a substantial window to optimize the manufacturing process further and potentially achieve additional yield improvements, although that is less likely.

Taiwanese political officials have agreed to discuss transferring TSMC's advanced 2 nm chip technology to allied democratic nations, but only after establishing the main mass production launch in late 2025 in Taiwan. This new stance comes amid growing international pressure and recent comments from upcoming US president Donald Trump about semiconductor manufacturing. The announcement by National Science and Technology Council Minister Cheng-Wen Wu marks a notable departure from earlier statements by Economic Affairs Minister J.W. Kuo, who had previously emphasized legal restrictions on transferring leading-edge process technology overseas. Interestingly, these different positions aren't so different from one point: timeline of node deployments. As TSMC produces latest nodes in Taiwan, overseas production will lag by a generation or two.

TSMC plans to implement its 2 nm technology in US facilities by 2030. The company's Arizona facility, Fab 21, will begin with less advanced N4 and N5 processes in early 2025 and progress to 3 nm technology by 2028. However, this timeline could face pressure for acceleration, mainly if new trade policies are implemented. Industry analyst Dan Nystedt points out significant challenges in transferring advanced chip production. Integrating research and development with manufacturing processes in Taiwan provides crucial advantages for initial production ramps, making simultaneous mass production launches in multiple locations technically challenging. Simply put, there aren't enough capable engineers, scientists, and factory workers capable of doing what TSMC accomplishes in Taiwan.

Apple is reportedly considering diversifying its chip manufacturing strategy with a new silicon manufacturer: Intel. While the upcoming iPhone 17 series, expected next year, will likely feature A19 chips produced by TSMC, a recent rumor from Chinese leaker Fixed Focus Digital hints at a potential switch to Intel for the A20 chipsets powering the 2026 iPhone 18 series. The A18 and A18 Pro chipsets debuted alongside the iPhone 16 series in September 2024, manufactured using TSMC's N3E node. Apple's A19 chips are expected to upgrade to TSMC's N3P node. According to the source, Apple is seeking an Intel 20A node. However, since the A20 node is canceled in favor of 18A, Apple could be an Intel Foundry customer for either 18A or 14A nodes.

Despite the buzz, skepticism persists. Intel has historically struggled with process node transitions and even outsourced production of its Arrow Lake CPUs to TSMC, raising questions about its readiness to deliver on Apple's demands. On the other hand, alternative reports suggest Apple might stick with TSMC's yet-unnamed 2 nm node for the A20, maintaining continuity in its supply chain. As the iPhone 18 series remains two years away, much can change. For now, we are left speculating whether this rumored collaboration with Intel represents a new chapter in Apple's chipset innovation or just a rumor with little substance. If the US government mandates more domestic production, chip designers could be looking at some of the more local manufacturing options, like Intel does on US soil. That could force Apple, NVIDIA, AMD, and Qualcomm to look into Intel's offerings.

The EUV lithography machine from ASML ordered by Rapidus is expected to arrive in Japan in mid-December, according to information from Nikkei cited by TrendForce. This marks the first deployment of EUV technology in Japan, an important step for the country's semiconductor industry as it seeks to establish itself as a major player. Rapidus is currently building a factory in Chitose, Hokkaido, and plans to start mass production of 2 nm chips in 2027. The company also plans to purchase several EUV devices if the 2-nanometer chip production is successful, and intends to build a second production facility specifically for 1.4 nm chips. To support these operations, ASML will establish a service center in Chitose City.

NVIDIA CEO Jensen Huang hinted at the possibility of outsourcing AI chip production to Rapidus. As of October, construction progress on the Rapidus facility, which began in September 2023, is up to 63% and remains on track. In addition to Rapidus, Micron's Hiroshima plant is scheduled to install EUV equipment in 2025, allowing for mass production in 2026. JASM, a TSMC subsidiary in Japan, plans to integrate EUV lithography with a second wafer plant in 2027 that will have a 6 nm production line.

Samsung's latest semiconductor manufacturing technology is falling short of expectations, as the company struggles to achieve acceptable production rates for its cutting-edge 3 nm chips. The latest rumors indicate that both versions of Samsung's 3 nm Gate-All-Around (GAA) process produce fewer viable chips than anticipated. The initial targets set by the South Korean tech giant were aimed at a 70% yield rate in volume production. However, the first "SF3E-3GAE" iteration of the technology has only managed to achieve between 50-60% viable yield output. More troubling is the performance of the second-generation process, which is reportedly yielding only 20% of usable chips—a figure that falls dramatically short of production goals. The timing is particularly challenging for Samsung as major clients begin to reevaluate their manufacturing partnerships.

Qualcomm has opted to produce its latest Snapdragon 8 Elite processors exclusively through rival TSMC's 3 nm facilities. Even more telling is the exodus of South Korean companies, traditionally loyal to Samsung, who are now turning to TSMC's more reliable manufacturing processes. While Samsung can claim the achievement of bringing 3 nm GAA technology to market before TSMC's competing N3B process, this technical victory rings hollow without the ability to mass-produce chips efficiently. The gap between Samsung's aspirations and manufacturing reality continues to widen. However, Samsung is shifting its focus toward its next technological milestone. Development efforts are reportedly intensifying around a 2 nm manufacturing process, with plans to debut this technology in a new Exynos processor (codenamed 'Ulysses') for the 2027 Galaxy S27 smartphone series.

Even with billions of US dollars being invested overseas, TSMC cannot legally manufacture its most advanced nodes outside of Taiwan. According to Taiwan's Minister of Economic Affairs J.W. Kuo, "Since Taiwan has regulations to protect its own technologies, TSMC cannot produce 2-nanometer chips overseas currently." He added, "Although TSMC plans to make 2-nanometer chips [abroad] in the future, its core technology will stay in Taiwan." This provides crucial insight into TSMC's strategic positioning, both in its US expansion plans and in navigating global geopolitical waters, especially with Taiwan being the major hub of silicon innovation. Taiwan's semiconductor industry follows strict regulations regarding overseas production capabilities, requiring companies to maintain their most advanced manufacturing processes within Taiwan.

The company's international expansion strategy includes significant developments in the United States. TSMC's Arizona facilities are central to these plans, with multiple fabs in different stages of development. The initial Arizona facility will begin producing 4 nm chips imminently, while a second facility, scheduled to open in 2028, will manufacture then mature 3 nm and 2 nm chips. A third planned facility aims to produce 2 nm or more sophisticated chips. Meanwhile, Taiwan-based facilities will produce more advanced chips at the same time, with volume production of A-16 chips planned for late 2026, following the rollout of 2 nm chip production in 2025. Furthermore, Taiwan-US semiconductor cooperation will continue regardless of political changes. Taiwan Semiconductor Industry Association (TSIA) Chairman and TSMC Senior Vice President Cliff Hou noted that historical evidence suggests US electoral outcomes have not significantly impacted this technological partnership, though some adjustments may occur.

Samsung Electronics today reported financial results for the third quarter ended Sept. 30, 2024. The Company posted KRW 79.1 trillion in consolidated revenue, an increase of 7% from the previous quarter, on the back of the launch effects of new smartphone models and increased sales of high-end memory products. Operating profit declined to KRW 9.18 trillion, largely due to one-off costs, including the provision of incentives in the Device Solutions (DS) Division. The strength of the Korean won against the U.S. dollar resulted in a negative impact on company-wide operating profit of about KRW 0.5 trillion compared to the previous quarter.

In the fourth quarter, while memory demand for mobile and PC may encounter softness, growth in AI will keep demand at robust levels. Against this backdrop, the Company will concentrate on driving sales of High Bandwidth Memory (HBM) and high-density products. The Foundry Business aims to increase order volumes by enhancing advanced process technologies. Samsung Display Corporation (SDC) expects the demand of flagship products from major customers to continue, while maintaining a quite conservative outlook on its performance. The Device eXperience (DX) Division will continue to focus on premium products, but sales are expected to decline slightly compared to the previous quarter.

Our latest front-page poll sheds light on what people want from the next generation of gaming GPUs. We asked our readers what mattered most to them, with answers including raster performance, ray tracing performance, energy efficiency, upscaling or frame-gen technologies, the size of video memory, and lastly, pricing. Our poll ran from September 19, and gathered close to 24,000 votes as of this writing. Pricing remains the king of our polls, with the option gathering 36.1% of the vote, or 8,620 votes. Our readers expect pricing of next-generation GPUs to remain flat, variant-for-variant, and not continue on the absurdly upward trend it has had for the past few generations, with the high-end being pushed beyond the $1,000-mark, and $500 barely bringing in a 1440p-class GPU, while 4K-capable game consoles exist.

Both AMD and NVIDIA know that Moore's Law is cooked, and that generational leaps in performance and transistor counts are only possible with increase in pricing for the latest foundry nodes. AMD even tried experimenting with disaggregated (chiplet-based) GPUs with its latest RDNA 3 generation, before calling it quits on the enthusiast-segment, so it could focus on the sub-$1000 performance segment. The second most popular response was Raster 3D performance (classic 3D rendering performance), which scored 27% or 6,453 votes.

Yesterday, Arm has announced significant progress in its Total Design initiative. The program, launched a year ago, aims to accelerate the development of custom silicon for data centers by fostering collaboration among industry partners. The ecosystem has now grown to include nearly 30 participating companies, with recent additions such as Alcor Micro, Egis, PUF Security, and SEMIFIVE. A notable development is a partnership between Arm, Samsung Foundry, ADTechnology, and Rebellions to create an AI CPU chiplet platform. This collaboration aims to deliver a solution for cloud, HPC, and AI/ML workloads, combining Rebellions' AI accelerator with ADTechnology's compute chiplet, implemented using Samsung Foundry's 2 nm Gate-All-Around (GAA) FET technology. The platform is expected to offer significant efficiency gains for generative AI workloads, with estimates suggesting a 2-3x improvement over the standard CPU design for LLMs like Llama3.1 with 405 billion parameters.

Arm's approach emphasizes the importance of CPU compute in supporting the complete AI stack, including data pre-processing, orchestration, and advanced techniques like Retrieval-augmented Generation (RAG). The company's Compute Subsystems (CSS) are designed to address these requirements, providing a foundation for partners to build diverse chiplet solutions. Several companies, including Alcor Micro and Alphawave, have already announced plans to develop CSS-powered chiplets for various AI and high-performance computing applications. The initiative also focuses on software readiness, ensuring that major frameworks and operating systems are compatible with Arm-based systems. Recent efforts include the introduction of Arm Kleidi technology, which optimizes CPU-based inference for open-source projects like PyTorch and Llama.cpp. Notably, as Google claims, most AI workloads are being inferenced on CPUs, so creating the most efficient and most performant CPUs for AI makes a lot of sense.

Samsung Electronics is speeding up its work on 2 nm production facilities, industry sources say. The company has started to install advanced equipment at its "S3" foundry line in Hwaseong to set up a 2 nm production line. This line aims to produce 7,000 wafers each month by the first quarter of next year. Also, Samsung plans to create a 1.4 nm production line at its "S5" foundry in Pyeongtaek Plant 2 by the second quarter of next year. This line has a goal to make 2,000 to 3,000 wafers each month. By the end of next year, Samsung will change all the remaining 3 nm production lines at "S3" to 2 nm.

As we reported earlier, Samsung has pushed back the start date for its Tyler, Texas foundry. The plant set to open by late 2024, won't install equipment until after 2026. Also, Samsung has changed its plans for the Pyeongtaek Fab 4 foundry line. Because of lower demand, it will now make DRAM instead, moreover, at Pyeongtaek Fab 3, which has a 4 nm line, Samsung has cut back production. These changes are part of Samsung's plan to make 2 nm chips next year and 1.4 nm chips by 2027. The company wants to catch up with its rival TSMC, right now, Samsung has 11.5% of the global foundry market in Q2, while TSMC leads with 62.3%. An industry expert stressed how crucial this is saying, "With the delay in 3 nm Exynos production and other issues, getting the 2 nm process right could make or break Samsung Foundry". The struggle for Samsung is real, with the company's top management, led by DS Division Vice Chairman Jeon Young-hyun, having recently issued a public apology for the division's underwhelming performance.

Samsung's foundry plans have again hit a major setback. The company notified staff at its Taylor, Texas facility that it was temporarily removing workers from the site because it is still experiencing challenges with 2 nm semiconductor yields, delaying mass production timelines from late 2024 to 2026. The Taylor site had been anticipated as the flagship facility for Samsung's sub-4 nm production, allowing access to potential customers near the facility. While Samsung has moved rapidly in terms of process development, its yields for advanced nodes have outstripped them, the company's yields for sub-3 nm processes hover around 50%, with Gate-All-Around (GAA) technology witnessing yields of only 10-20%, significantly lower than neighboring competitor TSMC's 60-70% for corresponding nodes.

The yield gaps that the company is experiencing have exacerbated the gap in market share, with TSMC capturing 62.3% of the global foundry market share in Q2 versus Samsung's 11.5%. The company is struggling to gain share despite efforts by Chairman Lee Jae-yong - including visits to component suppliers ASML, and Zeiss - and these yields put at risk as much as 9 trillion won in U.S. CHIP Act potential subsidies that are dependent upon operational milestones.