Imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, presents patterned structures obtained after exposure with the 0.55NA EUV scanner in the joint ASML-imec High NA EUV Lithography Lab in Veldhoven, the Netherlands. Random logic structures down to 9,5 nm (19 nm pitch), random vias with 30 nm center-to-center distance, 2D features at 22 nm pitch, and a DRAM specific lay out at P32nm were printed after single exposure, using materials and baseline processes that were optimized for High NA EUV by imec and its partners in the framework of imec's Advanced Patterning Program. With these results, imec confirms the readiness of the ecosystem to enable single exposure high-resolution High NA EUV Lithography.

Following the recent opening of the joint ASML-imec High NA EUV Lithography Lab in Veldhoven, the Netherlands, customers now have access to the (TWINSCAN EXE:5000) High NA EUV scanner to develop private High NA EUV use cases leveraging the customer's own design rules and lay outs.

Samsung Electronics today reported financial results for the second quarter ended June 30, 2024. The Company posted KRW 74.07 trillion in consolidated revenue and operating profit of KRW 10.44 trillion as favorable memory market conditions drove higher average sales price (ASP), while robust sales of OLED panels also contributed to the results.

Memory Market Continues To Recover; Solid Second Half Outlook Centered on Server Demand
The DS Division posted KRW 28.56 trillion in consolidated revenue and KRW 6.45 trillion in operating profit for the second quarter. Driven by strong demand for HBM as well as conventional DRAM and server SSDs, the memory market as a whole continued its recovery. This increased demand is a result of the continued AI investments by cloud service providers and growing demand for AI from businesses for their on-premise servers.

Applied Materials, Inc. today introduced materials engineering innovations designed to increase the performance-per-watt of computer systems by enabling copper wiring to scale to the 2 nm logic node and beyond. "The AI era needs more energy-efficient computing, and chip wiring and stacking are critical to performance and power consumption," said Dr. Prabu Raja, President of the Semiconductor Products Group at Applied Materials. "Applied's newest integrated materials solution enables the industry to scale low-resistance copper wiring to the emerging angstrom nodes, while our latest low-k dielectric material simultaneously reduces capacitance and strengthens chips to take 3D stacking to new heights."

Overcoming the Physics Challenges of Classic Moore's Law Scaling
Today's most advanced logic chips can contain tens of billions of transistors connected by more than 60 miles of microscopic copper wiring. Each layer of a chip's wiring begins with a thin film of dielectric material, which is etched to create channels that are filled with copper. Low-k dielectrics and copper have been the industry's workhorse wiring combination for decades, allowing chipmakers to deliver improvements in scaling, performance and power-efficiency with each generation.

Samsung Electronics, a world leader in advanced semiconductor technology, today announced that it will provide turnkey semiconductor solutions using the 2-nanometer (nm) foundry process and the advanced 2.5D packaging technology Interposer-Cube S (I-Cube S) to Preferred Networks, a leading Japanese AI company.

By leveraging Samsung's leading-edge foundry and advanced packaging products, Preferred Networks aims to develop powerful AI accelerators that meet the ever-growing demand for computing power driven by generative AI.

Ansys power integrity solutions have been certified by Samsung Foundry for use with Samsung's new SF2Z 2 nm gate-all-around manufacturing technology. SF2Z includes advanced technology that moves the power distribution network to the backside of the chip — saving space, lowering costs, and improving performance. Ansys solutions enable early adopters of Samsung's technology to design leading-edge semiconductor products for HPC, smartphones, AI, data center communication, and graphics processors.

The certification includes RedHawk-SC, which provides predictively accurate signoff verification for electromigration and voltage drop (IR drop) on power distribution networks for digital designs. In addition, the Totem power integrity platform provides comprehensive evaluation for analog and mixed-signal designs. Both RedHawk-SC and Totem signoff capabilities can reduce project risk, improve reliability, and extend the longevity of chips.

Samsung Electronics is delaying construction at its planned new chip factory in Taylor, Texas. The company is considering upgrading the factory to produce more advanced 2 nm chips instead of the originally planned 4 nm chips. Samsung will make a final decision on this in Q3 2024. In April, the US government provided $6.4 billion to support Samsung's $40 billion investment in Texas chip facilities, including the Taylor factory. However, reports now suggest Samsung may skip 4 nm production at Taylor altogether.

The Taylor factory was expected to open by 2026, but equipment orders have been delayed while Samsung re-evaluates the plans. This upgrade consideration comes after Samsung recently appointed a new CEO for its semiconductor business (Device Solutions Division) to focus on new growth opportunities. While Samsung's memory chip profits surged in 2024, its previous 3 nm chip was not very successful. By going straight to 2 nm in Taylor, Samsung likely aims to leapfrog competitors in advanced chip manufacturing (TSMC, and Intel plan to produce 2 nm-class chips in the US by the end of this decade).

Samsung Electronics, a world leader in advanced semiconductor technology, today unveiled its latest foundry innovations and outlined its vision for the AI era during Samsung Foundry Forum (SFF) U.S., an annual event held at the company's Device Solutions America headquarters in San Jose, California. Under the theme "Empowering the AI Revolution," Samsung announced its reinforced process technology roadmap, including two new cutting-edge nodes—SF2Z and SF4U—as well as its integrated Samsung AI Solutions platform harnessing the unique strengths of its Foundry, Memory and Advanced Package (AVP) businesses.

"At a time when numerous technologies are evolving around AI, the key to its implementation lies in high-performance, low-power semiconductors," said Dr. Siyoung Choi, President and Head of Foundry Business at Samsung Electronics. "Alongside our proven GAA process optimized for AI chips, we plan to introduce integrated, co-packaged optics (CPO) technology for high-speed, low-power data processing, providing our customers with the one-stop AI solutions they need to thrive in this transformative era."

Apple is locked in a fierce competition to stay ahead in the client AI applications race, and needs access to the latest foundry process at TSMC to built its future-generation SoCs on. The company's COO, Jeff Williams, reportedly paid a visit to TSMC CEO CC Wei to discuss Apple's foundry allocation of the Taiwanese foundry's 2 nm-class silicon fabrication process, for its next-generation M-series and A-series SoCs powering its future generations of iPhone, iPad, and Macs. Taiwan based industry observer, Economic Daily, which broke this story, says that it isn't just an edge with performance and efficiency that Apple is after, but also leadership in generative AI, and client AI applications. The company has reportedly invested over $100 billion in generative AI research and development over the past 5 years.

Apple's latest silicon, the M4 SoC, which debuted with the iPad Pro earlier this month, is built on TSMC's N3E (3 nm-class) node, and it's widely expected that the rest of the M4 line of SoCs for Macs, and the "A18," could be built on the same process, which would cover Apple for the rest of 2024, going into the first half of 2025. TSMC is expected to commence mass-production of chips on its 2 nm node in 2025, which is why Apple is in the TSMC boss's office to seek the first foundry allocation.

Samsung Electronics today reported financial results for the first quarter ended March 31, 2024. The Company posted KRW 71.92 trillion in consolidated revenue on the back of strong sales of flagship Galaxy S24 smartphones and higher prices for memory semiconductors. Operating profit increased to KRW 6.61 trillion as the Memory Business returned to profit by addressing demand for high value-added products. The Mobile eXperience (MX) Business posted higher earnings and the Visual Display and Digital Appliances businesses also recorded increased profitability.

The weakness of the Korean won against major currencies resulted in a positive impact on company-wide operating profit of about KRW 0.3 trillion compared to the previous quarter. The Company's total capital expenditures in the first quarter stood at KRW 11.3 trillion, including KRW 9.7 trillion for the Device Solutions (DS) Division and KRW 1.1 trillion on Samsung Display Corporation (SDC). Spending on memory was focused on facilities and packaging technologies to address demand for High Bandwidth Memory (HBM), DDR5 and other advanced products, while foundry investments were concentrated on establishing infrastructure to meet medium- to long-term demand. Display investments were mainly made in IT OLED products and flexible display technologies.

According to the latest report from Bloomberg, the US government under Joe Biden's administration has announced plans to provide Taiwan Semiconductor Manufacturing Company (TSMC) with a substantial financial support package worth $11.6 billion. The package is composed of $6.6 billion in grants and up to $5 billion in loans. This represents the most significant financial assistance approved under the CHIPS and Science Act, a key initiative to resurrect the US chip industry. The funding will aid TSMC in establishing three cutting-edge semiconductor production facilities in Arizona, with the company's total investment in the state expected to exceed an impressive $65 billion. TSMC's multi-phase Arizona project will commence with the construction of a fab module near its existing Fab 21 facility. Production using 4 nm and 5 nm process nodes is slated to begin by early 2025. The second phase, scheduled for 2028, will focus on even more advanced 2 nm and 3 nm technologies.

TSMC has kept details about the third facility's production timeline and process node under wraps. The company's massive investment in Arizona is expected to profoundly impact the local economy, creating 6,000 high-tech manufacturing jobs and over 20,000 construction positions. Moreover, $50 million has been earmarked for training local workers, which aligns with President Joe Biden's goal of bolstering domestic manufacturing and technological independence. However, TSMC's Arizona projects have encountered obstacles, including labor disputes and uncertainties regarding government support, resulting in delays for the second facility's production timeline. Additionally, reports suggest that at least one TSMC supplier has abandoned plans to set up operations in Arizona due to workforce-related challenges.

One key takeaway from the ongoing GTC is that Nvidia's AI empire has taken shape with strong partnerships from TSMC and other Taiwanese makers, such as those major server ODMs.

According to the news report from the technology-focused media DIGITIMES Asia, during his keynote at GTC on March 18, Huang underscored his company's partnerships with TSMC, as well as the supply chain in Taiwan. Speaking to the press later, Huang said Nvidia will have a very strong demand for CoWoS, the advanced packaging services TSMC offers.

NVIDIA today announced that TSMC and Synopsys are going into production with NVIDIA's computational lithography platform to accelerate manufacturing and push the limits of physics for the next generation of advanced semiconductor chips. TSMC, the world's leading foundry, and Synopsys, the leader in silicon to systems design solutions, have integrated NVIDIA cuLitho with their software, manufacturing processes and systems to speed chip fabrication, and in the future support the latest-generation NVIDIA Blackwell architecture GPUs.

"Computational lithography is a cornerstone of chip manufacturing," said Jensen Huang, founder and CEO of NVIDIA. "Our work on cuLitho, in partnership with TSMC and Synopsys, applies accelerated computing and generative AI to open new frontiers for semiconductor scaling." NVIDIA also introduced new generative AI algorithms that enhance cuLitho, a library for GPU-accelerated computational lithography, dramatically improving the semiconductor manufacturing process over current CPU-based methods.

ASML celebrated an important milestone last week—the company's social media account shared news about their third generation extreme ultraviolet (EUV) lithography tool reaching an unnamed customer: "chipmakers have a need for speed! The first Twinscan NXE:3800E is now being installed in a chip fab. 🔧 With its new wafer stages, the system will deliver leading edge productivity for printing advanced chips. We're pushing lithography to new limits." The post included a couple of snaps—ASML workers were gathered in front of a pair of climatized containers, and Peter Wennink (President and CEO) and Christophe Fouquet (EVP and CBO) thanked staff at company HQ.

The Twinscan NXE:3800E is ASML's latest platform from a series of 0.33 numerical aperture (Low-NA) lithography scanners. Information is scarce—the company has not yet published a 3800E product page. The preceding model—Twinscan NXE:3600D—supports EUV volume production at 3 and 5 nm. ASML roadmaps imply that the Twinscan NXE:3800E has been designed to produce chips on 2 and 3 nm-class technologies. The company's cutting-edge High-NA extreme ultraviolet (EUV) chipmaking tools (High-NA Twinscan EXE) are expected to cost around $380 million—reports from last month point to a possible $183 million price point for "existing Low-NA EUV lithography systems." Another Low-NA EUV machine is reported to be lined up for a possible 2026 release window—ASML's next-gen Twinscan NXE:4000F model will co-exist alongside emerging (pricier) High-NA solutions.

Intel is revamping its foundry play, and the company is set on its goals of becoming a strong contender to rivals such as TSMC and Samsung. Under Pat Gelsinger's lead, Intel recently split (virtually, under the same company) its units into Intel Product and Intel Foundry. During the SPIE 2024 conference for optics and photonics, Anne Kelleher, Intel's senior vice president, revealed that the 14A (1.4 nm) process offers a 15% performance-per-watt improvement over the company's 18A (1.8 nanometers) process. Additionally, the enhanced 14A-E process boasts a further 5% performance boost from the regular A14 node, being a small refresh. Intel's 14A process is set to be the first to utilize High-NA extreme ultraviolet (EUV) equipment, delivering a 20% increase in transistor logic density compared to the 18A node.

The company's aggressive pursuit of next-generation processes poses a significant threat to Samsung Electronics, which currently holds the second position in the foundry market. As part of its IDM 2.0 strategy, Intel hopes to reclaim its position as a leading foundry player and surpass Samsung by 2030. The company's collaboration with American companies, such as Microsoft, further solidifies its ambitions. Intel has already secured a $15 billion chip production contract with Microsoft for its 1.8 nm 18A process. The semiconductor industry is closely monitoring Intel's progress, as the company's advancements in process technology could potentially reshape the competitive landscape. With Samsung planning to mass-produce 2 nm process products next year, the race for dominance in the foundry market is heating up.

Marvell Technology, Inc., a leader in data infrastructure semiconductor solutions, is extending its collaboration with TSMC to develop the industry's first technology platform to produce 2 nm semiconductors optimized for accelerated infrastructure.

Behind the Marvell 2 nm platform is the company's industry-leading IP portfolio that covers the full spectrum of infrastructure requirements, including high-speed long-reach SerDes at speeds beyond 200 Gbps, processor subsystems, encryption engines, system-on-chip fabrics, chip-to-chip interconnects, and a variety of high-bandwidth physical layer interfaces for compute, memory, networking and storage architectures. These technologies will serve as the foundation for producing cloud-optimized custom compute accelerators, Ethernet switches, optical and copper interconnect digital signal processors, and other devices for powering AI clusters, cloud data centers and other accelerated infrastructure.

A South Korean website, gamma0burst, has combed through many LinkedIn profiles in an attempt to find unintentional technology leaks—last week's investigation targeted big companies including Apple, AMD, Google and Qualcomm. Employee work histories occasionally display confidential project information—gamma0burst's latest "hidden in plain sight" discovery has linked Apple a TSMC 2 nm process node. Late January reports suggested that the American multinational technology corporation was already queued up for an N2 process technology that utilizes gate-all-around (GAA) nanosheet transistors. Information gleaned from a severely redacted screenshot of an Apple employee profile indicates that work has started on 2 nm chip designs, in partnership with Taiwan's premier foundry. Additionally, the portion of revealed text also mentions that this unnamed Apple staffer is/was engaged in "TS3nm" and "TS5nm" designs.

Apple and TSMC's close relationship is well documented—the iPhone/iPad/MacBook maker enjoys preferential access to the latter's best fabrication services. The upcoming M4 and Bionic A18 chipsets have been linked to an "enhanced" 3 nm process node—as mid-February reports suggest. At the time, inside sources proposed that Apple had: "strengthened the AI computing performance of mobile devices and greatly increased the computing power of its own processors, which has simultaneously increased its wafer investment in TSMC. According to industry sources, Apple's wafer production volume for TSMC's 3 nm enhanced version process this year is expected to increase by more than 50% compared with last year, making it firmly the largest customer of TSMC." DigiTimes Asia and MacRumors think that: "Apple is...the first company that will receive chips built on TSMC's future 2 nm process, which is expected to go into production in the second half of 2025. Known simply as 'N2,' it is expected to offer a 10 to 15 percent speed improvement at the same power, or a 25 to 30 percent power reduction at the same speed compared to chips made with the supplier's 3 nm technology."

Samsung and ARM announced a collaborative project last week—the partners are aiming to deliver an "optimized next generation Arm Cortex -X CPU" developed on the latest Gate-All-Around (GAA) process technology. Semiconductor industry watchdogs believe that Samsung Foundry's 3 nm GAA process did not meet sales expectations—reports suggest that many clients decided to pursue advanced three nanometer service options chez TSMC. The South Korean multinational manufacturing conglomerate is setting its sights forward—with an in-progress SF2 GAAFET process in the pipeline—industry insiders reckon that Samsung leadership is hoping to score a major victory within this next-gen market segment.

Lately, important industry figures have been hyping up Backside Power Supply Delivery Network (BSPDN) technology—recent Intel Foundry Services (IFS) press material lays claim to several technological innovations. A prime example being an ambitious five-nodes-in-four-years (5N4Y) process roadmap that: "remains on track and will deliver the industry's first backside power solution." A Chosun Business report proposes that Samsung is working on Backside Power Supply designs—a possible "game changer" when combined with in-house 2 nm SF2 GAAFET. Early experiments, allegedly, involving two unidentified ARM cores have exceeded expectations—according to Chosun's sources, engineers were able to: "reduce the chip area by 10% and 19%, respectively, and succeeded in improving chip performance and frequency efficiency to a single-digit level." Samsung Foundry could be adjusting its mass production timetables, based on freshly reported technological breakthroughs—SF2 GAAFET + BSPDN designs could arrive before the original targeted year of 2027. Prior to the latest developments, Samsung's BSPDN tech was linked to a futuristic 1.7 nm line.

Smartphone chipset industry watchdogs believe that the Samsung 3 nm GAA process did not meet customer expectations, due to alleged yield issues. TSMC is seemingly victorious in this segment, as reports suggest that a next-generation 3 nm node production goal of "100,000 monthly wafers by the end of 2024" has been set. Three days ago, Samsung Foundry revealed that it is working on a very advanced SF2 GAAFET process—press outlets in South Korea propose that the manufacturing giant is hoping to outmuscle its main rival in a future 2 nm node category. Tuesday's press introduction stated that a development partnership is set: "to deliver optimized next generation ARM Cortex -X CPU developed on Samsung Foundry's latest Gate-All-Around (GAA) process technology."

A Sedaily article posits that the company's cutting-edge manufacturing tech has already attracted interest from notable parties: "Samsung Electronics is taking advantage of these advantages to win orders for the 2 nm project. Samsung Electronics took its first step by winning an order to produce a 2 nm AI accelerator from Preferred Networks (PFN), Japan's largest AI company. Qualcomm, the world's largest system semiconductor design company, has entered into discussions with Samsung Electronics' System LSI Division, which designs high-performance chips, to produce 2 nm prototypes." December 2023 news reports suggested that Samsung leadership was considering a 2 nm wafer price discount—in order to stay competitive with competing foundry services. It is possible that Qualcomm is evaluating the 2 nm SF2 GAAFET process for a distant Snapdragon 8 "Gen 5" chipset, while Samsung LSI could be working on a 2 nm "Exynos 2600" SoC design.

The cutting edge 2 nm EUV foundry node by TSMC is expected to enter risk product in Q4 2024, according to a report by Taiwan-based industry observer DigiTimes. 2 nm would be an important milestone for the foundry company, as it would be the first from the company to implement GAA (gates all around) FETs, the technological successor to FinFETs, which drove silicon fabrication node development for almost a decade, from 16 nm to 3 nm. The GAAFET technology will be critical for the foundry's journey between 2 nm and 1 nm.

TSMC is expected to risk-produce chips on its 2 nm node in its new fab at the Baoshan campus in the Hsinchu Science Park, located in northern Taiwan. Should all go well with risk production, one can expect mass production of chips by Q2-2025. Until then, refinements to the company's final FinFET node, the N3 family, will remain the cutting-edge of silicon fabrication. Samsung has a similar 2025 target set for mass production on its 2 nm node, dubbed SF2. Across the Pacific, Intel Foundry Services has its Intel 20A node, which implements GAAFET (aka RibbonFET) technology aiming for similar timelines, including an ambitious 2024 mass production target.

Samsung Electronics foundry has reportedly bagged a mass production order for its cutting edge 2 nm EUV foundry node from Japanese AI chip startup PFN (Preferred Networks). This is reportedly the first major third party order for the 2 nm node. Founded in 2014, PFN specializes in AI and IoT chips, and spun off from Preferred Infrastructure. Samsung's 2 nm node, called the SF2, is on track for delivery of mass produced chips in 2025, which means much of 2024 will be spent on testing, validation, and risk production, with the node expected to go live toward the end of the year. Samsung SF2 is being designed to offer 25% higher power efficiency (at iso-clocks), and 12% increase in performance, over SF3 (3 nm EUV FinFET). In the semiconductor fabrication market, Samsung SF2 competes against TSMC N2 and Intel 20A.

DigiTimes Asia has reached out to insiders at fabrication toolmakers in an effort to delve deeper into claims made by industry analysts at the start of 2024—both SemiAnalysis and China Renaissance have proposed that TSMC is unlikely to adopt High-NA EUV production techniques within a five year period. The latest news article explores a non-upgrade approach for the next couple of years: "TSMC has not placed orders for high-numerical aperture (High-NA) extreme ultraviolet (EUV) tools and is unlikely to use the technology in 2 nm and 1.4 nm (A14) process manufacturing." Intel Foundry Services (IFS) will be one of the first semiconductor manufacturers to go online with ASML's latest and greatest machinery, although no firm timeframes have been confirmed. Team Blue's Taiwanese rival (and occasional business partner) is seemingly happy with its existing infrastructure, but industry watchdogs propose that cost considerations are key factors behind TSMC's cautious planning for the next decade.

The DigiTimes insider sources believe that TSMC will not budge until at least 2029, possibly coinciding with a 1 nm production node—analysts at China Renaissance reckon that High-NA EUV machines could be delivered in the future when facilities are readied for an "A10" codenamed process. TSMC published a very ambitious "transistor count" product timeline in early January (see below)—the first "1 nm" products are supposedly targeted for a 2030 rollout, but this schedule could change due to unforeseen circumstances. Intel is expected to "phase in" its fanciest ASML gear collection once the 18A process becomes old hat—Tom's Hardware thinks that 2026 - 2027 is a feasible timeframe.

This week in its earnings call, Samsung announced that its foundry business has received a significant order for a two nanometer AI chips, marking a major win for its advanced fabrication technology. The unnamed customer has contracted Samsung to produce AI accelerators using its upcoming 2 nm process node, which promises significant gains in performance and efficiency over today's leading-edge chips. Along with the AI chips, the deal includes supporting HBM and advanced packaging - indicating a large-scale and complex project. Industry sources speculate the order may be from a major hyperscaler like Google, Microsoft, or Alibaba, who are aggressively expanding their AI capabilities. Competition for AI chip contracts has heated up as the field becomes crucial for data centers, autonomous vehicles, and other emerging applications. Samsung said demand recovery in 2023 across smartphones, PCs and enterprise hardware will fuel growth for its broader foundry business. It's forging ahead with 3 nm production while eyeing 2 nm for launch around 2025.

Compared to its 3 nm process, 2 nm aims to increase power efficiency by 25% and boost performance by 12% while reducing chip area by 5%. The new order provides validation for Samsung's billion-dollar investments in next-generation manufacturing. It also bolsters Samsung's position against Taiwan-based TSMC, which holds a large portion of the foundry market share. TSMC landed Apple as its first 2 nm customer, while Intel announced 5G infrastructure chip orders from Ericsson and Faraday Technology using its "Intel 18A" node. With rivals securing major customers, Samsung is aggressively pricing 2 nm to attract clients. Reports indicate Qualcomm may shift some flagship mobile chips to Samsung's foundry at the 2 nm node, so if the yields are good, the node has a great potential to attract customers.

A Taiwan Economic Daily news article proposes that a couple of high profile clients are considering TSMC's 2 nanometer process—Apple is widely believed to be the first customer to join the foundry's queue for cutting edge services. The report posits that Intel is also signed up on the Taiwanese firm's 2 nm reservation list—TSMC is expected to start production in 2025—insiders reckon that Team Blue's "Nova Lake" CPU family is the prime candidate here. Its CPU tile is alleged to utilize TSMC 2 nm node. Intel's recent "Core" processor roadmaps do not display any technologies beyond 2025—many believe that "Nova Lake" is pencilled in for a loose 2026 launch window, perhaps within the second half of the year.

The existence of "Nova Lake" was revealed late last year by HWiNFO patch notes—a short entry mentioned preliminary support for the family's integrated GPU. Intel is engaged in hyping up of its own foundry's 20A and 18A processes, but remain reliant on TSMC plants for various bits of silicon. Industry tipsters reckon that aspects of "Lunar Lake" CPUs are based on the Taiwanese foundry's N3B node. Team Blue Corporation and United Microelectronics Corporation (UMC) announced a new development partnership last week, but initial offerings will arrive on a relatively passé "12-nanometer semiconductor process platform." TSMC's very advanced foundry services seem to be unmatched at this juncture.

Japanese tech giant Canon hopes to shake up the semiconductor manufacturing industry by shipping new low-cost nanoimprint lithography (NIL) machines as early as this year. The technology, which stamps chip designs onto silicon wafers rather than using more complex light-based etching like market leader ASML's systems, could allow Canon to undercut rivals and democratize leading-edge chip production. "We would like to start shipping this year or next year...while the market is hot. It is a very unique technology that will enable cutting-edge chips to be made simply and at a low cost," said Hiroaki Takeishi, head of Canon's industrial group overseeing nanoimprint lithography technological advancement. Nanoimprint machines target a semiconductor node width of 5 nanometers, aiming to reach 2 nm eventually. Takeishi said the technology has primarily resolved previous defect rate issues, but success will depend on convincing customers that integration into existing fabrication plants is worthwhile.

There is skepticism about Canon's ability to significantly disrupt the market led by ASML's expensive but sophisticated extreme ultraviolet (EUV) lithography tools. However, if nanoimprint can increase yields to nearly 90% at lower costs, it could carve out a niche, especially with EUV supply struggling to meet surging demand. Canon's NIL machines are supposedly 40% the cost of ASML machinery, while operating with up to 90% lower power draw. Initially focusing on 3D NAND memory chips rather than complex processors, Canon must contend with export controls limiting sales to China. But with few options left, Takeishi said Canon will "pay careful attention" to sanctions risks. If successfully deployed commercially after 15+ years in development, Canon's nanoimprint technology could shift the competitive landscape by enabling new players to manufacture leading-edge semiconductors at dramatically lower costs. But it remains to be seen whether the new machines' defect rates, integration challenges, and geopolitical headwinds will allow Canon to disrupt the chipmaking giants it aims to compete with significantly.

A DigiTimes Asia report posits that TSMC is preparing another VVIP foundry lane for Apple Inc.—insiders claim that the Taiwanese foundry giant is in the process of expanding production capacity into next generation 2 nm nanometer fields. This expensive and time consuming endeavor is only made possible with the reassurance of big customers being added to the foundry's order books. TSMC's 2 nm-class N2, N2P, and N2X process technologies are due in 2025 and beyond (according to recent presentation slides)—these advanced packages are set to drop with all sorts of innovations: nanosheet gate-all-around (GAA) transistors, backside power delivery, and super-high-performance metal-insulator-metal (SHPMIM). According to a DigiTimes source "Apple is widely believed to be the initial client to utilize the (next-gen) process."

Apple and NVIDIA were reported to be ahead of many important clients in the queue for TSMC's 3 nm process nodes, so it is not surprising to see old patterns repeat (according to industry rumors) again. Apple is expected to update its next generation iPhones, iPad, and Mac laptop product lines with more advanced Bionic and M-series chipsets in 2025. Last year's roster included a rollout of 3 nm TSMC silicon across Apple A17 Pro and M3 ARM-based processors.