Responding to investor questions in TSMC's first quarter earnings call for 2022, CEO C. C. Wei reiterated that the company's upcoming manufacturing processes are generally moving smoothly throughout development. Even as TSMC announced historic revenues on the back of increased pricing throughout the semiconductor industry, the company is showing no signs of slowing down on its development. When further asked regarding the company's ability to navigate the world's troubled, inflation-ridden waters, Wei added that TSMC's strategic positioning as the leading semiconductor foundry makes it resilient to market and demand fluctuations.

TSMC's roadmap has seen multiple accelerations of late, which have placed 3 nm tape-out to occur before the end of the year. Perhaps more significantly, the company's next-generation 2 nm manufacturing process, which will make use of GAA (Gate All Around) transistor designs for greater design efficiency and density, are still on track for a 2025 volume production following an expected 2024 tape-out.

While there's a lot of talk about cutting edge nodes, Samsung Foundries are looking at alternative options to find new business and are said to be eyeing legacy nodes for future expansions. At the same time, Samsung is looking at setting up its own chip testing and packaging factory, to be able to better serve customers who are looking for a full-service partner. It's not clear which legacy nodes Samsung are eyeing, but the story by Business Korea states that at least some of it will focus on CMOS imaging sensors, since there is apparently a shortage of those too.

Samsung is said to have plans for no less than 300 new customers by 2026 for its foundry business, across all nodes. However, this doesn't mean Samsung will stop developing new, cutting edge nodes, as Samsung is still planning to kick off volume production on its 3 nm node in the first half of this year, with 2 nm said to start volume production in 2025. After its dealings with Nvidia and Qualcomm that haven't been what you'd call successful, the question is who will be willing to partner with Samsung Foundry on its cutting edge nodes in the future.

Intel and TSMC are positioning themselves as two competing foundries for a significant period. However, as the difficulties in semiconductor manufacturing rise, the collaboration of the two seems inevitable. Not because Intel is eyeing TSMC's clients, but because of the race to produce the most minor and best possible semiconductor node. We already know that Intel plans to use some of TSMC's nodes for its Ponte Vecchio accelerator that contains 47 tiles. However, we didn't realize just how big the contract between the two companies was. According to the latest report from DigiTimes, Intel is supposed to become one of the top three clients at TSMC.

As the report notes, the collaboration should extend to at least TSMC's 2 nm node, expected in 2025. After that, the state of semiconductors is unknown. Intel has a solid chance to be in the top three customers in 2023 and become one of the primary sources of profit for the Taiwanese giant. We are excited to see how this prediction plays out and hope to hear more from both in the future.

Samsung Electronics, a world leader in advanced semiconductor technology, today unveiled plans for continuous process technology migration to 3- and 2-nanometer (nm) based on the company's Gate-All-Around (GAA) transistor structure at its 5th annual Samsung Foundry Forum (SFF) 2021. With a theme of "Adding One More Dimension," the multi-day virtual event is expected to draw over 2,000 global customers and partners. At this year's event, Samsung will share its vision to bolster its leadership in the rapidly evolving foundry market by taking each respective part of foundry business to the next level: process technology, manufacturing operations, and foundry services.

"We will increase our overall production capacity and lead the most advanced technologies while taking silicon scaling a step further and continuing technological innovation by application," said Dr. Siyoung Choi, President and Head of Foundry Business at Samsung Electronics. "Amid further digitalization prompted by the COVID-19 pandemic, our customers and partners will discover the limitless potential of silicon implementation for delivering the right technology at the right time."

"Moore's Law is alive and well," says ASML, in its vision document addressing investors. The company manufactures the machines that perform the actual task of silicon lithography—turning silicon discs into wafers of logic or storage chips. It highlighted the various technologies making progress, which will help its semiconductor-fabrication customers, such as TSMC and their hundreds of clients, sustain Moore's Law all the way through this decade. The company predicts SoCs with as many as 300 billion transistors by 2030. To achieve this, the company is innovating in two distinct directions—at the chip-level, to increase transistor density per chip to over 50 billion transistors; and at the system level, through packaging technology innovations, to reach that ultimate transistor count.

According to ASML's roadmap, at the turn of the decade, its technology enables 5 nm-class in production, and is at the cusp of a major breakthrough, nanosheet-FETs. which pave the way for 3 nm and 2 nm nodes, backed by EUV lithography. The journey from 2 nm to 1.5 nm will require another breakthrough, forked-nanosheets, and from 1.5 nm to 1 nm yet another breakthrough, CFET. Sub-1 nm fabrication will be possible toward the turn of this decade, thanks to 2D atomic channel technology, which is how chip-designers will be able to cram over 50 billion transistors per chip, and build MCM systems with over 300 billion transistors. The presentation predicts that besides 3D packaging, stacked silicon will also play a role, with multiple stacked logic layers, heterogenous chips with logic, storage, and I/O layers, stacked DRAM (up from single-digit layers to double-digits; and for NAND flash to grow from the current 176-layer, to nearly 500-layer by 2030.

At the annual Hot Chips conference, IBM (NYSE: IBM) today unveiled details of the upcoming new IBM Telum Processor, designed to bring deep learning inference to enterprise workloads to help address fraud in real-time. Telum is IBM's first processor that contains on-chip acceleration for AI inferencing while a transaction is taking place. Three years in development, the breakthrough of this new on-chip hardware acceleration is designed to help customers achieve business insights at scale across banking, finance, trading, insurance applications and customer interactions. A Telum-based system is planned for the first half of 2022.

Today, businesses typically apply detection techniques to catch fraud after it occurs, a process that can be time consuming and compute-intensive due to the limitations of today's technology, particularly when fraud analysis and detection is conducted far away from mission critical transactions and data. Due to latency requirements, complex fraud detection often cannot be completed in real-time - meaning a bad actor could have already successfully purchased goods with a stolen credit card before the retailer is aware fraud has taken place.

Intel, in a move comparable to its competitors' Performance Rating system from the 1990s, has invented a new naming scheme for its in-house foundry nodes to claim technological parity with contemporaries such as TSMC and Samsung, that are well into the sub-10 nm class. Back in the i586 era, when Intel's competitors such as AMD and Cyrix, couldn't keep up with its clock-speeds yet found their chips to be somewhat competitive, they invented the PR (processor rating) system, with a logical number attempting to denote parity with an Intel processor's clock-speed. For example, a PR400 processor rating meant that the chip rivaled a Pentium II 400 MHz (which it mostly didn't). The last that the PR system made sense was with the final generation of single-core performance chips, Pentium 4 and Athlon XP, beyond which, the introduction of multi-core obfuscated the PR system. A Phenom X4 9600 processor didn't mean performance on par with a rival Intel chip running at an impossible 9.60 GHz.

Intel's new foundry naming system sees its 10 nm Enhanced SuperFin node re-badge as "Intel 7." The company currently builds 11th Gen Core "Tiger Lake" processors on the 10 nm SuperFin node, and is expected to build its upcoming 12th Gen Core "Alder Lake" chips on its refinement, the 10 nm Enhanced SuperFin, which will now be referred to as "Intel 7." The company is careful to avoid using the nanometer unit next to the number, instead signaling the consumer that the node somehow offers transistor density and power characteristics comparable to a 7 nm node. Intel 7 offers a 10-15 percent performance/Watt gain over 10 nm SuperFin, and is already in volume production, with a debut within 2021 with "Alder Lake."

NVIDIA is reported to be cutting down on production of its highly popular RTX 2060 graphics card, in a bid to increase production of the RTX 30-series graphics cards that still elude most consumers looking to get one on their gaming rig. The decision may be motivated by increased margins on RTX 30-series products, as well as by the continuing component shortage in the industry, with even GDDR6 becoming a limiting factor to production capability.

While one might consider this a strange move at face value (Turing is manufactured on TSMC's 12 nm node, whilst Ampere is manufactured on Samsung's 8 nm), the fact of the matter is that there are a multitude of components required for GPUs besides the graphics processing silicon proper; and NVIDIA essentially sells ready-to-produce kits to AICs (Add-in-Card Partners) which already include all the required components, circuitry, and GPU slice to put together. And since supply on most components and even simple logic is currently strained, every component in an RTX 2060-allocated kit could be eating into final production capacity for the RTX 30-series graphics cards - hence the decision to curb the attempt to satiate pent-up demand with a last-generation graphics card and instead focusing on current-gen hardware.

IBM today unveiled a breakthrough in semiconductor design and process with the development of the world's first chip announced with 2 nanometer (nm) nanosheet technology. Semiconductors play critical roles in everything from computing, to appliances, to communication devices, transportation systems, and critical infrastructure.

Demand for increased chip performance and energy efficiency continues to rise, especially in the era of hybrid cloud, AI, and the Internet of Things. IBM's new 2 nm chip technology helps advance the state-of-the-art in the semiconductor industry, addressing this growing demand. It is projected to achieve 45 percent higher performance, or 75 percent lower energy use, than today's most advanced 7 nm node chips.

European Union has today processed a declaration that was signed by 17 member states about the development of a 2 nm semiconductor node and an advanced low-power processor. The declaration signed today proposes that the EU puts away 145 billion Euros for the development of the technologies needed to manufacture a 2 nm semiconductor manufacturing process, along with the development of a custom, low-power embedded processor designed for industrial applications. The 17 member countries include Belgium, France, Germany, Croatia, Estonia, Italy, Greece, Malta, Spain, The Netherlands, Portugal, Austria, Slovenia, Slovakia, Romania, Finland, and Cyprus. All of the countries listed are going to join the development of these technologies and will have the funds to do it over the next 2-3 years.

EU DeclarationTo ensure Europe's technology sovereignty and competitiveness, as well as our capacity to address key environmental and societal challenges and new emerging mass markets, we need to strengthen Europe's capacity to develop the next generation of processors and semiconductors. This includes chips and embedded systems that offer the best performance for specific applications across a wide range of sectors as well as leading-edge manufacturing progressively advancing towards 2 nm nodes for processor technology. Using connectivity, where Europe enjoys global lead, as a major use case driver for developing such capacity enables Europe to set the right level of ambition. This will require a collective effort to pool investment and to coordinate actions, by both public and private stakeholders.

The Taiwan Economic Daily claims that TSMC has achieved a major internal breakthrough for the eventual rollout of 2 nm fabrication process technology. According to the publication, this breakthrough has turned TSMC even more optimistic towards a 2023 rollout of 2 nm risk production - which is all the more impressive considering reports that TSMC will be leaving the FinFet realm for a new multi-bridge channel field effect transistor (MBCFET) architecture - itself based on the Gate-All-Around (GAA) technology. This breakthrough comes one year after TSMC put together an internal team whose aim was to pave the way for 2 nm deployment.

MBCFET expands on the GAAFET architecture by taking the Nanowire field-effect transistor and expanding it so that it becomes a Nanosheet. The main idea is to make the field-effect transistor three-dimensional. This new complementary metal oxide semiconductor transistor can improve circuit control and reduce leakage current. This design philosophy is not exclusive to TSMC - Samsung has plans to deploy a variant of this design on their 3 nm process technology. And as has been the norm, further reductions in chip fabrication scale come at hefty costs - while the development cost for 5 nm has already achieved $476M in cost, Samsung reports that their 3 nm GAA technology will cost in excess of $500M - and 2 nm, naturally, will come in even costlier than that.

TSMC, the leading semiconductor foundry in the world, has reportedly begun construction of its 2 nm manufacturing facility. According to a DigiTimes report, translated by @chiakokhua on Twitter, besides the construction of 2 nm R&D center, TSMC has also started the construction of the manufacturing facility for that node, so it will be ready in time. Please do note that the node name doesn't represent the size of the transistor, so it will not actually be 2 nm wide. The new facilities will be located near TSMC's headquarters in Hsinchu Science Park, Taiwan. The report also confirms the first details about the node, specifically that it will use Gate-All-Around (GAA) technology. And there is also another interesting piece of information regarding even smaller node, the planning for 1 nm node has begun according to the source.

Besides advanced nodes, TSMC also laid out clear plans to accelerate the push of advanced packaging technology. That includes SoIC, InFO, CoWoS, and WoW. All of these technologies are classified as "3D Fabric" by the company, even though some are 2.5D. These technologies will be mass-produced at "ZhuNan" and "NanKe" facilities starting in the second half of 2021, and are expected to significantly contribute to the company's profits. It is also reported that the competing foundry, Samsung, has a 3D packaging technology of its own called X-cube, however, it is attracting customers a lot slower than TSMC due to the high costs of the new technology.

TSMC, the world's leading semiconductor manufacturing company, has reportedly started to accelerate research and development (R&D) of its next-generation 2 nm node. Having just recently announced that they will be starting production of a 5 nm process in Q4 of 2020, TSMC is pumping out nodes very fast and much faster compared to competition like Intel and Samsung. Having an R&D budget of almost 16 billion USD, TSMC seems to be spending the funds very wisely. The 5 nm node is going into volume production this year, and smaller nodes are already being prepared.

The 3 nm node is going into trial production in the first half of 2021, while the mass production is supposed to commence in 2022. As far as the 2 nm node, TSMC has recently purchased more expensive Extreme Ultra-Violet (EUV) lithography machines for the 2 nm node. Due to the high costs of these EUV machines, TSMC's capital spending will not be revisited this year and it should remain in the $16 billion range. As far as a timeline for 2 nm is concerned, we don't know when will TSMC start trial production as the node is still in development phases.

A report via DigiTimes places TSMC as having announced to its investors that exploratory studies and R&D for the development of the 2 nm process node have commenced. As today's leading semiconductor fabrication company, TSMC doesn't seem to be one resting on its laurels. Their 7 nm process and derivatives have already achieved a 30% weight on the company's semiconductor orders, and their 5 nm node (which will include EUV litography) is set to hit HVM (High Volume Manufacturing) in Q2 of this year. Apart from that, not much more is known on 2 nm.

After 5 nm, which is expected to boats of an 84-87% transistor density gain over the current 7nm node, the plans are to go 3nm, with TSMC expecting that node to hit mass production come 2022. Interestingly, TSMC is planning to still use FinFET technology for its 3 nm manufacturing node, though in a new GAAFET (gate-all-around field-effect transistor) technology. TSMC's plans to deploy FinFET in under 5nm manufacturing is something that many industry analysts and specialist thought extremely difficult to achieve, with expectations for these sub-5nm nodes to require more exotic materials and transistor designs than TSMC's apparent plans