Friday, April 24th 2020
DigiTimes: TSMC Kicking Off Development of 2nm Process Node
A report via DigiTimes places TSMC as having announced to its investors that exploratory studies and R&D for the development of the 2 nm process node have commenced. As today's leading semiconductor fabrication company, TSMC doesn't seem to be one resting on its laurels. Their 7 nm process and derivatives have already achieved a 30% weight on the company's semiconductor orders, and their 5 nm node (which will include EUV litography) is set to hit HVM (High Volume Manufacturing) in Q2 of this year. Apart from that, not much more is known on 2 nm.
After 5 nm, which is expected to boats of an 84-87% transistor density gain over the current 7nm node, the plans are to go 3nm, with TSMC expecting that node to hit mass production come 2022. Interestingly, TSMC is planning to still use FinFET technology for its 3 nm manufacturing node, though in a new GAAFET (gate-all-around field-effect transistor) technology. TSMC's plans to deploy FinFET in under 5nm manufacturing is something that many industry analysts and specialist thought extremely difficult to achieve, with expectations for these sub-5nm nodes to require more exotic materials and transistor designs than TSMC's apparent plans
Sources:
DigiTimes, via Tom's Hardware
After 5 nm, which is expected to boats of an 84-87% transistor density gain over the current 7nm node, the plans are to go 3nm, with TSMC expecting that node to hit mass production come 2022. Interestingly, TSMC is planning to still use FinFET technology for its 3 nm manufacturing node, though in a new GAAFET (gate-all-around field-effect transistor) technology. TSMC's plans to deploy FinFET in under 5nm manufacturing is something that many industry analysts and specialist thought extremely difficult to achieve, with expectations for these sub-5nm nodes to require more exotic materials and transistor designs than TSMC's apparent plans
17 Comments on DigiTimes: TSMC Kicking Off Development of 2nm Process Node
Samsung: We'll have 5nm chips ready by the end of the year, and 3nm is already in the plans.
TSMC: We have already developed the process of 6nm, 5nm, 5nm+, 3nm and 2nm. All will be available in bulk in up to 2 years.
Intel left the group.
1. It's just marketing for N2.
2. At such dimensions, I think they will find it pretty tricky to control the electrons.
TSMC 16nm => ~20-nm Leff (20nm node)
TSMC N7 => ~14-nm Leff (14nm node)
GloFo 14nm => ~20-nm Leff (20nm node)
GloFo 7LP => ~16-nm Leff (16nm node)
5nm should be >10-nm Leff (>10nm node)
3nm should be >7-nm Leff (>7nm node)
2nm should be >5-nm Leff (>5nm node)
Research of transistor structures indicate that standard FINFET will likely end at 3nm unless TSMC is able to work some magic as indicated in this article. Carbon nanotubes, nanosheets, gate all around FETs could be the next big thing in the world of semiconductors. When I was writing a research paper on this stuff in my semiconductor materials class I predicted GAAFETs would be the next iteration for transistors simply because it only marginally increases the manufacturing complexity of transistor, where as carbon nanotubes/sheets make for much more complex process and a lot more expensive. Hell even from Planar to FINFET the complexity of fabrication went way up since there are a lot more places now for problems to arise. Dimensions of the channel and gate have very little room for variation or the transistor will not function at all.