Earlier in the week, Apple specialist press outlets picked up on a noted industry analyst's technological forecast for a future iPhone processor design. Jeff Pu—of GF Industries, Hong Kong—predicted that the next-generation A20 SoC would be produced via a TSMC 3 nm (N3P) nodes process. Despite rumors of Apple gaining front row seats at the "2 nm ballgame," the partnership between fabless chip designer and foundry could potentially revisit already covered ground. The A19 chipset was previously linked to N3P (by insiders), with Pu expressing the belief that A20 would utilize the same fundamental lithographic underpinnings; albeit enhanced with TSMC's Chip on Wafer on Substrate (CoWoS) packaging technology (for AI improvements).

This morning, MacRumors followed up on their initial news article—they reported that "wires were crossed" at GF Industries, regarding projections for the (2026) iPhone 18 generation. The publication received direct feedback from the man of the hour: "Jeff Pu (lead Apple analyst) has since clarified that he believes the A20 chip will be manufactured with the N2 process, so the information about the chip using the N3P process should be disregarded. Earlier reports had said the A20 chip would be 2 nm, so rumors align again. This is ultimately good news, as it means the A20 chip should have more substantial performance and power efficiency improvements over the A19 chip." Cutting-edge smartphone processor enthusiasts expressed much disappointment when A20 was (regressively) linked to N3P; the latest revisement should instill some joy. According to industry moles, TSMC is making good progress with its cutting-edge 2 nm node process—mass production is expected to start at some point within the second half of 2025.

AMD's next-generation Zen 6-based "Medusa Point" mobile APUs will not feature RDNA 4 graphics as previously speculated, according to recent code discoveries in AMD GPUOpen Drivers on GitHub. The Device ID "GfxIp12" associated with RDNA 4 architecture has been reserved only for discrete GPUs, confirming that the current Radeon RX 9000 series will exclusively implement AMD's latest graphics architecture. Current technical documentation indicates AMD will instead extend RDNA 3.5 implementation beyond the Zen 5 portfolio while potentially positioning UDNA as the successor technology for integrated graphics.

The chiplet-based Medusa Point design will reportedly pair a single 12-core Zen 6 CCD manufactured on TSMC's 3 nm-class node with a mobile client I/O die likely built on N4P. This arrangement is significantly different from current monolithic mobile solutions. Earlier speculation indicates the Medusa Point platform may support 3D V-Cache variants, leveraging the same vertical stacking methodology employed in current Zen 5 implementations. The mobile processor's memory controllers and neural processing unit are expected to receive substantial updates. However, compatibility limitations with AMD's latest graphics features, like FSR 4 technology, remain a concern due to the absence of RDNA 4 silicon. The Zen 6-powered Medusa Point processor family is scheduled for release in 2026, targeting premium mobile computing applications with a performance profile that builds upon AMD's current Strix Halo positioning.

Over a year ago, industry watchdogs posited that Apple was patiently waiting in line at the front of TSMC's 2 Nanometer GAA "VVIP queue." The securing of cutting-edge manufacturing processes seems to be a consistent priority for the Cupertino, California-headquartered fabless chip designer. Current generation Apple chipsets—at best—utilize TSMC 3 nm (N3E) wafers. Up until very recently, many insiders believed that the projected late 2026 launch of A20 SoC-powered iPhone 18 smartphones would signal a transition to the Taiwanese foundry's advanced 2 nm (N2) node process. Officially, TSMC has roadmapped the start of 2 nm mass production around the second half of 2025.

According to Jeff Pu—a Hong Kong-based analyst at GF Securities—the speculated A20 (2026) chipset could stick with N3P. Leaks suggest that aspects of Apple's next in line "A19" and "A19 Pro" mobile SoCs could be produced via a 3 nm TSMC process. MacRumors has picked up on additional inside track whispers; about Apple M5 processors (for next-gen iPad Pro models) being based on N3P—"likely due to increased wafer costs." Pu reckons that Apple's engineering team has provisioned a major generational improvement with A20's AI capabilities, courtesy of TSMC's Chip on Wafer on Substrate (CoWoS) packaging technology. This significant upgrade is touted to tighten integration between the chip's processor, unified memory, and Neural Engine segments. Revised insider forecasts have positioned A21 chip designs as natural candidates for a shift into 2 nm GAA territories.

Global Unichip Corp. (GUC), the Advanced ASIC Leader, today announced the successful launch of industry's first Universal Chiplet Interconnect Express (UCIe) PHY silicon, achieving a data rate of 32 Gbps per lane, the highest speed defined in the UCIe specification. The 32G UCIe IP, supporting UCIe 2.0, delivers an impressive bandwidth density of 10 Tbps per 1 mm of die edge (5 Tbps/mm full-duplex). This milestone was achieved using TSMC's advanced N3P process and CoWoS packaging technologies, targeting AI, high-performance computing (HPC), xPU, and networking applications.

In this test chip, several dies with North-South and East-West IP orientations are interconnected through CoWoS interposer. The silicon measurements show robust 32 Gbps operation with wide horizontal and vertical eye openings. GUC is working aggressively on the full-corner qualification, and the complete silicon report is expected to be available in the coming quarter.

Scientists from Beijing University have developed the world's first two-dimensional gate-all-around field-effect transistor (GAAFET), establishing a new performance benchmark in domestic semiconductor design. The design, documented in Nature, represents a difference in transistor architecture that could reshape the future of Chinese microelectronics design. Given the reported characteristic of 40% higher performance and 10% improved efficiency compared to the TSMC 3 nm N3 node, it looks rather promising. The research team, headed by Professors Peng Hailin and Qiu Chenguang, engineered a "wafer-scale multi-layer-stacked single-crystalline 2D GAA configuration" that demonstrated superior performance metrics when benchmarked against current industry leaders. The innovation leverages bismuth oxyselenide (Bi₂O₂Se), a novel semiconductor material that maintains exceptional carrier mobility at sub-nanometer dimensions—a critical advantage as the industry struggles to push angstrom-era semiconductor nodes.

"Traditional silicon-based transistors face fundamental physical limitations at extreme scales," explained Professor Peng, who characterized the technology as "the fastest, most efficient transistor ever developed." The 2D GAAFET architecture circumvents the mobility degradation that plagues silicon in ultra-small geometries, allowing for continued performance scaling beyond current nodes. The development comes during China's intensified efforts to achieve semiconductor self-sufficiency, as trade restrictions have limited access to advanced lithography equipment and other critical manufacturing technologies. Even with China developing domestic EUV technology, it is still not "battle" proven. Rather than competing directly with established fabrication processes, the Beijing team has pioneered an entirely different technological approach—what Professor Peng described as "changing lanes entirely" rather than seeking incremental improvements, where China can not compete in the near term.

China's domestic extreme ultraviolet (EUV) lithography development is far from a distant dream. The newest system, now undergoing testing at Huawei's Dongguan facility, leverages laser-induced discharge plasma (LDP) technology, representing a potentially disruptive approach to EUV light generation. The system is scheduled for trial production in Q3 2025, with mass manufacturing targeted for 2026, potentially positioning China to break ASML's technical monopoly in advanced lithography. The LDP approach employed in the Chinese system generates 13.5 nm EUV radiation by vaporizing tin between electrodes and converting it to plasma via high-voltage discharge, where electron-ion collisions produce the required wavelength. This methodology offers several technical advantages over ASML's laser-produced plasma (LPP) technique, including simplified architecture, reduced footprint, improved energy efficiency, and potentially lower production costs.

The LPP method relies on high-energy lasers and complex FPGA-based real-time control electronics to achieve the same result. While ASML has refined its LPP-based systems over decades, the inherent efficiency advantages of the LDP approach could accelerate China's catch-up timeline in this critical semiconductor manufacturing technology. When the US imposed sanctions on EUV shipments to Chinese companies, the Chinese semiconductor development was basically limited as standard deep ultraviolet (DUV) wave lithography systems utilize 248 nm (KrF) and 193 nm (ArF) wavelengths for semiconductor patterning, with 193 nm immersion technology representing the most advanced pre-EUV production technique. These longer wavelengths contrast with EUV's 13.5 nm radiation, requiring multiple patterning techniques to achieve advanced nodes.

On Wednesday (February 19), Apple announced the upcoming launch of its "budget-friendly" iPhone 16e smartphone model. The Cupertino, California-based company has refreshed its entry level product tier—starting at $599—with modernized internals. Apple's new design houses an A18 chipset, as well as their much-discussed debut modem design. The C1 is a custom 5G part; fully developed in-house. Previously, modern iPhone product ranges have been fitted with Qualcomm 5G modems. As expected, Apple contracted with TSMC for the production of A18 and C1 silicon—the A-type SoC is based on a 3 nm process node (TSMC N3E). Their proprietary modem baseband design utilizes 4 mm, while the receiver uses a 7 nm process—according to insiders.

Taiwan's Commercial Times reckons that TSMC will be the "biggest beneficiary" from the aforementioned agreement with Apple. Ctee TW's latest report cites industry analysis; soothsayers estimate annual shipments reaching roughly 22 million units annually. Additional whispers suggest that the C1 modem will turn up in non-iPhone devices—namely next-gen Watches and iPads, by next year. The report also mentions that upcoming Mac products are slated for C1 upgrades. Further leaks have linked project "Ganymede" to a "C2" custom 5G modem design—inside sources believe that a 3 nm TSMC process is on the cards. Another codename—"Prometheus"—was leaked by insiders; possibly referencing a future "C3" model.

The late 2024 news cycle suggested that Samsung's semiconductor business was going through tough times. Alleged yield problems—affecting the 3 nm Gate-All-Around (GAA) process—were highlighted last November. Fast-forward to January 2025; the South Korean megacorp has launched its cutting-edge Galaxy S25 smartphone series. The entire lineup of newly unveiled flagship smartphones contains Qualcomm's Snapdragon 8 Elite mobile chipsets; the Southern Californian chip designer is reportedly pulling in a tidy sum from this partnership. Fresh reports from South Korean news outlets indicate that Samsung System LSI employees have received an "encouraging" email from their boss, regarding current production predicaments.

Businesskorea and Sedaily reports include quotes extracted from the (apparently) leaked internal memo. LSI division president, Park Yong-in, reportedly stated: "we are currently in a situation where we have to develop two flagship products at the same time." Both articles allege that Samsung's semiconductor teams are expected to "cultivate roots and withstand storms." Industry watchdogs believe that the aforementioned "flagship products" are the Exynos 2500 mobile chipset, and Samsung Electronic's next-gen Galaxy S26 smartphone family. Earlier this month, we heard whispers about the much-delayed in-house chip design being readied (with a 2 nm process) for a possible late 2025 launch, inside unannounced Galaxy Z Flip 7 and Fold 7 devices. Park disclosed anticipated incoming obstacles in 2025: "last year's business division profit was higher than expected, but this was a temporary phenomenon...Looking at the entire business division, there will be monthly surpluses and deficits." Last month, inside sources proposed the notion that foundry investments were slashed in half.

AMD is readying two important client segment processors powered by the next-generation "Zen 6" microarchitecture, according to a sensational new report by Moore's Law is Dead. These are the "Medusa Point" mobile processor, and the "Olympic Ridge" desktop. The former is a BGA roughly the size and Z-Height of the current "Strix Point," but the latter is being designed for the existing Socket AM5, making it the third (and probably final) microarchitecture to do so. If you recall, Socket AM4 served three generations of Zen, not counting the refreshed "Zen+." At the heart of the effort is a new CPU complex die (CCD) that AMD plans to use across its client and server lineup.

The "Zen 6" performance CCD is being designed for a 3 nm-class node, likely the TSMC N3E. This node promises a significant increase in transistor density, power, and clock speed improvements over the current TSMC N4P node being used to build the "Zen 5" CCD. Here's where it gets interesting. The CCD contains twelve full-sized "Zen 6" cores, marking the first increase in core-counts of AMD's performance cores since its very first "Zen" CCD. All 12 of these cores are part of a single CPU core complex (CCX), and share a common L3 cache. There could be a proportionate increase in cache size to 48 MB. AMD is also expected to improve the way the CCDs communicate with the I/O die and among each other.

TSMC has unveiled today its board meeting decisions, the chip giant has greenlit a massive US$17 billion investment to boost production capacity. According to TSMC, to meet long-term capacity plans based on market demand forecasts and TSMC's technology development roadmap, the board approved capital appropriations of approximately US$17.14 billion for installation and upgrade of advanced technology capacity, installation and upgrade of advanced packaging, mature and/or specialty technology capacity, fab construction, and installation of fab facility systems.

Previous reports by MoneyDJ suggested that TSMC might unveil plans for a third Arizona fab, a potential fourth fab, or its first advanced packaging plant after the board meeting. However, no updates have been confirmed yet. Industry sources suggested that TSMC's second Arizona fab, featuring 3 nm, will likely go ahead of schedule, providing a temporary response to U.S. pressures. According to the same report, TSMC's second Arizona fab is expected to begin equipment installation in mid-2026, with mass production expected by 2027. Notably, this progress would exceed TSMC's projections which expected the second plant to start 3 nm and 2 nm production in 2028, with a third plant potentially for the 2 nm process by the late 2030s. The MoneyDJ report further notes that initially, TSMC's second Arizona plant will offer 25K-30K 3 nm wafers per month. TSMC's first Arizona plant, initially slated for 2025, started 4 nm production ahead of schedule in Q4 2024.

AMD is rumored to be building its next-generation CCD (core complex die) that implements the "Zen 6" microarchitecture, on the 3 nm TSMC N3E foundry node. This is part of a set of rumors from ChipHell forum, which got past rumors on AMD right. Apparently, AMD will also refresh the I/O dies for its next generation process, building them on the 4 nm foundry node, likely the TSMC N4C. The TSMC N3E node offers a 20% speed improvement, over 30% power savings, and approximately 60% logic density increase over TSMC N5, whereas the TSMC N4P node that the company uses for its current "Zen 5" chiplets only clock minor increases in logic density and power over N5. The N3E node relies on EUV double-patterning to achieve its logic density increases.

Perhaps the most interesting piece of news is the new-generation I/O dies. AMD is building these on the 4 nm node, which is a significant step up from the 6 nm node its current I/O dies are built on. On the client side of things, 4 nm will enable AMD to give the new cIOD an updated iGPU, probably based on a newer graphics architecture, such as RDNA 3.5. It will also give AMD the opportunity to integrate an NPU. The company might also update its key I/O components, such as the DDR5 memory controllers, to support higher memory speeds unlocked by CUDIMMs. We don't predict any updates on the PCIe front, since AMD is expected to carry on with Socket AM5, which determines that the cIOD puts out 28 PCIe Gen 5 lanes. At best, the USB interface put out from the processor could be updated to USB4 through an on-die host controller. Over on the server side, the new-generation sIOD will bring much needed increases to the DDR5 memory speeds enabled by clock drivers.

Samsung's native foundry operations have wrestled with the 3 nm Gate-All-Around (GAA) process—these problems have persisted since the first reports of "missed production targets" emerged late last year—online speculators floated a very disappointing yield figure: only 20%. Last December, industry moles proposed that the South Korean technology giant had devised plans to form an Exynos-centric "multi-channel partnership" with rival chipmakers. Speculation pointed to TSMC being the only valid ally. Semiconductor industry tipster—Jukanlosreve—believes that negotiations have taken place, and the answer was a firm "no." TSMC's most advanced node process order books are likely filled up with more important customers—industry watchdogs reckon that Apple usually gets first dibs.

Taiwan's top semiconductor manufacturer leads the market with its cutting-edge lithography techniques. Insiders believe that Samsung was impressed by TSMC's 2 nm trial production runs achieving (rumored) 60% yields. The higher-end Exynos chipsets are normally produced with the best node process available, but missed manufacturing goals have caused Samsung to drop in-house tech. In the recent past, Qualcomm's most powerful Snapdragon mobile chipsets have been deployed on flagship Galaxy S smartphones. Jukanlosreve believes that TSMC rejected Samsung's proposed Exynos deal due to a fear of revealing too many "trade secrets." Potentially, the South Koreans could have learned a thing or two about improving yields—courtesy of TSMC's expert knowledge.

TSMC (TWSE: 2330, NYSE: TSM) today announced consolidated revenue of NT$868.46 billion, net income of NT$374.68 billion, and diluted earnings per share of NT$14.45 (US$2.24 per ADR unit) for the fourth quarter ended December 31, 2024. Year-over-year, fourth quarter revenue increased 38.8% while net income and diluted EPS both increased 57.0%. Compared to third quarter 2024, fourth quarter results represented a 14.3% increase in revenue and a 15.2% increase in net income. All figures were prepared in accordance with TIFRS on a consolidated basis.

In US dollars, fourth quarter revenue was $26.88 billion, which increased 37.0% year-over-year and increased 14.4% from the previous quarter. Gross margin for the quarter was 59.0%, operating margin was 49.0%, and net profit margin was 43.1%. In the fourth quarter, shipments of 3-nanometer accounted for 26% of total wafer revenue; 5-nanometer accounted for 34%; 7-nanometer accounted for 14%. Advanced technologies, defined as 7-nanometer and more advanced technologies, accounted for 74% of total wafer revenue.

Alphawave Semi (LSE: AWE), a global leader in high-speed connectivity and compute silicon for the world's technology infrastructure, proudly introduces the industry's first 64 Gbps Universal Chiplet Interconnect Express (UCIe) Die-to-Die (D2D) IP Subsystem to deliver unprecedented chiplet interconnect data rates, setting a new standard for ultra-high-performance D2D connectivity solutions in the industry. The third generation, 64 Gbps IP Subsystem builds on the successes of the most recent Gen 2 36 Gbps IP subsystem and silicon-proven Gen 1 24 Gbps and is available in TSMC's 3 nm Technology for both Standard and Advanced packaging. The silicon proven success and tapeout milestones pave the way for Alphawave Semi's Gen 3 UCIe IP subsystem offering.

Alphawave Semi is set to revolutionize connectivity with its Gen 3 64 Gbps UCIe IP, delivering a bandwidth density of over 20 Tbps/mm, with ultra-low power and latency. This solution is highly configurable supporting multiple protocols, including AXI-4, AXI-S, CXS, CHI and CHI-C2C to address the growing demands for high-performance connectivity across disaggregated systems in High-Performance Computing (HPC), Data Centers, and Artificial Intelligence (AI) applications.

Rapidus Corporation, a manufacturer of advanced logic semiconductors, today announced the delivery and installation of ASML's EUV lithography equipment at its Innovative Integration for Manufacturing (IIM-1) foundry, an advanced semiconductor development and manufacturing fab currently under construction in Chitose, Hokkaido. To commemorate the installation, a ceremony was held at Portom Hall in the New Chitose Airport.

This is a significant milestone for Japan's semiconductor industry, marking the first time that an EUV lithography tool will be used for mass production in the country. In addition to the EUV lithography machinery, Rapidus will install additional complementary advanced semiconductor manufacturing equipment, as well as full automated material handling systems in its IIM-1 foundry to optimize 2 nm generation gate-all-around (GAA) semiconductor manufacturing.

According to a recent report by seasoned industry analyst Ming-Chi Kuo, the M5-powered iPad Pro is set to enter mass-production towards the latter half of next year. This falls in line with previous information that came courtesy of supply chain sources.

Apple revealed the M4 SoC alongside the OLED iPad Pro refresh in May of this year, which was quite a surprise considering that this was the first time Apple chose to unveil a new M-series SoC in an iPad instead of a Mac. This trend appears poised to continue, with the 2025 iPad Pro as well. Interestingly, Apple is seemingly switching up its release schedule yet again, barely managing to stick to a uniform 12-month cycle. The M3 followed the M2 after almost 16 months, while the M4 replaced the M3 in just 6 months.

SK Hynix plans to produce its 6th generation high-bandwidth memory chips (HBM4) using TSMC's 3 nm process, a change from initial plans to use the 5 nm technology. The Korea Economic Daily reports that these chips will be delivered to NVIDIA in the second half of 2025. NVIDIA's GPU products are currently based on 4 nm HBM chips. The HBM4 prototype chip launched in March by SK Hynix features vertical stacking on a 3 nm die., compared to a 5 nm base die, the new 3 nm-based HBM chip is expected to offer a 20-30% performance improvement. However, SK Hynix's general-purpose HBM4 and HBM4E chips will continue to use the 12 nm process in collaboration with TSMC.

While SK Hynix's fifth-generation HBM3E chips used its own base die technology, the company has chosen TSMC's 3 nm technology for HBM4. This decision is anticipated to significantly widen the performance gap with competitor Samsung Electronics, which plans to manufacture its HBM4 chips using the 4 nm process. SK hynix is currently leading the global HBM market with almost 50% of market share, most of its HBM products been delivered to NVIDIA.

Marvell Technology, Inc., a leader in data infrastructure semiconductor solutions, today introduced Marvell Ara, the industry's first 3 nm 1.6 Tbps PAM4 interconnects platform featuring 200 Gbps electrical and optical interfaces. Building on the success of the Nova 2 DSP, the industry's first 5 nm 1.6 Tbps PAM4 DSP with 200 Gbps electrical and optical interfaces, Ara leverages the comprehensive Marvell 3 nm platform with industry-leading 200 Gbps SerDes and integrated optical modulator drivers, to reduce 1.6 Tbps optical module power by over 20%. The energy efficiency improvement reduces operational costs and enables new AI server and networking architectures to address the need for higher bandwidth and performance for AI workloads, within the significant power constraints of the data center.

Ara, the industry's first 3 nm PAM4 optical DSP, builds on six generations of Marvell leadership in PAM4 optical DSP technology. It integrates eight 200 Gbps electrical lanes to the host and eight 200 Gbps optical lanes, enabling 1.6 Tbps in a compact, standardized module form factor. Leveraging 3 nm technology and laser driver integration, Ara reduces module design complexity, power consumption and cost, setting a new benchmark for next-generation AI and cloud infrastructure.

Being the leading-edge semiconductor manufacturing company, TSMC actively works on increasing the efficiency of its upcoming nodes, even when they are finalized and ready for high-volume manufacturing. According to a TSMC employee identified as Dr. Kim on X, recent test runs of the 2 nm N2 nodes show a 6% improvement in production yields compared to baseline expectations. This advancement could translate into substantial cost savings for the company's customers when mass production begins in late 2025. However, specific details about whether the gains were achieved in SRAM or logic test chips remain undisclosed. The timing is particularly noteworthy as TSMC prepares to launch its shuttle test wafer services for 2 nm technology in January. The N2 process represents a giant leap for TSMC, marking its first gate-all-around (GAA) nanosheet transistors implementation, the first step to derive from the classical FinFET design.

According to TSMC's projections, chips manufactured using the N2 process will consume 25-30% less power while maintaining the same transistor count and frequency as its N3E node. Additionally, the technology is expected to deliver 10-15% performance improvements and achieve a 15% increase in transistor density. A key innovation in the N2 process is the enhanced design of its GAA nanosheet transistors, which offers improved electrostatic control and reduced gate leakage compared to 3 nm FinFET transistors, given that the gate can be controlled from all sides. This advancement enables smaller high-density transistors to maintain reliable performance through better threshold voltage tuning capabilities. With approximately seven to eight months until full-scale volume production begins, the company has a substantial window to optimize the manufacturing process further and potentially achieve additional yield improvements, although that is less likely.

Taiwanese political officials have agreed to discuss transferring TSMC's advanced 2 nm chip technology to allied democratic nations, but only after establishing the main mass production launch in late 2025 in Taiwan. This new stance comes amid growing international pressure and recent comments from upcoming US president Donald Trump about semiconductor manufacturing. The announcement by National Science and Technology Council Minister Cheng-Wen Wu marks a notable departure from earlier statements by Economic Affairs Minister J.W. Kuo, who had previously emphasized legal restrictions on transferring leading-edge process technology overseas. Interestingly, these different positions aren't so different from one point: timeline of node deployments. As TSMC produces latest nodes in Taiwan, overseas production will lag by a generation or two.

TSMC plans to implement its 2 nm technology in US facilities by 2030. The company's Arizona facility, Fab 21, will begin with less advanced N4 and N5 processes in early 2025 and progress to 3 nm technology by 2028. However, this timeline could face pressure for acceleration, mainly if new trade policies are implemented. Industry analyst Dan Nystedt points out significant challenges in transferring advanced chip production. Integrating research and development with manufacturing processes in Taiwan provides crucial advantages for initial production ramps, making simultaneous mass production launches in multiple locations technically challenging. Simply put, there aren't enough capable engineers, scientists, and factory workers capable of doing what TSMC accomplishes in Taiwan.

According to Taiwanese media Commercial Times, Intel is significantly increasing its outsourcing of "Arrow Lake" CPU production to TSMC, a strategic move as it grapples with persistent issues in its own foundry division. This decision to outsource a substantial portion of Arrow Lake's production is a significant shift in Intel's strategy, showing the company's rising reliance on external partners to meet quality and performance demands. The Arrow Lake Core Ultra 200 series is Intel's first major outsourcing initiative, in which Intel gave its core IP to third-party foundries, more specifically for a 3 nm node at TSMC. However, it clearly indicates the performance gaps in Intel's own Intel Foundry and the high demand expectations for the new CPUs. Originally intended to use Intel 20A node, Intel shifted focus of 18A node for its products and upcoming foundry customers.

Intel's recent orders with TSMC extend to its upcoming Lunar Lake chips and next-generation Falcon Shores AI GPUs, both of which will use TSMC's 3 nm process. Although Intel's 18A node remains promising, the company relies on current products to sustain its revenue streams, making TSMC's support crucial in ensuring timely shipments. This increased outsourcing reflects Intel's need to maintain competitive performance in the short term. Once its Foundry division meets performance and capacity targets, Intel aims to bring more CPU manufacturing back in-house. However, if anything goes wrong, Intel could face challenges securing sufficient volume from TSMC, as the foundry has longstanding commitments with major clients like Apple, NVIDIA, Qualcomm, and AMD.

Samsung's latest semiconductor manufacturing technology is falling short of expectations, as the company struggles to achieve acceptable production rates for its cutting-edge 3 nm chips. The latest rumors indicate that both versions of Samsung's 3 nm Gate-All-Around (GAA) process produce fewer viable chips than anticipated. The initial targets set by the South Korean tech giant were aimed at a 70% yield rate in volume production. However, the first "SF3E-3GAE" iteration of the technology has only managed to achieve between 50-60% viable yield output. More troubling is the performance of the second-generation process, which is reportedly yielding only 20% of usable chips—a figure that falls dramatically short of production goals. The timing is particularly challenging for Samsung as major clients begin to reevaluate their manufacturing partnerships.

Qualcomm has opted to produce its latest Snapdragon 8 Elite processors exclusively through rival TSMC's 3 nm facilities. Even more telling is the exodus of South Korean companies, traditionally loyal to Samsung, who are now turning to TSMC's more reliable manufacturing processes. While Samsung can claim the achievement of bringing 3 nm GAA technology to market before TSMC's competing N3B process, this technical victory rings hollow without the ability to mass-produce chips efficiently. The gap between Samsung's aspirations and manufacturing reality continues to widen. However, Samsung is shifting its focus toward its next technological milestone. Development efforts are reportedly intensifying around a 2 nm manufacturing process, with plans to debut this technology in a new Exynos processor (codenamed 'Ulysses') for the 2027 Galaxy S27 smartphone series.

Our latest front-page poll sheds light on what people want from the next generation of gaming GPUs. We asked our readers what mattered most to them, with answers including raster performance, ray tracing performance, energy efficiency, upscaling or frame-gen technologies, the size of video memory, and lastly, pricing. Our poll ran from September 19, and gathered close to 24,000 votes as of this writing. Pricing remains the king of our polls, with the option gathering 36.1% of the vote, or 8,620 votes. Our readers expect pricing of next-generation GPUs to remain flat, variant-for-variant, and not continue on the absurdly upward trend it has had for the past few generations, with the high-end being pushed beyond the $1,000-mark, and $500 barely bringing in a 1440p-class GPU, while 4K-capable game consoles exist.

Both AMD and NVIDIA know that Moore's Law is cooked, and that generational leaps in performance and transistor counts are only possible with increase in pricing for the latest foundry nodes. AMD even tried experimenting with disaggregated (chiplet-based) GPUs with its latest RDNA 3 generation, before calling it quits on the enthusiast-segment, so it could focus on the sub-$1000 performance segment. The second most popular response was Raster 3D performance (classic 3D rendering performance), which scored 27% or 6,453 votes.

As Intel's Core Ultra "Arrow Lake-S" desktop processors near their launch, ASUS China put out a video presentation about its Z890 chipset motherboards ready for these processors, which included a technical run-down of Intel's first tile-based desktop processor, which included detailed die-shots of the various tiles. This is stuff that would require not just de-lidding the processor (removing the integrated heat-spreader), but also clearing up the top layers of the die to reveal the various components underneath.

The whole-chip die-shot gives us a bird's eye view of the four key logic tiles—Compute, Graphics, SoC, and I/O, sitting on top of the Foveros base tile. Our article from earlier this week goes into the die areas of the individual tiles, and the base tile. The Compute tile is built on the most advanced foundry node among the four tiles, the 3 nm TSMC N3B. Unlike the older generation "Raptor Lake-S" and "Alder Lake-S," the P-cores and E-core clusters aren't clumped into the two ends of the CPU complex. In "Arrow Lake-S," they follow a staggered layout, with a row of P-cores, followed by a row of E-core clusters, followed by two rows of P-cores, and then another row of E-core clusters, before the final row of P-cores, to achieve the total core-count of 8P+16E. This arrangement reduces concentration of heat when the P-cores are loaded (eg: when gaming), and ensures each E-core cluster is just one ringbus stop away from a P-core, which should improve thread-migration latencies. The central region of the tile has this ringbus, and 36 MB of L3 cache shared among the P-cores and E-core clusters.

As a quick follow-up to last week's "Arrow Lake-S" de-lidding by Madness727, we now have a line-up of a de-lidded Core Ultra 9 285K "Arrow Lake-S" processor placed next to a Core i9-14900K "Raptor Lake-S," and the Core i9-12900K "Alder Lake-S." The tile-based "Arrow Lake-S" is visibly larger than the two, despite being made on more advanced foundry nodes. Both the 8P+16E "Raptor Lake-S" and 8P+8E "Alder Lake-S" chips are built on the Intel 7 node (10 nm Enhanced SuperFin). The "Raptor Lake-S" monolithic chip comes with a die-area of 257 mm². The "Alder Lake-S" is physically smaller, at 215 mm². What sets the two apart isn't just the two additional E-core clusters on "Raptor Lake-S," but also larger caches—2 MB of L2 per P-core, increased form 1.25 MB/core, and 4 MB per E-core cluster, increased from 2 MB/cluster.

Thanks to high quality die-shots of the "Arrow Lake-S" by Madness727, we have our first die-area estimations by A Hollow Knight on Twitter. The LGA1851 fiberglass substrate has the same dimensions as the LGA1700 substrate. This is to ensure the socket retains cooler compatibility. Using geometrical measurements, the base tile of the "Arrow Lake-S" is estimated to be 300.9 mm² in area. The base-tile is a more suitable guideline for "die-area," since Intel uses filler tiles to ensure gaps in the arrangement of logic tiles are filled, and the chip aligns with the base-tile below. The base tile, built on an Intel 22 nm foundry node, serves like a silicon interposer, facilitating high-density microscopic wiring between the various logic tiles stacked on top, and an interface to the fiberglass substrate below.