TrendForce reports an interesting shift in the electronics landscape: dwindling inventories for TV components, along with a surging mobile repair market that's been driving TDDI demand, have sparked a smattering of urgent orders in the Q2 supply chain. These last-minute orders have served as pivotal lifelines, propping up Q2 capacity utilization and revenue for semiconductor foundries. However, the adrenaline rush from these stop-gap orders may be a short-lived phenomenon and is unlikely to be carried over into the third quarter.

On the other hand, demand for staple consumer products like smartphones, PCs, and notebooks remains sluggish, perpetuating a slump in the use of expensive, cutting-edge manufacturing processes. At the same time, traditionally stable sectors—automotive, industrial control, and servers—are undergoing inventory correction. The confluence of these trends has resulted in a sustained contraction for the world's top ten semiconductor foundries. Their global revenue declined by approximately 1.1% for the quarter, amounting to a staggering US$26.2 billion.

"Navi 4C" is a future high-end GPU from AMD that will likely not see the light of day, as the company is pivoting away from the high-end GPU segment with its next RDNA4 generation. For AMD to continue investing in the development of this GPU, the gaming graphics card segment should have posted better sales, especially in the high-end, which it didn't. Moore's Law is Dead scored details of what could have been a fascinating technological endeavor for AMD, in building a highly disaggregated GPU.

AMD's current "Navi 31" GPU sees a disaggregation of the main logic components of the GPU that benefit from the latest 5 nm foundry node to be located in a central Graphics Compute Die; surrounded by up to six little chiplets built on the older 6 nm foundry node, which contain segments of the GPU's Infinity Cache memory, and its memory interface—hence the name memory cache die. With "Navi 4C," AMD had intended to further disaggregate the GPU, identifying even more components on the GCD that can be spun out into chiplets; as well as breaking up the shader engines themselves into smaller self-contained chiplets (smaller dies == greater yields and lower foundry costs).

Samsung Electronics today reported financial results for the second quarter ended June 30, 2023. The Company posted KRW 60.01 trillion in consolidated revenue, a 6% decline from the previous quarter, mainly due to a decline in smartphone shipments despite a slight recovery in revenue of the DS (Device Solutions) Division. Operating profit rose sequentially to KRW 0.67 trillion as the DS Division posted a narrower loss, while Samsung Display Corporation (SDC) and the Digital Appliances Business saw improved profitability.

The Memory Business saw results improve from the previous quarter as its focus on High Bandwidth Memory (HBM) and DDR5 products in anticipation of robust demand for AI applications led to higher-than-guided DRAM shipments. System semiconductors posted a decline in profit due to lower utilization rates on weak demand from major applications.

Semiconductor industry research firm TechInsights said it has found that Samsung's 3 nm GAA (gate-all-around) process has been incorporated into the crypto miner ASIC (Whatsminer M56S++) from a Chinese manufacturer, MicroBT. In a Disruptive Technology Event Brief exclusively provided to DIGITIMES Asia, TechInsights points out that the significance of this development lies in the commercial utilization of GAA technology, which facilitates the scaling of transistors to 2 nm and beyond. "This development is crucial because it has the potential to enhance performance, improve energy efficiency, keep up with Moore's Law, and enable advanced applications," said TechInsights, identifying the MicroBT ASIC chip the first commercialized product using GAA technology in the industry.

But this would also reveal that Samsung is the foundry for MicroBT, using the 3 nm GAA process. DIGITIMES Research semiconductor analyst Eric Chen pointed out that Samsung indeed has started producing chips using the 3 nm GAA process, but the capacity is still small. "Getting revenues from shipment can be defined as 'commercialization', but ASIC is a relatively simple kind of chip to produce, in terms of architecture."

Competition between Samsung and TSMC in the 4 nm and 3 nm foundry process markets is about to heat up, with the Korean foundry claiming yields competitive to those of TSMC, according to a report in the Kukmin Ilbo, a Korean daily newspaper. 4 nm is the final silicon fabrication process to use the FinFET technology that powered nodes ranging between 16 nm to 4 nm. Samsung Foundry is claiming 4 nm wafer yields of 75%, against the 80% yields figure put out by TSMC. 4 nm powers several current-generation mobile SoCs, PC processors, and more importantly, the GPUs driving the AI gold-rush.

Things get very interesting with 3 nm, the node that debuts GAA-FET (gates all around FET) technology. Here, Samsung claims to offer higher yields than TSMC, with its 3 nm GAA node clocking 60% yields, against 55% put out by TSMC. Samsung was recently bitten by a scandal where its engineers allegedly falsified yields figures to customers to score orders, which had a cascading effect on the volumes and competitiveness of their customers. We're inclined to think that Samsung has taken lessons and is more careful with the yields figures being reported in the press. Meanwhile, Intel Foundry Services competes with the Intel 3 node, which is physically 7 nm FinFET, but with electrical characteristics comparable to those of 3 nm.

According to Taiwanese media, TSMC will start production of its first 1.4 nm fab in 2026, with chip production in the fab said to start sometime in 2027 or 2028. The new fab will be located in Longtan Science Park outside of Hsinchu in Taiwan, where many of TSMC's current fabs are located. TSMC is currently constructing a 2 nm and below node R&D facility at a nearby plot of land to where the new fab is expected to be built. This facility is expected to be finished in 2025 and TSMC has been allocated a total area of just over 158 hectares of land for future expansion in the area.

In related news, TSMC is expected to be charging US$25,000 per 2 nm GAA wafer, which is an increase of about a fifth compared to its 3 nm wafers which are going for around US$20,000. This is largely due to the nodes being fully booked and TSMC being able to charge a premium for its cutting edge nodes. TSMC is also expanding in CoWoS packaging facilities due to increased demand from both AMD and NVIDIA for AI related products. Currently TSMC is said to be able to output 12,000 CoWoS wafers per month and this is twice as much as last year, yet TSMC is unable to meet demand from its customers.

Samsung Electronics, a world leader in advanced semiconductor technology, today announced its latest foundry technology innovations and business strategy at the 7th annual Samsung Foundry Forum (SFF) 2023. Under the theme "Innovation Beyond Boundaries," this year's forum delved into Samsung Foundry's mission to address customer needs in the artificial intelligence (AI) era through advanced semiconductor technology.

Over 700 guests, from customers and partners of Samsung Foundry, attended this year's event, of which 38 companies hosted their own booths to share the latest technology trends in the foundry industry.

TrendForce reports that the global top 10 foundries witnessed a significant 18.6% QoQ decline in revenue during the first quarter of 2023. This decline—amounting to approximately US$27.3 billion—can be attributed to sustained weak end-market demand and the compounded effects of the off-peak season. The rankings also underwent notable changes, with GlobalFoundries surpassing UMC to secure the third position, and Tower Semiconductor surpassing PSMC and VIS to claim the seventh spot.

Declining capacity utilization rate and shipment volume contribute to widened revenue decline
The revenue decline in Q1 was primarily influenced by declining capacity utilization rates and shipment volume across the top 10 foundries. For instance, TSMC generated US$16.74 billion in revenue—marking a 16.2% QoQ drop in revenue. Weakened demand for mainstream applications such as laptops and smartphones led to a significant decline in the utilization rates and revenue of the 7/6 nm and 5/4 nm processes, falling over 20% and 17%, respectively. While the second quarter may see temporary relief coming from rush orders, the persistently low capacity utilization rate indicates that revenue is likely to continue declining, albeit at a slower pace compared to Q1.

When TSMC introduced its N3 lineup of nodes, the company only talked about the logic scaling of the two new semiconductor manufacturing steps. However, it turns out that there was a reason for it, as WikiChip confirms that the SRAM bit cells of N3 nodes are almost identical to the SRAM bit cells of N5 nodes. At TSMC 2023 Technology Symposium, TSMC presented additional details about its N3 node lineup, including logic and SRAM density. For starters, the N3 node is TSMC's "3 nm" node family that has two products: a Base N3 node (N3B) and an Enhanced N3 node (N3E). The base N3B uses a new (for TSMC) self-aligned contact (SAC) scheme that Intel introduced back in 2011 with a 22 nm node, which improves the node's yield.

Regardless of N3's logic density improvements compared to the "last-generation" N5, the SRAM density is almost identical. Initially, TSMC claimed N3B SRAM density was 1.2x over the N5 process. However, recent information shows that the actual SRAM density is merely a 5% difference. With SRAM taking a large portion of the transistor and area budget of a processor, N3B's soaring manufacturing costs are harder to justify when there is almost no area improvement. For some time, SRAM scaling wasn't following logic scaling; however, the two have now completely decoupled.

Thanks to the latest release of the Power On newsletter from Mark Gurman, we have additional information about Apple's upcoming M3 Pro chip. Currently in testing and reported on by an App Store developer, Apple is looking to upgrade the microarchitecture of the forthcoming chip and add additional cores to the system for more performance. As the report notes, the entry-level M3 Pro chip currently in testing will have 12 CPU cores, six for efficiency and six for performance tasks, with 18 graphics cores, all manufactured on TSMC's 3 nm node. The current baseline for M2 Pro is 10 CPU cores, where four are dedicated to efficiency, and six are dedicated to performance. The current generation entry-level M2 Pro also features a 16-core GPU, which is two cores fewer than the upcoming model.

Generally, the M3 Pro chip will boost integrated memory across the board, as the sample spotted in testing shows 36 GB of memory. The M2 Pro offered 32 GB in that memory tier, so a four GB increase is inbound there. Presumably, the 16 GB version (if it exists) and 64 GB version will also get memory bumps by going the M3 Pro route. Of course, we have to wait for more information as these chips become more widely available to developers.

AMD's next-generation Ryzen 8000 "Granite Ridge" desktop processor based on the "Zen 5" microarchitecture, will continue to top out at 16-core/32-thread as the maximum CPU core-count possible, says a report by PC Games Hardware. The processor will retain the chiplet design of the current Ryzen 7000 "Raphael" processor, with two 8-core "Zen 5" CCDs, and one I/O die. It's very likely that AMD will reuse the same 6 nm client I/O die (cIOD) as "Raphael," just the way it used the same 12 nm cIOD between Ryzen 3000 "Matisse" and Ryzen 5000 "Vermeer;" but with updates that could enable higher DDR5 memory speeds. Each of the up to two "Eldora" Zen 5 CCDs has 8 CPU cores, with 1 MB of dedicated L2 cache per core, and 32 MB of shared L3 cache. The CCDs are very likely to be built on the TSMC 3 nm EUV silicon fabrication process.

Perhaps the most interesting aspect of the PCGH leak would have to be the TDP numbers being mentioned, which continue to show higher-performance SKUs with 170 W TDP, and lower tiers with 65 W TDP. With its CPU core-counts not seeing increases, AMD would bank on not just the generational IPC increase of its "Zen 5" cores, but also max out performance within the power envelope of the new node, by dialing up clock speeds. AMD could ride out 2023 with its Ryzen 7000 "Zen 4" processors on the desktop platform, with "Granite Ridge" slated to enter production only by Q1-2024. The company could update its product stack in the meantime, perhaps even bring the 4 nm "Phoenix" monolithic APU silicon to the Socket AM5 desktop platform. Ryzen 8000 is expected to retain full compatibility with existing Socket AM5, and AMD 600-series chipset motherboards.

Barron's Magazine has been on a technology industry kick this week and published their interview with AMD CEO Dr. Lisa Su on May 3. The interviewer asks Su about her views on Moore's Law and it becomes apparent that she remains a believer of Gordon Moore's (more than half-century old) prediction - Moore, an Intel co-founder passed away in late March. Su explains that her company's engineers will need to innovate in order to carry on with that legacy: "I would certainly say I don't think Moore's Law is dead. I think Moore's Law has slowed down. We have to do different things to continue to get that performance and that energy efficiency. We've done chiplets - that's been one big step. We've now done 3-D packaging. We think there are a number of other innovations, as well." Expertise in other areas is also key in hitting technological goals: "Software and algorithms are also quite important. I think you need all of these pieces for us to continue this performance trajectory that we've all been on."

When asked about the challenges involved in advancing CPU designs within limitations, Su responds with: "Yes. The transistor costs and the amount of improvement you're getting from density and overall energy reduction is less from each generation. But we're still moving (forward) generation to generation. We're doing plenty of work in 3 nanometer today, and we're looking beyond that to 2 nm as well. But we'll continue to use chiplets and these type of constructions to try to get around some of the Moore's Law challenges." AMD and Intel continue to hold firm with Moore's Law, even though slightly younger upstarts disagree (see NVIDIA). Dr. Lisa Su's latest thoughts stay consistent with her colleague's past statements - AMD CTO Mark Papermaster reckoned that the theory is pertinent for another six to eight years, although it could be a costly endeavor for AMD - the company believes that it cannot double transistor density every 18 to 24 months without incurring extra expenses.

Intel Graphics employees inadvertently revealed that the company's Xe2 "Battlemage" graphics architecture is being designed for the 4 nm silicon fabrication node, which would give Intel's GPU designers a leap in transistor density and power headroom, given that TSMC 4 nm is an EUV node compared to the current 6 nm DUV node the company builds its Arc "Alchemist" GPUs on. The leak also seems to confirm that its succeeding "Celestial" graphics architecture is being designed for 3 nm. An enthusiast named gamma0burst sifted through public profiles of several Intel employees, and scored these details in their professional profile pages.

We are almost certain that Xe2 "Battlemage" is going to be built on the TSMC 4 nm node, and to a slightly lesser degree, about Xe3 "Celestial" being designed for TSMC's 3 nm N3X node. Intel roadmaps pin the debut of "Battlemage" to a 2023-2024 timeline, although this could also be a reference to the iGPU of the upcoming Core "Meteor Lake" processors that debut in the second half of 2023. Intel is highly likely to deliver "Meteor Lake" within its 2H-2023 timeline, which would mean that the mention of "2024" in the graphics technology roadmap could mean that discrete GPUs based on "Battlemage" only arrive next year.

It appears it's not only AMD that is eyeing a move to Samsung, when it comes to fabricating upcoming chips, as reports are now suggesting that Qualcomm is considering a second attempt at making flagship mobile SoCs at Samsung's foundry. However, in this case, we're talking 3 nm chips in the shape of the Snapdragon 8 Gen 4, which is expected to launch in devices sometime in 2024. This is said to be Qualcomm's first chip based on cores built by Nuvia, a company that Qualcomm acquired in 2021.

That said, Qualcomm will apparently not rely on Samsung alone, but will also be making the Snapdragon 8 Gen 4 at TSMC. This might be because of past experience with Samsung, but the report out of Taiwan, suggests that the chips made by Samsung's foundry business will be used in Samsung branded phones, whereas the TSMC made chips might end up in devices by Qualcomm's other customers. It could also be a bet for Qualcomm to try and get better pricing by both foundries or a means of hedging their bets, to see which foundry produces the better chips. Then there's the situation between the PRC and the ROC, which could potentially put Qualcomm in a situation where it has no chips, so going with Samsung could be a means of covering for all potential risk scenarios.

Samsung Electronics is engaged in stiff competition with TSMC for chip manufacturing orders for 3 nm, its first semiconductor foundry node to implement GAA-FET technology, after nearly a decade of FinFET-based nodes. SF3, a 3 nm GAA-FET node, enters mass-production later this year. Samsung is claiming wafer yields in the range of 60-70% in the development phases of the node. This number is crucial to attract customers as they base their wafer orders squarely on yields first, and cost-per-wafer next.

Samsung is trying to rebuild confidence among chip designers after the 2022 controversy over its engineering "fabricating" yield numbers to customers to win their business. Samsung also stated that with 2023-2024 being dominated by 3 nm-class nodes, namely SF3 (3GAP), and its refinement the SF3P (3GAP+), the company will begin introducing its 2 nm class nodes in 2025-2026. Samsung's current customers for its 3 nm node include unnamed HPC processor designer, and a mobile AP (application processor) designer.

Samsung Electronics today reported financial results for the first quarter ended March 31, 2023. The Company posted KRW 63.75 trillion in consolidated revenue, a 10% decline from the previous quarter, as overall consumer spending slowed amid the uncertain global macroeconomic environment. Operating profit was KRW 0.64 trillion as the DS (Device Solutions) Division faced decreased demand, while profit in the DX (Device eXperience) Division increased.

The DS Division's profit declined from the previous quarter due to weak demand in the Memory Business, a decline in utilization rates in the Foundry Business and continued weak demand and inventory adjustments from customers. Samsung Display Corporation (SDC) saw earnings in the mobile panel business decline quarter-on-quarter amid a market contraction, while the large panel business slightly narrowed its losses. The DX Division's results improved on the back of strong sales of the premium Galaxy S23 series as well as an enhanced sales mix focusing on premium TVs.

TSMC today showcased its latest technology developments at its 2023 North America Technology Symposium, including progress in 2 nm technology and new members of its industry-leading 3 nm technology family, offering a range of processes tuned to meet diverse customer demands. These include N3P, an enhanced 3 nm process for better power, performance and density, N3X, a process tailored for high performance computing (HPC) applications, and N3AE, enabling early start of automotive applications on the most advanced silicon technology.

With more than 1,600 customers and partners registered to attend, the North America Technology Symposium in Santa Clara, California is the first of the TSMC's Technology Symposiums around the world in the coming months. The North America symposium also features an Innovation Zone spotlighting the exciting technologies of 18 emerging start-up customers.

Accelerating the integration of heterogeneous dies to enable the next level of system scalability and functionality, Synopsys, Inc. (Nasdaq: SNPS) has strengthened its collaboration with TSMC and Ansys for multi-die system design and manufacturing. Synopsys provides the industry's most comprehensive EDA and IP solutions for multi-die systems on TSMC's advanced 7 nm, 5 nm and 3 nm process technologies with support for TSMC 3DFabric technologies and 3Dblox standard. The integration of Synopsys implementation and signoff solutions and Ansys multi-physics analysis technology on TSMC processes allows designers to tackle the biggest challenges of multi-die systems, from early exploration to architecture design with signoff power, signal and thermal integrity analysis.

"Multi-die systems provide a way forward to achieve reduced power and area and higher performance, opening the door to a new era of innovation at the system-level," said Dan Kochpatcharin, head of Design Infrastructure Management Division at TSMC. "Our long-standing collaboration with Open Innovation Platform (OIP) ecosystem partners like Synopsys and Ansys gives mutual customers a faster path to multi-die system success through a full spectrum of best-in-class EDA and IP solutions optimized for our most advanced technologies."

Conflicting reports are flying around about Apple's next generation MacBook Air lineup, mostly surrounding suggestions of a firm release date or debut reveal at WWDC 2023. 9to5Mac claims that its insider sources have pointed to a new range of M3 chipset powered MacBook Air extra thin laptops offered up in two different screen sizes: 13-inch and 15-inch. An insider claimed last month that Apple's upcoming laptop lineup was in an advanced stage of production, and was far along enough to warrant an "imminent" launch window. A Taiwanese publication has presented new evidence this week, and it posits that Apple could drop M3 chipset-based laptops from announcement presentations organized for this year's Worldwide Developers Conference, which is set to take place from June 5 to 9.

According to the financial section of Taiwan's UDN news site, Apple's key decision makers could be in favor of fielding laptops based on its current generation M2 SoC, instead of an entry-level M3-based range, due to delays and changes in priority for the N3B node at TSMC foundries. This is seen as an odd move given reports from earlier this month of Apple requesting a reduction in factory output for its M2 chips, following a slump in demand. Apple could be changing its strategy with regards to the alleged surplus of M2 silicon - the article theorizes that the company will spend more time fitting the older generation chipsets into a new range of laptops and desktop computers. An M3-based product line could be delayed into late 2023, and it is alleged that TSMC has been instructed to concentrate mostly on manufacturing Apple's Bionix A17 mobile chipset via the cutting edge 3 nm FinFet technology process (N3B) - earmarked to debut on the iPhone 15 Pro in autumn 2023.

A technology tipster has been dropping multiple tidbits this week about Qualcomm's upcoming Snapdragon 8 Gen 3 mobile chipset - this follows a leak (from a different source, going back to mid-April) about the next generation Adreno 750 GPU getting tuned up for a battle against Apple's Bionic A17 in terms of graphics benchmarks. The latest leak points to the GPU being clocked at 900 MHz, rather than the rumored higher figure of 1.0 GHz speed (garnered from tests at Qualcomm's labs). The focus has now turned to the next generation flagship Snapdragon's CPU aspect, with information emerging about core clock speeds and multiple cluster configurations.

Revegnus suggests that the Snapdragon 8 Gen 3 (SD8G3) chipset will be packing a large primary core in the shape of Arm's Cortex-X4 CPU with a reported maximum clock speed of 3.40 GHz. Leaks from the past have posited that the SD8G3 would feature a fairly standard 1x Large + 5x Big + 2x Small CPU core layout (with clocks predicted to be: large Cortex X4 at 3.2 GHz, big Cortex-A720 at 3.0 GHz, and small Cortex-A520 at 2.0 GHz). An insider source has provided Revegnus with additional information about two different CPU core configurations - 1+5+2 and 2+4+2 - it is theorized that smartphone manufacturers will be offered the latter layout as an exclusive option for special edition flagship phones. The more powerful 2+4+2 variant is said to sacrifice a big core (A720) in favor of a dual Cortex X4 headliner, although the resultant thermal output of twin large cores could prove to be problematic.

An online tipster, posting on the Chinese blog site Weibo, has let slip that Qualcomm's upcoming Snapdragon 8 Gen 3 mobile chipset is touted to pack some hefty graphical capabilities. The suggested Adreno "750" smartphone and tablet GPU is touted to offer a 50% increase over the present generation Adreno 740 - as featured on the recently released and cutting-edge Snapdragon 8 Gen 2 chipset. The current generation top-of-the-range Snapdragon is no slouch when it comes to graphics benchmarks, where it outperforms Apple's prime contender - the Bionic A16 SoC.

The Snapdragon 8 Gen 3 SoC is expected to launch in the last quarter of 2023, but details of the flagship devices that it will power are non-existent at the time of writing. The tipster suggests that Qualcomm has decided to remain on TSMC's 4 nm process for its next generation mobile chipset - perhaps an all too safe decision when you consider that Apple has upped the stakes with the approach of its Bionic A17 SoC. It has been reported that the Cupertino, California-based company has chosen to fabricate via TSMC's 3 nm process, although the Taiwanese foundry is said to be struggling with its N3 production line. The engineers at Qualcomm's San Diego headquarters are alleged to be experimenting with increased clock speeds running on the next gen Adreno GPU - as high as 1.0 GHz - in order to eke out as much performance as possible, in anticipation of besting the Bionic A17 in graphics benchmarks. The tipster theorizes that Qualcomm will still have a hard time matching Apple in terms of pure CPU throughput, so the consolation prize will lie with a superior GPU getting rigged onto the Snapdragon 8 Gen 3.

An AMD engineer inadvertently leaked the core codenames of the company's upcoming "Zen 5" and "Zen 6" microarchitectures. It's important to understand here what has been leaked. "Zen 5" and "Zen 6" are microarchitecture names, just like the current "Zen 4" and past "Zen 3" or older. AMD uses codenames for the CCD (CPU complex dies) based on these microarchitectures, which it shares between Ryzen client and EPYC enterprise processors. For example, the CCD codename for "Zen 3" is "Brekenridge," and for "Zen 4" it is "Durango." AMD also uses codenames for the CPU cores themselves. "Zen 3" CPU cores are codenamed "Cerebrus," and "Zen 4" CPU cores "Persphone." And now, the leak:

The CCD based on the upcoming "Zen 5" microarchitecture is codenamed "Eldora," and the "Zen 5" CPU core itself is codenamed "Nirvana." There's no codename for the CCD based on "Zen 6," but its CPU cores are codenamed "Morpheus." The "Zen 5" microarchitecture will be based on the 3 nm EUV foundry node; while "Zen 6" will be 2 nm EUV. The engineer in the screenshot is contributing to the power-management technology behind "Zen 5" and "Zen 6," and states that their work on "Zen 5" spanned January-December of 2022, which means the development phase of the next "Zen" architecture is probably complete, and the architecture is undergoing testing and refinement. It's also claimed that work on at least the power-management aspect of "Zen 6" has started from January 2023.

Intel has awarded TSMC with some big contracts for future manufacturing of next generation GPUs, according to Taiwan's Commercial Times. As previously covered on TPU, the second generation Battlemage graphics processing units will get fabricated via a 4 nm process. According to insider sources at both partnering companies, Intel is eyeing a release date in the second half of 2024 for this Xe2-based architecture. The same sources pointed to the third generation Celestial graphics processing units being ready in time for a second half of 2026 launch window. Arc Celestial, which is based on the Xe3 architecture, is set for manufacture in the coming years courtesy of TSMC's N3X (3 nm) process node.

One of the sources claim that Intel is quietly confident about its future prospects in the GPU sector, despite mixed critical and commercial reactions to the first generation line-up of Arc Alchemist discrete graphics cards. The company is said to be anticipating great demand for more potent versions of its graphics products in the future, and internal restructuring efforts have not dulled the will of a core team of engineers. The restructuring process resulted in the original AXG graphics division being divided into two sub-groups - CCG and DCAI. The pioneer of the entire endeavor, Raja Koduri, departed Intel midway through last month, to pursue new opportunities with an AI-focused startup.

In no mood to cede its market-share growth to Intel, AMD has reportedly decided to accelerate the development of its next-generation "Zen 5" microarchitecture for debut within 2023. In its mid-2022 presentations, AMD had publicly given "Zen 5" a 2024 release date. This is part of a reading-in-between the lines for a recent GIGABYTE press release announcing server platforms powered by relatively low-cost Ryzen desktop processors. The specific sentence from that release reads "The next generation of AMD Ryzen desktop processors that will come out later this year will also be supported on this AM5 platform, so customers who purchase these servers today have the opportunity to upgrade to the Ryzen 7000 series successor."

While the GIGABYTE press release speaks of a next-generation Ryzen desktop processor, it stands to reason that it is referencing an early release of "Zen 5," and since AMD shares the CPU complex dies (CCDs) between its Ryzen client and EPYC server processors, the company is looking at a two-pronged upgrade to its processor lineup, with its next-generation EPYC "Turin" processor competing with Xeon Scalable "Emerald Rapids," and Ryzen "Granite Ridge" desktop processors taking on Intel's Core "Raptor Lake Refresh" and "Meteor Lake-S" desktop processors. It is rumored that "Zen 5" is being designed for the TSMC 3 nm node, and could see an increase in CPU core count per CCD, up from the present 8. TSMC 3 nm node goes into commercial mass-production in the first half of 2023 as the TSMC N3 node, with a refined N3E node slated for the second half of the year.

Apple's engineering team is rumored to be adjusting performance targets set for its next generation mobile SoC - the A17 Bionic - due to issues at the TSMC foundry. The cutting edge 3 nm process is proving difficult to handle, according to industry tipsters on Twitter. The leaks point to the A17 Bionic's overall performance goals being lowered by 20%, mainly due to the TSMC N3B node not meeting production targets. The factory is apparently lowering its yield and execution targets due to ongoing problems with FinFET limitations.

The leakers have recently revealed more up-to-date A17 Bionic's Geekbench 6 scores, with single thread performance at 3019, and multi-thread at 7860. Various publications have been hyping the mobile SoC's single thread performance as matching that of desktop CPUs from Intel and AMD, more specifically 13th-gen Core i7 and 'high-end' Ryzen models. Naturally the A17 Bionic cannot compete with these CPUs in terms of multi-thread performance.