Imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, presents patterned structures obtained after exposure with the 0.55NA EUV scanner in the joint ASML-imec High NA EUV Lithography Lab in Veldhoven, the Netherlands. Random logic structures down to 9,5 nm (19 nm pitch), random vias with 30 nm center-to-center distance, 2D features at 22 nm pitch, and a DRAM specific lay out at P32nm were printed after single exposure, using materials and baseline processes that were optimized for High NA EUV by imec and its partners in the framework of imec's Advanced Patterning Program. With these results, imec confirms the readiness of the ecosystem to enable single exposure high-resolution High NA EUV Lithography.

Following the recent opening of the joint ASML-imec High NA EUV Lithography Lab in Veldhoven, the Netherlands, customers now have access to the (TWINSCAN EXE:5000) High NA EUV scanner to develop private High NA EUV use cases leveraging the customer's own design rules and lay outs.

Japanese professor Tsumoru Shintake of the Okinawa Institute of Science and Technology (OIST) has unveiled a revolutionary extreme ultraviolet (EUV) lithography technology that promises to significantly push down semiconductor manufacturing costs. The new technology tackles two previously insurmountable issues in EUV lithography. First, it introduces a streamlined optical projection system using only two mirrors, a dramatic simplification from the conventional six or more. Second, it employs a novel "dual line field" method to efficiently direct EUV light onto the photomask without obstructing the optical path. Prof. Shintake's design offers substantial advantages over current EUV lithography machines. It can operate with smaller EUV light sources, consuming less than one-tenth of the power required by conventional systems. This reduction in energy consumption also reduces operating expenses (OpEx), which are usually high in semiconductor manufacturing facilities.

The simplified two-mirror design also promises improved stability and maintainability. While traditional EUV systems often require over 1 megawatt of power, the OIST model can achieve comparable results with just 100 kilowatts. Despite its simplicity, the system maintains high contrast and reduces mask 3D effects, which is crucial for attaining nanometer-scale precision in semiconductor production. OIST has filed a patent application for this technology, with plans for practical implementation through demonstration experiments. The global EUV lithography market is projected to grow from $8.9 billion in 2024 to $17.4 billion by 2030, when most nodes are expected to use EUV scanners. In contrast, ASML's single EUV scanner can cost up to $380 million without OpEx, which is very high thanks to the power consumption of high-energy light UV light emitters. Regular EUV scanners also lose 40% of the UV light going to the next mirror, with only 1% of the starting light source reaching the silicon wafer. And that is while consuming over one megawatt of power. However, with the proposed low-cost EUV system, more than 10% of the energy makes it to the wafer, and the new system is expected to use less than 100 kilowatts of power while carrying a cost of less than 100 million, a third from ASML's flagship.

Today, ASML Holding NV (ASML) has published its 2024 second-quarter results.

• Q2 total net sales of €6.2 billion, gross margin of 51.5%, net income of €1.6 billion
• Quarterly net bookings in Q2 of €5.6 billion of which €2.5 billion is EUV
• ASML expects Q3 2024 total net sales between €6.7 billion and €7.3 billion and a gross margin between 50% and 51%

CEO statement and outlook
"Our second-quarter total net sales came in at €6.2 billion, at the high-end of our guidance, with a gross margin of 51.5% which is above guidance, both primarily driven by more immersion systems sales. In line with previous quarters, overall semiconductor inventory levels continue to improve, and we also see further improvement in litho tool utilization levels at both Logic and Memory customers. While there are still uncertainties in the market, primarily driven by the macro environment, we expect industry recovery to continue in the second half of the year. We expect third-quarter total net sales between €6.7 billion and €7.3 billion with a gross margin between 50% and 51%. ASML expects R&D costs of around €1,100 million and SG&A costs of around €295 million. Our outlook for the full year 2024 remains unchanged. We see 2024 as a transition year with continued investments in both capacity ramp and technology. We currently see strong developments in AI, driving most of the industry recovery and growth, ahead of other market segments," said ASML President and Chief Executive Officer Christophe Fouquet.

Intel has reportedly chosen the TSMC 4 nm EUV foundry node for its next generation Arc Xe2 discrete GPUs based on the "Battlemage" graphics architecture. This would mark a generational upgrade from the Arc "Alchemist" family, which Intel built on the TSMC 6 nm DUV process. The TSMC N4 node offers significant increases in transistor densities, performance, and power efficiency over the N6, which is allowing Intel to nearly double the Xe cores on its largest "Battlemage" variant in numerical terms. This, coupled with increased IPC, clock speeds, and other features, should make the "Battlemage" contemporary against today's AMD RDNA 3 and NVIDIA Ada gaming GPUs. Interestingly, TSMC N4 isn't the most advanced foundry node that the Xe2 "Battlemage" is being built on. The iGPU powering Intel's Core Ultra 200V "Lunar Lake" processor is part of its Compute tile, which Intel is building on the more advanced TSMC N3 (3 nm) node.

TSMC has commenced mass-production of chips for Intel on its 3 nm EUV FinFET foundry node, according to a report by Taiwan industry observer DigiTimes. Intel is using the TSMC 3 nm node for the compute tile of its upcoming Core Ultra 300 "Lunar Lake" processor. The company went into depth about "Lunar Lake" in its Computex 2024 presentation. While a disaggregated chiplet-based processor like "Meteor Lake," the new "Lunar Lake" chip sees the CPU cores, iGPU, NPU, and memory controllers sit on a single chiplet called the compute tile, built on the 3 nm node; while the SoC and I/O components are disaggregated the chip's only other chiplet, the SoC tile, which is built on the TSMC 6 nm node.

Intel hasn't gone into the nuts and bolts of "Arrow Lake," besides mentioning that the processor will feature the same "Lion Cove" P-cores and "Skymont" E-cores as "Lunar Lake," albeit arranged in a more familiar ringbus configuration, where the E-core clusters share L3 cache with the P-cores (something that doesn't happen on "Lunar Lake"). "Arrow Lake" also features a iGPU based on the same Xe2 graphics architecture as "Lunar Lake," and will feature an NPU that meets Microsoft Copilot+ AI PC requirements. What remains a mystery about "Arrow Lake" is the way Intel will go about organizing the various chiplets or tiles. Reports from February 2024 mentioned Intel tapping into TSMC 3 nm for just the disaggregated graphics tile of "Arrow Lake," but we now know from "Lunar Lake" that Intel doesn't shy away from letting TSMC fabricate its CPU cores. The first notebooks powered by "Lunar Lake" are expected to hit shelves within Q3-2024, with "Arrow Lake" following on in Q4.

ASML, the world's sole provider of extreme ultraviolet (EUV) lithography systems essential for manufacturing the most advanced chips, has revealed its roadmap for pushing semiconductor scaling even further. In a recent presentation, former ASML president Martin van den Brink announced the company's plans for a new "Hyper-NA" EUV technology that would succeed the High-NA EUV systems, which are just beginning to deploy. The Hyper-NA tools, still in early research stages, would increase the numerical aperture to 0.75 from High-NA's 0.55, enabling chips with transistor densities beyond the projected limits of High-NA in the early 2030s. This higher numerical aperture should reduce reliance on multi-patterning techniques that add complexity and cost.

Hyper-NA is bringing challenges of its own to commercialization. Key obstacles include light polarization effects that degrade imaging contrast, requiring polarization filters that reduce light throughput. Resist materials may also need to become thinner to maintain resolution. While leading EUV chipmakers like TSMC can likely extend scaling for several more nodes using multi-patterning with existing 0.33 NA EUV tools, Intel has adopted 0.55 High-NA to avoid these complexities. But Hyper-NA will likely become essential across the industry later this decade as High-NA's physical limits are reached. Beyond Hyper-NA, few alternative patterning solutions exist besides expensive multi-beam electron lithography, which lacks the throughput of EUV photolithography. To continue classical scaling, the industry may need to eventually transition to new channel materials with superior electron mobility properties compared to silicon, requiring novel deposition and etch capabilities.

Intel Corporation (Nasdaq: INTC) and Apollo (NYSE: APO) today announced a definitive agreement under which Apollo-managed funds and affiliates will lead an investment of $11 billion to acquire from Intel a 49% equity interest in a joint venture entity related to Intel's Fab 34. The transaction represents Intel's second Semiconductor Co-Investment Program (SCIP) arrangement. SCIP is an element of Intel's Smart Capital strategy, a funding approach designed to create financial flexibility to accelerate the company's strategy, including investing in its global manufacturing operations, while maintaining a strong balance sheet.

Located in Leixlip, Ireland, Fab 34 is Intel's leading-edge high-volume manufacturing (HVM) facility designed for wafers using the Intel 4 and Intel 3 process technologies. To date, Intel has invested $18.4 billion in Fab 34. This transaction allows Intel to unlock and redeploy to other parts of its business a portion of this investment while continuing the build-out of Fab 34. As part of its transformation strategy, Intel has committed billions of dollars of investments to regaining process leadership and building out leading-edge wafer fabrication and advanced packaging capacity globally.

Last year, Micron unveiled plans to construct a cutting-edge DRAM factory in Hiroshima, Japan. However, the project has faced a significant two-year delay, pushing back the initial timeline for mass production of the company's most advanced memory products. Originally slated to begin mass production by the end of 2025, Micron now aims to have the new facility operational by 2027. The complexity of integrating extreme ultraviolet lithography (EUV) equipment, which enables the production of highly advanced chips, has contributed to the delay. The Hiroshima plant will produce next-generation 1-gamma DRAM and high-bandwidth memory (HBM) designed for generative AI applications. Micron expects the HBM market, currently dominated by rivals SK Hynix and Samsung, to experience rapid growth, with the company targeting a 25% market share by 2025.

The project is expected to cost between 600 and 800 billion Japanese yen ($3.8 to $5.1 billion), with Japan's government covering one-third of the cost. Micron has received a subsidy of up to 192 billion yen ($1.2 billion) for construction and equipment, as well as a subsidy to cover half of the necessary funding to produce HBM at the plant, amounting to 25 billion yen ($159 million). Despite the delay, the increased investment in the factory reflects Micron's commitment to advancing its memory technology and capitalizing on the growing demand for HBM. An indication of that is the fact that customers have pre-ordered 100% of the HBM capacity for 2024, not leaving a single HBM die unused.

AMD's future RDNA 5 graphics architecture will bear a "clean sheet" design, and may probably not even have the RDNA branding, says WJM47196, a source of AMD leaks on ChipHell. Two generations ahead of the current RDNA 3 architecture powering the Radeon RX 7000 series discrete GPUs, RDNA 5 could see AMD reimagine the GPU and its key components, much in the same way RDNA did over the former "Vega" architecture, bringing in a significant performance/watt jump, which AMD could build upon with its successful RDNA 2 powered Radeon RX 6000 series.

Performance per Watt is the biggest metric on which a generation of GPUs can be assessed, and analysts believe that RDNA 3 missed the mark with generational gains in performance/watt despite the switch to the advanced 5 nm EUV process from the 7 nm DUV. AMD's decision to disaggregate the GPU, with some of its components being built on the older 6 nm node may have also impacted the performance/watt curve. The leaker also makes a sensational claim that "Navi 31" was originally supposed to feature 192 MB of Infinity Cache, which would have meant 32 MB segments of it per memory cache die (MCD). The company instead went with 16 MB per MCD, or just 96 MB per GPU, which only get reduced as AMD segmented the RX 7900 XT and RX 7900 GRE by disabling one or two MCDs.

Today, ASML Holding NV (ASML) has published its 2024 first-quarter results.

• Q1 total net sales of €5.3 billion, gross margin of 51.0%, net income of €1.2 billion
• Quarterly net bookings in Q1 of €3.6 billion of which €656 million is EUV
• ASML expects Q2 2024 total net sales between €5.7 billion and €6.2 billion, and a gross margin between 50% and 51%
• ASML expects 2024 total net sales to be similar to 2023

CEO statement and outlook
"Our first-quarter total net sales came in at €5.3 billion, at the midpoint of our guidance, with a gross margin of 51.0% which is above guidance, primarily driven by product mix and one-offs. We expect second-quarter total net sales between €5.7 billion and €6.2 billion with a gross margin between 50% and 51%. ASML expects R&D costs of around €1,070 million and SG&A costs of around €295 million. Our outlook for the full year 2024 is unchanged, with the second half of the year expected to be stronger than the first half, in line with the industry's continued recovery from the downturn. We see 2024 as a transition year with continued investments in both capacity ramp and technology, to be ready for the turn in the cycle," said ASML President and Chief Executive Officer Peter Wennink.

Intel Core Ultra "Lunar Lake-MX" will be the company's bulwark against Apple's M-series Pro and Max chips, designed to power the next crop of performance ultraportables. The MX codename extension denotes MoP (memory-on-package), which sees stacked LPDDR5X memory chips share the package's fiberglass substrate with the chip, to conserve PCB footprint, and give Intel greater control over the right kind of memory speed, timings, and power-management features suited to its microarchitecture. This is essentially what Apple does with its M-series SoCs powering its MacBooks and iPad Pros. Igor's Lab scored the motherlode on the way Intel has restructured the various components across its chiplets, and the various I/O wired to the package.

When compared to "Meteor Lake," the "Lunar Lake" microarchitecture sees a small amount of "re-aggregation" of the various logic-heavy components of the processor. On "Meteor Lake," the CPU cores and the iGPU sat on separate tiles—Compute tile and Graphics tile, respectively, with a large SoC tile sitting between them, and a smaller I/O tile that serves as an extension of the SoC tile. All four tiles sat on top of a Foveros base tile, which is essentially an interposer—a silicon die that facilitates high-density microscopic wiring between the various tiles that are placed on top of it. With "Lunar Lake," there are only two tiles—the Compute tile, and the SoC tile.

The 3 nm EUV node, which will be TSMC's final semiconductor fabrication node to implement FinFET transistors, will make for a staggering 20% of TSMC's revenues in 2024, a report by ICSmart says. 20% is big for a new foundry node, considering that TSMC is simultaneously running 4 nm and 5 nm EUV nodes; 6 nm and 7 nm DUV nodes; and several older mature nodes. Apple is expected to be the foundry's biggest customer for 3 nm, as it could power the company's current A17 and M3, and upcoming A18 and M4 line of chips for its next-generation iPhone and MacBooks; followed by NVIDIA, AMD, and possibly even Intel. AMD is expected to build some versions of its upcoming "Zen 5" processors on 3 nm; while Intel is expected to use 3 nm for some of the tiles of its upcoming "Lunar Lake" processor. The same report goes to suggest that 3 nm will make up 30% of TSMC's revenues in 2025.

According to Bloomberg's latest investigation, Huawei and Semiconductor Manufacturing International Corporation (SMIC) have submitted patents on the self-aligned quadruple patterning (SAQP) pattern etching technique to enable SMIC to achieve 5 nm semiconductor production. The two Chinese giants have been working with the Deep Ultra Violet (DUV) machinery to develop a pattern etching technique allowing SMIC to produce a node compliant with the US exporting rules while maintaining the density improvements from the previously announced 7 nm node. In the 7 nm process, SMIC most likely used self-aligned dual patterning (SADP) with DUV tools, but for the increased density of the 5 nm node, a doubling to SAQP is required. In semiconductor manufacturing, lithography tools take multiple turns to etch the design of the silicon wafer.

Especially with smaller nodes getting ever-increasing density requirements, it is becoming challenging to etch sub-10 nm designs using DUV tools. That is where Extreme Ultra Violet (EUV) tools from ASML come into play. With EUV, the wavelengths of the lithography printers are 14 times smaller than DUV, at only 13.5 nm, compared to 193 nm of ArF immersion DUV systems. This means that without EUV, SMIC has to look into alternatives like SAQP to increase the density of its nodes and, as a result, include more complications and possibly lower yields. As an example, Intel tried to use SAQP in its first 10 nm nodes to reduce reliance on EUV, which resulted in a series of delays and complications, eventually pushing Intel into EUV. While Huawei and SMIC may develop a more efficient solution for SAQP, the use of EUV is imminent as the regular DUV can not keep up with the increasing density of semiconductor nodes. Given that ASML can't ship its EUV machinery to China, Huawei is supposedly developing its own EUV machines, but will likely take a few more years to show.

ASML celebrated an important milestone last week—the company's social media account shared news about their third generation extreme ultraviolet (EUV) lithography tool reaching an unnamed customer: "chipmakers have a need for speed! The first Twinscan NXE:3800E is now being installed in a chip fab. 🔧 With its new wafer stages, the system will deliver leading edge productivity for printing advanced chips. We're pushing lithography to new limits." The post included a couple of snaps—ASML workers were gathered in front of a pair of climatized containers, and Peter Wennink (President and CEO) and Christophe Fouquet (EVP and CBO) thanked staff at company HQ.

The Twinscan NXE:3800E is ASML's latest platform from a series of 0.33 numerical aperture (Low-NA) lithography scanners. Information is scarce—the company has not yet published a 3800E product page. The preceding model—Twinscan NXE:3600D—supports EUV volume production at 3 and 5 nm. ASML roadmaps imply that the Twinscan NXE:3800E has been designed to produce chips on 2 and 3 nm-class technologies. The company's cutting-edge High-NA extreme ultraviolet (EUV) chipmaking tools (High-NA Twinscan EXE) are expected to cost around $380 million—reports from last month point to a possible $183 million price point for "existing Low-NA EUV lithography systems." Another Low-NA EUV machine is reported to be lined up for a possible 2026 release window—ASML's next-gen Twinscan NXE:4000F model will co-exist alongside emerging (pricier) High-NA solutions.

Silicon Motion Technology Corporation ("Silicon Motion"), a global leader in designing and marketing NAND flash controllers for solid state storage devices, today introduced its UFS (Universal Flash Storage) 4.0 controller, the SM2756, as the flagship of the industry's broadest merchant portfolio of UFS controller solutions for the growing requirements of AI-powered smartphones as well as other high-performance applications including automotive and edge computing. The company also added a new, second generation SM2753 UFS 3.1 controller to broaden its portfolio of controllers now supporting UFS 4.0 to UFS 2.2 standards. Silicon Motion's UFS portfolio delivers high-performance and low power embedded storage for flagship to mainstream and value mobile and computing devices, supporting the broadest range of NAND flash, including next-generation high speed 3D TLC and QLC NAND.

The new SM2756 UFS 4.0 controller solution is the world's most advanced controller, built on leading 6 nm EUV technology and using MIPI M-PHY low-power architecture, providing the right balance of high performance and power efficiency to enable the all day computing needs of today's premium and AI mobile devices. The SM2756 achieves sequential read performance exceeding 4,300 MB/s and sequential write speeds of over 4,000 MB/s and supports the broadest range of 3D TLC and QLC NAND flash with densities of up to 2 TB.

Intel is revamping its foundry play, and the company is set on its goals of becoming a strong contender to rivals such as TSMC and Samsung. Under Pat Gelsinger's lead, Intel recently split (virtually, under the same company) its units into Intel Product and Intel Foundry. During the SPIE 2024 conference for optics and photonics, Anne Kelleher, Intel's senior vice president, revealed that the 14A (1.4 nm) process offers a 15% performance-per-watt improvement over the company's 18A (1.8 nanometers) process. Additionally, the enhanced 14A-E process boasts a further 5% performance boost from the regular A14 node, being a small refresh. Intel's 14A process is set to be the first to utilize High-NA extreme ultraviolet (EUV) equipment, delivering a 20% increase in transistor logic density compared to the 18A node.

The company's aggressive pursuit of next-generation processes poses a significant threat to Samsung Electronics, which currently holds the second position in the foundry market. As part of its IDM 2.0 strategy, Intel hopes to reclaim its position as a leading foundry player and surpass Samsung by 2030. The company's collaboration with American companies, such as Microsoft, further solidifies its ambitions. Intel has already secured a $15 billion chip production contract with Microsoft for its 1.8 nm 18A process. The semiconductor industry is closely monitoring Intel's progress, as the company's advancements in process technology could potentially reshape the competitive landscape. With Samsung planning to mass-produce 2 nm process products next year, the race for dominance in the foundry market is heating up.

SMIC, China's largest semiconductor manufacturer, is reportedly assembling a dedicated team to develop 3 nm semiconductor node technology, following reports of the company setting up 5 nm chip production for Huawei later this year. This move is part of SMIC's efforts to achieve independence from foreign companies and reduce its reliance on US technology. According to a report from Joongang, SMIC's initial goal is to commence operations of its 5 nm production line, which will mass-produce Huawei chipsets for various products, including AI silicon. However, SMIC is already looking beyond the 5 nm node. The company has assembled an internal research and development team to begin work on the next-generation 3 nm node.

The Chinese manufacturer is expected to accomplish this using existing DUV machinery, as ASML, the sole supplier of advanced EUV technology, is prohibited from providing equipment to Chinese companies due to US restrictions. It is reported that one of the biggest challenges facing SMIC is the potential for low yields and high production costs. The company is seeking substantial subsidies from the Chinese government to overcome these obstacles. Receiving government subsidies will be crucial for SMIC, especially considering that its 5 nm chips are expected to be up to 50 percent more expensive than TSMC's due to the use of older DUV equipment. The first 3 nm wafers from SMIC are not expected to roll out for several years, as the company will prioritize the commercialization of Huawei's 5 nm chips. This ambitious undertaking by SMIC represents a significant challenge for the company as it strives to reduce its dependence on foreign semiconductor technology and establish itself as an essential player in the global manufacturing industry.

Chipmaking manufacturing equipment giant ASML has expressed concerns about staying in the Netherlands and considering expansion into other countries due to its home country's capped possibilities. On Wednesday, ASML executives met with Netherlands Prime Minister Mark Rutte to discuss the company's growth plans. The meeting, however, failed to fully resolve ASML's concerns surrounding the country's stance on skilled foreign labor, leaving uncertainty over the tech giant's expansion in its home market. Being one of the world's largest suppliers to chipmakers, ASML has said it needs to double its operations in the following decade to meet soaring demand. However, the company is hitting roadblocks in the Netherlands, including difficulty obtaining building permits, constraints on the electrical grid, transportation bottlenecks, and a need for supporting infrastructure like hospitals, schools, and housing. A key issue is the Netherlands' ability to attract scarce foreign engineering talent, with over 40% of ASML's Dutch workforce being non-Dutch. Recent parliamentary motions to cap international students and scrap a tax break for skilled migrants have met with criticism from ASML and other tech employers.

In an effort dubbed "Operation Beethoven," the Dutch government is scrambling to address ASML's concerns and prevent the company from expanding abroad, having already seen multinationals like Shell and Unilever leave their home country in recent years. However, ASML CEO Peter Wennink said that while the company prefers to grow in the Netherlands, it can do so elsewhere if needed. The situation comes amid pressure from the US for allies like the Netherlands to tighten restrictions on China's further access to semiconductor technology. As the sole producer of extreme ultraviolet (EUV) lithography machines crucial for advanced chipmaking, like High-NA and Low-NA, ASML holds strategic importance beyond just economics. With a new right-wing Dutch government being formed, whether a compromise can be reached to ensure ASML's continued growth in the Netherlands remains to be seen. The tech giant's decision could significantly affect the Dutch economy and its position in the global chip industry.

Samsung Electronics foundry has reportedly bagged a mass production order for its cutting edge 2 nm EUV foundry node from Japanese AI chip startup PFN (Preferred Networks). This is reportedly the first major third party order for the 2 nm node. Founded in 2014, PFN specializes in AI and IoT chips, and spun off from Preferred Infrastructure. Samsung's 2 nm node, called the SF2, is on track for delivery of mass produced chips in 2025, which means much of 2024 will be spent on testing, validation, and risk production, with the node expected to go live toward the end of the year. Samsung SF2 is being designed to offer 25% higher power efficiency (at iso-clocks), and 12% increase in performance, over SF3 (3 nm EUV FinFET). In the semiconductor fabrication market, Samsung SF2 competes against TSMC N2 and Intel 20A.

According to a Bloomberg report, Intel is seeking to raise at least $2 billion in equity funding from investors for expanding its fabrication facility in Leixlip, Ireland, known as Fab 34. The chipmaker has hired an advisor to find potential investors interested in providing capital for the project. Fab 34 is currently Intel's only chip plant in Europe that uses cutting-edge extreme ultraviolet (EUV) lithography. It produces processors on the Intel 4 process node, including compute tiles for Meteor Lake client CPUs and expected future Xeon data center chips. While $2 billion alone cannot finance the construction of an entirely new fab today, it can support meaningful expansion or upgrades of existing capacity. Intel likely aims to grow Fab 34's output and/or transition it to more advanced 3 nm-class technologies like Intel 3, Intel 20A, or Intel 18A.

Expanding production aligns with Intel's needs for its own products and its Intel Foundry Services business, providing contract manufacturing. Intel previously secured a $15 billion investment from Brookfield Infrastructure for its Arizona fabs in exchange for a 49% stake, demonstrating the company's willingness to partner to raise capital for manufacturing projects. The Brookfield deal also set a precedent of using outside financing to supplement Intel's own spending budget. It provided $15 billion in effectively free cash flow Intel can redirect to other priorities like new fabs without increasing debt. Intel's latest fundraising efforts for the Ireland site follow a similar equity investment model that leverages outside capital to support its manufacturing expansion plans. Acquiring High-NA EUV machinery for manufacturing is costly, as these machines can reach up to $380 million alone.

ASML has revealed that its cutting-edge High-NA extreme ultraviolet (EUV) chipmaking tools, called High-NA Twinscan EXE, will cost around $380 million each—over twice as much as its existing Low-NA EUV lithography systems that cost about $183 million. The company has taken 10-20 initial orders from the likes of Intel and SK Hynix and plans to manufacture 20 High-NA systems annually by 2028 to meet demand. The High-NA EUV technology represents a major breakthrough, enabling an improved 8 nm imprint resolution compared to 13 nm with current Low-NA EUV tools. This allows chipmakers to produce transistors that are nearly 1.7 times smaller, translating to a threefold increase in transistor density on chips. Attaining this level of precision is critical for manufacturing sub-3 nm chips, an industry goal for 2025-2026. It also eliminates the need for complex double patterning techniques required presently.

However, superior performance comes at a cost - literally and figuratively. The hefty $380 million price tag for each High-NA system introduces financial challenges for chipmakers. Additionally, the larger High-NA tools require completely reconfiguring chip fabrication facilities. Their halved imaging field also necessitates rethinking chip designs. As a result, adoption timelines differ across companies - Intel intends to deploy High-NA EUV at an advanced 1.8 nm (18A) node, while TSMC is taking a more conservative approach, potentially implementing it only in 2030 and not rushing the use of these lithography machines, as the company's nodes are already developing well and on time. Interestingly, the installation process of ASML's High-NA Twinscan EXE 150,000-kilogram system required 250 crates, 250 engineers, and six months to complete. So, production is as equally complex as the installation and operation of this delicate machinery.

Japanese tech giant Canon hopes to shake up the semiconductor manufacturing industry by shipping new low-cost nanoimprint lithography (NIL) machines as early as this year. The technology, which stamps chip designs onto silicon wafers rather than using more complex light-based etching like market leader ASML's systems, could allow Canon to undercut rivals and democratize leading-edge chip production. "We would like to start shipping this year or next year...while the market is hot. It is a very unique technology that will enable cutting-edge chips to be made simply and at a low cost," said Hiroaki Takeishi, head of Canon's industrial group overseeing nanoimprint lithography technological advancement. Nanoimprint machines target a semiconductor node width of 5 nanometers, aiming to reach 2 nm eventually. Takeishi said the technology has primarily resolved previous defect rate issues, but success will depend on convincing customers that integration into existing fabrication plants is worthwhile.

There is skepticism about Canon's ability to significantly disrupt the market led by ASML's expensive but sophisticated extreme ultraviolet (EUV) lithography tools. However, if nanoimprint can increase yields to nearly 90% at lower costs, it could carve out a niche, especially with EUV supply struggling to meet surging demand. Canon's NIL machines are supposedly 40% the cost of ASML machinery, while operating with up to 90% lower power draw. Initially focusing on 3D NAND memory chips rather than complex processors, Canon must contend with export controls limiting sales to China. But with few options left, Takeishi said Canon will "pay careful attention" to sanctions risks. If successfully deployed commercially after 15+ years in development, Canon's nanoimprint technology could shift the competitive landscape by enabling new players to manufacture leading-edge semiconductors at dramatically lower costs. But it remains to be seen whether the new machines' defect rates, integration challenges, and geopolitical headwinds will allow Canon to disrupt the chipmaking giants it aims to compete with significantly.

Intel Corporation today reported fourth-quarter and full-year 2023 financial results. "We delivered strong Q4 results, surpassing expectations for the fourth consecutive quarter with revenue at the higher end of our guidance," said Pat Gelsinger, Intel CEO. "The quarter capped a year of tremendous progress on Intel's transformation, where we consistently drove execution and accelerated innovation, resulting in strong customer momentum for our products. In 2024, we remain relentlessly focused on achieving process and product leadership, continuing to build our external foundry business and at-scale global manufacturing, and executing our mission to bring AI everywhere as we drive long-term value for stakeholders."

David Zinsner, Intel CFO, said, "We continued to drive operational efficiencies in the fourth quarter, and comfortably achieved our commitment to deliver $3 billion in cost savings in 2023. We expect to unlock further efficiencies in 2024 and beyond as we implement our new internal foundry model, which is designed to drive greater transparency and accountability and higher returns on our owners' capital." For the full year, the company generated $11.5 billion in cash from operations and paid dividends of $3.1 billion.

AMD is looking to debut its Ryzen 9000 series "Granite Ridge" desktop processors based on the "Zen 5" microarchitecture some time around May-June 2024, according to High Yield YT, a reliable source with AMD leaks. These processors will be built in the existing Socket AM5 package, and be compatible with all existing AMD 600 series chipset motherboards. It remains to be seen if AMD debuts a new line of motherboard chipsets. Almost all Socket AM5 motherboards come with the USB BIOS flashback feature, which means motherboards from even the earliest production batches that are in the retail channel, should be able to easily support the new processors.

AMD is giving its next-gen desktop processors the Ryzen 9000 series processor model numbering, as it used the Ryzen 8000 series for its recently announced Socket AM5 desktop APUs based on the "Hawk Point" monolithic silicon. "Granite Ridge" will be a chiplet-based processor, much like the Ryzen 7000 series "Raphael." In fact, it will even retain the same 6 nm client I/O die (cIOD) as "Raphael," with some possible revisions made to increase its native DDR5 memory frequency (up from the current DDR5-5200), and improve its memory overclocking capabilities. It's being reported that DDR5-6400 could be the new "sweetspot" memory speed for these processors, up from the current DDR5-6000.

Today, ASML Holding NV (ASML) has published its 2023 fourth quarter and full-year results.

• Q4 net sales of €7.2 billion, gross margin of 51.4%, net income of €2.0 billion
• Quarterly net bookings in Q4 of €9.2 billion of which €5.6 billion is EUV
• 2023 net sales of €27.6 billion, gross margin of 51.3%, net income of €7.8 billion
• ASML expects 2024 net sales to be similar to 2023
• ASML expects Q1 2024 net sales between €5.0 billion and €5.5 billion and a gross margin between 48% and 49%

CEO statement and outlook
"Our fourth-quarter net sales came in at €7.2 billion with a gross margin of 51.4%, both slightly above our guidance. ASML achieved another strong year in 2023 with 30% growth, ending with total net sales for the year of €27.6 billion, a gross margin of 51.3% and a backlog of €39 billion. We shipped the first modules of the first High NA EUV system, EXE:5000, to a customer before the end of the year."