Intel Corporation today revealed one of the most detailed process and packaging technology roadmaps the company has ever provided, showcasing a series of foundational innovations that will power products through 2025 and beyond. In addition to announcing RibbonFET, its first new transistor architecture in more than a decade, and PowerVia, an industry-first new backside power delivery method, the company highlighted its planned swift adoption of next-generation extreme ultraviolet lithography (EUV), referred to as High Numerical Aperture (High NA) EUV. Intel is positioned to receive the first High NA EUV production tool in the industry.

"Building on Intel's unquestioned leadership in advanced packaging, we are accelerating our innovation roadmap to ensure we are on a clear path to process performance leadership by 2025," Intel CEO Pat Gelsinger said during the global "Intel Accelerated" webcast. "We are leveraging our unparalleled pipeline of innovation to deliver technology advances from the transistor up to the system level. Until the periodic table is exhausted, we will be relentless in our pursuit of Moore's Law and our path to innovate with the magic of silicon."

SK hynix Inc. today announced financial results for its second quarter 2021 ended on June 30, 2021. The consolidated revenue of the second quarter 2021 was 10.322 trillion won, while the operating profit amounted to 2.695 trillion won and the net income 1.988 trillion won. Operating margin for the quarter was 26% and net margin was 19%.

It was the first time in three years that SK hynix recorded the quarterly revenue of more than 10 trillion won as the memory market condition, which began to recover earlier this year, continued to improve in the second quarter. The company last logged more than 10 trillion won in the third quarter of 2018 when the memory market was booming.

SK hynix announced that it has started this month mass production of the 8 Gigabit (Gb) LPDDR4 mobile DRAM based on the 1anm, which is the fourth generation of the 10 nm process technology. As the semiconductor industry classifies the 10 nm DRAM products, naming them after the alphabets, the 1a technology is the fourth generation, following the first three generations of the 1x, 1y, and 1z. SK hynix plans to provide the latest mobile DRAM products to smartphone manufacturers from the second half of 2021. This is the first time that SK hynix adopted the EUV equipment for mass production after proving the stability of the cutting edge lithography technology through partial adoption for its 1ynm DRAM production.

As technology migration continues to ultra-micro levels, an increasing number of semiconductor companies are adopting the EUV equipment for the photo process where circuit patterns are drawn on the wafer surfaces. Industry experts believe that a semiconductor company's leadership in technology will depend on how it can fully take advantage of the EUV equipment. SK hynix plans to use the EUV technology for production of all its 1anm DRAM products going forward as it has proved the stability of the process.

Semiconductor manufacturing is no easy task. Every company in that business knows that, and the hardships of silicon manufacturing have been felt by even the greatest players like Samsung and Intel. Today, according to the latest report from Business Korea, Samsung is again in trouble with its 5 nm node. It has been reported previously that Samsung is struggling with yields of its 5 nm node, however, we didn't know just how much until now. According to the sources over at Business Korea, Samsung's 5 nm semiconductor node is experiencing less than 50% yields. That means, for example, that out of 100 chips manufactured on a single silicon wafer, only half are functional. And that is not good at all.

Usually, for a node to go into high-volume manufacturing (HVM), the yielding rate needs to be around 95%. In case it is not at that level, manufacturing of that node is not very efficient and not very profitable. The V1 Line in Hwaseong, where this Samsung 5 nm is made, uses EUV tools to manufacture the new node. While the yields are currently below 50%, it is expected to improve as Samsung engineers tweak and tune the node and the tools that are running the facility. We can expect to hear more about the yields of this node in the coming months.

Samsung's ambitious 3 nm silicon fabrication node that leverages the Gate All Around FET transistors, has reportedly been delayed to 2024. The company brands this specific node as 3GAE. 2024 is the earliest date when Samsung will be able to mass-produce chips on 3GAE, which means the company, along with Intel, will begin to fall significantly behind TSMC on foundry technology. The Taiwanese semiconductor fabrication giant will target 2 nm-class nodes around 2024, which leverages EUV multi-patterning, extensive use of cobalt in contacts and interconnects, germanium doped channels, and other in-house innovations. With Intel's foundry technology development slowing to a crawl in the sub-10 nm domain, Samsung is the only viable alternative to TSMC for cutting-edge logic chip manufacturing.

Samsung Electronics plans to build a new cutting-edge semiconductor fab in Austin, Texas, according to an ETimes report. An official announcement to this effect will be made later today, when South Korean President Moon and U.S. President Biden are scheduled to hold their first Summit meeting, in Washington DC. The facility will offer third-party contract manufacturing of semiconductor chips on the 5 nanometer EUV process. Samsung has earmarked an investment of $18 billion toward the construction of this fab, which will be located close to the company's existing foundry in Texas, which manufactures chips on the 14 nm node. Samsung's investment is in response to rising demand of high-volume logic chips by major American firms such as Amazon, Google, Microsoft, and Tesla.

SK hynix Inc. today announced financial results for its first quarter 2021 ended on March 31, 2021. The consolidated revenue of the first quarter 2021 was 8.494 trillion won while the operating profit amounted to 1.324 trillion won, and the net income 993 billion won. Operating margin for the quarter was 16% and net margin was 12%.

The Company made better results both QoQ and YoY in the first quarter as the semiconductor market conditions improved earlier this year. Although the first quarter is usually off-season of the semiconductor industry, the Company said that the market conditions improved as demand for memory products for PCs and mobiles increased. In addition, cost competitiveness has increased as yields of major products have improved. Through this, the revenue and the operating profit increased by 7% and 37%, respectively, compared to the previous quarter.

On March 22nd, the CEO of SK Hynix, Seok-Hee Lee, gave a keynote speech to the IEEE International Reliability Physics Symposium (IRPS) and shared with experts a part of its plan for the future of SK Hynix products. The CEO took the stage and delivered some conceptual technologies that the company is working on right now. At the center of the show, two distinct products stood out - 3D NAND and DRAM. So far, the company has believed that its 3D NAND scaling was very limited and that it can push up to 500 layers sometime in the future before the limit is reached. However, according to the latest research, SK Hynix will be able to produce 600-layer 3D NAND technology in the distant future.

So far, the company has managed to manufacture and sample 512Gb 176-layer 3D NAND chips, so the 600-layer solutions are still far away. Nonetheless, it is a possibility that we are looking at. Before we reach that layer number, there are various problems needed to be solved so the technology can work. According to SK Hynix, "the company introduced the atomic layer deposition (ALD) technology to further improve the cell property of efficiently storing electric charges and exporting them when needed, while developing technology to maintain uniform electric charges over a certain amount through the innovation of dielectric materials. In addition to this, to solve film stress issues, the mechanical stress levels of films is controlled and the cell oxide-nitride (ON) material is being optimized. To deal with the interference phenomenon between cells and charge loss that occur when more cells are stacked at a limited height, SK Hynix developed the isolated-charge trap nitride (isolated-CTN) structure to enhance reliability."

ASML has finally finished development of EUV (Extreme Ultra Violet) pellicles to be employed in manufacturing processes that use the most energetic frequency of visible light to etch semiconductors onto wafers. Pellicles have been used for decades in the industry, and they are basically ultra-thin membranes that protect photomasks during the etching process - impeding particles from depositing in the substrate, which could lead to defects at the wafer level for every subsequent patterning that is laid on top of the impurity. Manufacturers such as TSMC have deployed EUV-powered manufacturing processes, but they have had to toil with potentially lower yields and increased costs with wafer analysis so as to reduce chances of defects appearing.

It's been a long time coming for EUV-capable pellicles, because these have different requirements compared to their traditional, non-EUV counterparts. However, once they are available on the market, it's expected that all semiconductor manufacturers with bleeding-edge manufacturing processes integrate them into their production flows. These will allow for better yields, which in turn should reduce overall pricing for the manufacturing processes. As an example, these EUV masks could be deployed on TSMC's 7 nm, 6 nm, 5 nm, and so on and so on. Other players other than ASML are also finishing their pellicle design, so the industry will have multiple options to integrate into their processes.

SiPearl has this week announced their collaboration with Open-Silicon Research, the India-based entity of OpenFive, to produce the next-generation SoC designed for HPC purposes. SiPearl is a part of the European Processor Initiative (EPI) team and is responsible for designing the SoC itself that is supposed to be a base for the European exascale supercomputer. In the partnership with Open-Silicon Research, SiPearl expects to get a service that will integrate all the IP blocks and help with the tape out of the chip once it is done. There is a deadline set for the year 2023, however, both companies expect the chip to get shipped by Q4 of 2022.

When it comes to details of the SoC, it is called Rhea and it will be a 72-core Arm ISA based processor with Neoverse Zeus cores interconnected by a mesh. There are going to be 68 mesh network L3 cache slices in between all of the cores. All of that will be manufactured using TSMC's 6 nm extreme ultraviolet lithography (EUV) technology for silicon manufacturing. The Rhea SoC design will utilize 2.5D packaging with many IP blocks stitched together and HBM2E memory present on the die. It is unknown exactly what configuration of HBM2E is going to be present. The system will also see support for DDR5 memory and thus enable two-level system memory by combining HBM and DDR. We are excited to see how the final product looks like and now we wait for more updates on the project.

Samsung has been one of the world's biggest foundries and one of three big players still left in the leading-edge semiconductor process development and manufacturing. However, the Korean giant is always seeking ways to improve its offerings, especially for Western customers. Today, it is reported that Samsung has reportedly talked with regulators in Texas, New York, and Arizona about building a $17 billion silicon manufacturing facility in the United States. The supposed factory is going to be located near Austin, Texas, and is supposed to offer around 1800 jobs. If the deal is approved and Samsung manages to complete the project on time, the factory is supposed to start mass production in Q4 of 2023.

What process is Samsung going to manufacture in the new fab? Well, current speculations are pointing out to the 3 nm node, with Samsung's special GAAFET (Gate All Around FET) technology tied to the new node. The fab is also expected to make use of extreme ultraviolet (EUV) lithography for manufacturing. Samsung already has a facility in the US called S2, however, that will not be upgraded as it is still serving a lot of clients. Instead, the company will build new facilities to accommodate the demand for newer nodes. It is important to note that Samsung will not do any R&D work in the new fab, and the company will only manufacture the silicon there.

SK hynix Inc. held a completion ceremony for its new fabrication plant M16 at headquarter located in Icheon, Gyeonggi-do, South Korea. Under the theme of "We Do Technology: Opening the Happiness", the ceremony was held as SK Group's internal event in order to adhere to the COVID-19 containment measures.

A total of 16 personnel including SK Group Chairman Chey Tae-Won and SK Group Senior Vice Chairman Chey JaeWon, SK SUPEX Council Chairman Cho DaeSik, SK hynix Vice Chairman Park Jung-ho, SK Holdings President & CEO Jang DongHyun, SK hynix CEO Seok-Hee Lee, and SK hynix Lead Independent Director Ha Yung Ku attended the on-site ceremony, along other employees and partner companies' members joined through live video conference.

In the latest report by DigiTimes, it is said that TSMC has placed an order on 13 Extreme Ultra-Violet (EUV) machines from the Dutch company ASML. Thanks to the rapid increase in demand for its silicon, TSMC has developed plans for expansion across the next few years to satisfy the existing and upcoming customers. Usually, the company knows and can predict its demand for a future period. That is why TSMC is expanding its capacities with 13 additional ASML Twinscan NXE EUV scanners. These machines are set to be delivered by the course of 2021. It is unknown exactly when these machines are going to be delivered and installed at TSMC's facilities, however, it is fascinating that the demand for the company's capacities is ever-expanding. The price of single EUV machinery is as much as $175.75 million, so it is estimated that the expansion of capacity will cost TSMC a whopping $2.284,75 million. Despite the high pricing, the Return on Investment (ROI) is very high for TSMC.

During its Q3 earnings call, Samsung Electronics has provided everyone with an update on its foundry and node production development. In the past year or so, Samsung's foundry has been a producer of a 7 nm LPP (Low Power Performance) node as its smallest node. That is now changed as Samsung has started the production of the 5 nm LPE (Low Power Early) semiconductor manufacturing node. In the past, we have reported that the company struggled with yields of its 5 nm process, however, that seems to be ironed out and now the node is in full production. To contribute to the statement that the new node is doing well, we also recently reported that Samsung will be the sole manufacturer of Qualcomm Snapdragon 875 5G SoC.

The new 5 nm semiconductor node is a marginal improvement over the past 7 nm node. It features a 10% performance improvement that is taking the same power and chip complexity or a 20% power reduction of the same processor clocks and design. When it comes to density, the company advertises the node with x1.33 times increase in transistor density compared to the previous node. The 5LPE node is manufactured using the Extreme Ultra-Violet (EUV) methodology and its FinFET transistors feature new characteristics like Smart Difusion Break isolation, flexible contact placement, and single-fin devices for low power applications. The node is design-rule compatible with the previous 7 nm LPP node, so the existing IP can be used and manufactured on this new process. That means that this is not a brand new process but rather an enhancement. First products are set to arrive with the next generation of smartphone SoCs, like the aforementioned Qualcomm Snapdragon 875.

Intel has finally sounded the "full steam ahead" whistle for its Fab 42, set in Arizona. Fab 42 has a storied past to it, as Intel started its construction back in 2011. It was actually finished by 2013, and by 2014 all essential infrastructure for semiconductor fabrication was there - except for the fabrication equipment itself. You see, Intel aimed for this factory to produce 450 mm wafers (instead of the industry standard 300 mm) in the 14 nm process. However, back in 2014, Intel wasn't sure about demand for its 14 nm products - and the company was actually planning to debut 10 nm back in 2016, so it sort of made sense. Of course, then came the 10 nm delays, the 14 nm supply issues, and backporting of certain products to other less cutting-edge processes. If only Intel had had a crystal ball.

TSMC has had quite a good time recently. They are having all of their capacity fully booked and the development of new semiconductor nodes is going good. Today, thanks to the report of DigiTimes, we have found out that TSMC is ramping up the production lines to prepare for 3 nm high-volume manufacturing. The 3 nm node is expected to enter HVM in 2022, which is not that far away. In the beginning, the new node is going to be manufactured on 55.000 wafers of 300 mm size, and it is expected to reach as much as 100.000 wafers per month output by 2023. With the accelerated purchase of EUV machines, TSMC already has all of the equipment required for the manufacturing of the latest node. We are waiting to see more details on the 3 nm node as we approach its official release.

Rumors fresh of South Korean shores claim that Samsung has snagged a position as sole provider for Qualcomm's Snapdragon 875 SoC on its 5 nm EUV manufacturing process. The reason for this, according to a supposed industry insider, boiled down to money (as it almost always does): Samsung simply offered lower pricing for chips manufactured under its 5 nm EUV process than TSMC did. The deal has been claimed to be worth some $840M. This makes sense, as Samsung has a considerable product portfolio - including lucrative memory fabrication - from which it can pool resources so as to lower pricing for new manufacturing technologies, whereas TSMC can only count on revenues it brings in from contracted silicon manufacturing deals.

Samsung's 5 nm EUV will still offer the now tried-and-true FinFet transistor design - next-generation GAAFET (gate all-around FET) are reserved for the companies' 3 nm efforts. This piece of news directly contradicts Digitimes' earlier reporting on Qualcomm leaving Samsung as a foundry partner due to lower than adequate yields for Samsung's 5 nm EUV. With Samsung already manufacturing NVIDIA's Ampere on its 8 nm node, and now with a confirmed high-volume client with Qualcomm, this likely means more available capacity for other TSMC clients - of which we could mention AMD and Apple.

Just ahead of the September launch, specifications of NVIDIA's upcoming RTX Ampere lineup have been leaked by industry sources over at VideoCardz. According to the website, three alleged GeForce SKUs are being launched in September - RTX 3090, RTX 3080, and RTX 3070. The new lineup features major improvements: 2nd generation ray-tracing cores and 3rd generation tensor cores made for AI and ML. When it comes to connectivity and I/O, the new cards use the PCIe 4.0 interface and have support for the latest display outputs like HDMI 2.1 and DisplayPort 1.4a.

The GeForce RTX 3090 comes with 24 GB of GDDR6X memory running on a 384-bit bus at 19.5 Gbps. This gives a memory bandwidth capacity of 936 GB/s. The card features the GA102-300 GPU with 5,248 CUDA cores running at 1695 MHz, and is rated for 350 W TGP (board power). While the Founders Edition cards will use NVIDIA's new 12-pin power connector, non-Founders Edition cards, from board partners like ASUS, MSI and Gigabyte, will be powered by two 8-pin connectors. Next up is specs for the GeForce RTX 3080, a GA102-200 based card that has 4,352 CUDA cores running at 1710 MHz, paired with 10 GB of GDDR6X memory running at 19 Gbps. The memory is connected with a 320-bit bus that achieves 760 GB/s bandwidth. The board is rated at 320 W and the card is designed to be powered by dual 8-pin connectors. And finally, there is the GeForce RTX 3070, which is built around the GA104-300 GPU with a yet unknown number of CUDA cores. We only know that it has the older non-X GDDR6 memory that runs at 16 Gbps speed on a 256-bit bus. The GPUs are supposedly manufactured on TSMC's 7 nm process, possibly the EUV variant.

TSMC had been working super hard in the past few years and has been investing in lots of new technologies to drive the innovation forward. At TSMC's Technology Symposium held this week was, the company has presented various things like the update on its 12 nm node, as well as future plans for node development. One of the most interesting announcements made this week was TSMC's state and ownership of Extreme Ultra-Violet (EUV) machines. ASML, the maker of these EUV machines used to etch the pattern on silicon, has been the supplier of the Taiwanese company. TSMC has announced that they own an amazing 50% of all EUV machine installations.

What is more important is the capacity that the company achieves with it. It is reported that TSMC achieves 60% of all EUV wafer capacity in the world, which is a massive achievement of what TSMC can do with the equipment. The company right now has only two nodes on EUV in high-volume manufacturing, the 7 nm+ node and 5 nm node (which is going HVM in Q4), however, that is more than any of its competitors. All of the future nodes are to be manufactured using the EUV machines and the smaller nodes require it. As far as the competitors go, only Samsung is currently making EUV silicon on the 7 nm LPP node. Intel is yet to release some products on a 7 nm node of its own, which is the first EUV node from the company.

TSMC on Monday kicked off a virtual tech symposium, where it announced its new 12 nm N12e node for IoT edge devices, announced the new 3DFabric Technology, and detailed progress on its upcoming 5 nm N5 and 3 nm N3 silicon fabrication nodes. The company maintains that the N5 (5 nm) node offers the benefits of a full node uplift over its current-gen N7 (7 nm), which recently clocked over 1 billion chips shipped. The N5 node incorporates EUV lithography more extensively than N6/N7+, and in comparison to N7 offers 30% better power at the same performance, 15% more performance at the same power, and an 80% increase in logic density. The company has commenced high-volume manufacturing on this node.

2021 will see the introduction and ramp-up of the N5P node, an enhancement of the 5 nm N5 node, offering a 10% improvement in power at the same performance, or 5% increase in performance at the same power. A nodelet of the N5 family of nodes, called N4, could see risk production in Q4 2021. The N4 node is advertised as "4 nm," although the company didn't get into its iso-power/iso-performance specifics over the N5 node. The next major node for TSMC will be the 3 nm N3 node, with massive 25%-30% improvement in power at the same performance, or 10%-15% improvement in performance at same power, compared to N5. It also offers a 70% logic density gain over N5. 3DFabric technology is a new umbrella term for TSMC's CoWoS (chip on wafer on substrate), CoW (chip on wafer), and WoW (wafer on wafer) 3-D packaging innovations, with which it plans to offer packaging innovations that compete with Intel's various new 3D chip packaging technologies on the anvil.

In a bid to show off its volume production prowess and technological edge (but mostly to rub it in to rival fabs), TSMC on Thursday announced that it shipped its 1 billionth chip fabricated on its 7 nm process. If these dies were combined into one big rectangular wafer, they would cover 13 New York City blocks. TSMC's 7 nm process debuted with its N7 node, which went into volume production in April 2018, over two years ago. The fab has since mass-produced 7 nm chips for the likes of Qualcomm, Apple, and AMD, among dozens of other clients. The company now looks to monetize refinements of N7, namely the N7e and N7P (DUV refinements), while executing its crucial EUV-based N7+ node, leading up to future nodelets such as N6. Much of TSMC's growth will be propelled by 5G modems, application processors, and its pivotal role in the growth of companies such as AMD.

Samsung Electronics Co., Ltd., a world leader in advanced semiconductor technology, today announced the immediate availability of its silicon-proven 3D IC packaging technology, eXtended-Cube (X-Cube), for today's most advanced process nodes. Leveraging Samsung's through-silicon via (TSV) technology, X-Cube enables significant leaps in speed and power efficiency to help address the rigorous performance demands of next-generation applications including 5G, artificial intelligence, high-performance computing, as well as mobile and wearable.

"Samsung's new 3D integration technology ensures reliable TSV interconnections even at the cutting-edge EUV process nodes," said Moonsoo Kang, senior vice president of Foundry Market Strategy at Samsung Electronics. "We are committed to bringing more 3D IC innovation that can push the boundaries of semiconductors."

Samsung Electronics reported today KRW 52.97 trillion in consolidated revenue and KRW 8.15 trillion in operating profit for the second quarter ended June 30, 2020. Even as the spread of COVID-19 caused closures and slowdowns at stores and production sites around the world, the Company responded to challenges through its extensive global supply chain, while minimizing the impact of the pandemic by strengthening online sales channels and optimizing costs.

Quarterly operating profit rose 26 percent from the previous quarter and 23 percent from a year earlier, thanks to firm demand for memory chips and appliances, as well as a one-off gain at its Display Panel Business. A partial recovery in global demand since May also helped offset some COVID-19 effects, resulting in higher earnings than initially expected. Revenue in the quarter fell 4 percent from the previous quarter and 6 percent from a year earlier due to reduced sales of smartphones and other devices.

Semiconductor manufacturing is a difficult process. Often when a new node is being developed, there are new materials introduced that may cause some yield issues. Or perhaps with 7 nm and below nodes, they are quite difficult to manufacture due to their size, as the transistor can get damaged by the smallest impurity in silicon. So manufacturers have to be extra careful and must spend more time on the development of new nodes. According to industry sources over at DigiTimes, we have information that Samsung is struggling with its 5 nm EUV node.

This unfortunate news comes after the industry sources of DigiTimes reported that Qualcomm's next-generation 5G chipsets could be affected if Samsung doesn't improve its yields. While there are no specific pieces of information on what is the main cause of bad yields, there could be a plethora of reasons. From anything related to manufacturing equipment to silicon impurities. We don't know yet. We hope that Samsung can sort out these issues in time, so Qualcomm wouldn't need to reserve its orders at rival foundries and port the design to a new process.

TSMC is reportedly planning a stopgap between its 5 nm-class silicon fabrication nodes, and the 3 nm-class, called N4. According to the foundry's CEO, Liu Deyin, speaking at a shareholders meeting, N4 will be a 4 nm node, and an enhancement of N5P, the company's most advanced 5 nm-class node. N4 is slated for mass-production of contracted products in 2023, and could help TSMC's customers execute their product roadmaps of the time. From the looks of it, N4 is a repeat of the N6 story: a nodelet that's an enhancement of N7+, the company's most advanced 7 nm-class node that leverages EUV lithography.