Monday, June 13th 2022
Intel 4 Process Node Detailed, Doubling Density with 20% Higher Performance
Intel's semiconductors nodes have been quite controversial with the arrival of the 10 nm design. Years in the making, the node got delayed multiple times, and only recently did the general public get the first 10 nm chips. Today, at IEEE's annual VLSI Symposium, we get more details about Intel's upcoming nodes, called Intel 4. Previously referred to as a 7 nm process, Intel 4 is the company's first node to use EUV lithography accompanied by various technologies. The first thing when a new process node is discussed is density. Compared to Intel 7, Intel 4 will double the transistor count for the same area and enable 20% higher performing transistors.
Looking at individual transistor size, the new Intel 4 node represents a very tiny piece of silicon that is even smaller than its predecessor. With a Fin Pitch of 30 nm, Contact Gate Poly Pitch of 50 nm between gates, and Minimum Metal Pitch (M0) of 50 nm, the Intel 4 transistor is significantly smaller compared to the Intel 7 cell, listed in the table below. For scaling, Intel 4 provides double the number of transistors in the same area compared to Intel 7. However, this reasoning is applied only to logic. For SRAM, the new PDK provides 0.77 area reduction, meaning that the same SoC built on Intel 7 will not be half the size of Intel 4, as SRAM plays a significant role in chip design. The Intel 7 HP library can put 80 million transistors on a square millimeter, while Intel 4 HP is capable of 160 million transistors per square millimeter.Regarding individual transistor layers, Intel had some fun with them as the company now put 16 layers of metal for logic in the Intel 4 node, compared to 15 in the Intel 7 PDK. The gate is made from Tungsten, while the first four metal layers are made from Copper with Cobalt Cladding, ensuring better performance than plain Copper. For the remaining layers, pure Copper is used for interconnecting the wiring.
In the manufacturing process of Intel 4, the company is using EUV for the first time and achieving great results. The number of steps to manufacture the chip is now reduced, and it is reported that the number of masks for etching is reduced by 20% compared to Intel 7, thanks to more powerful EUV lithography tools. If not for EUV, the number of masks for this type of transistor would need to jump by 30% as the multi-patterning process is very complicated.
And last but not least comes the performance of these new transistors. At iso-power of 0.65 Volts, Intel reports a 21.5% gain in sustainable frequency with Intel 4 compared to Intel 7. At higher power like 0.84 Volts, the curve flattens to about 10% improvement. For iso-frequency tests, the company reports 40% lower power consumption measured at 2.1 GHz transistor switching speed.First products based on the new node are set to arrive sometimes in 2023, with Meteor Lake-P designs hitting the shelves first. Other SKUs are expected to follow and we are eager to see how good this semiconductor manufacturing node turns out to be.
Looking at individual transistor size, the new Intel 4 node represents a very tiny piece of silicon that is even smaller than its predecessor. With a Fin Pitch of 30 nm, Contact Gate Poly Pitch of 50 nm between gates, and Minimum Metal Pitch (M0) of 50 nm, the Intel 4 transistor is significantly smaller compared to the Intel 7 cell, listed in the table below. For scaling, Intel 4 provides double the number of transistors in the same area compared to Intel 7. However, this reasoning is applied only to logic. For SRAM, the new PDK provides 0.77 area reduction, meaning that the same SoC built on Intel 7 will not be half the size of Intel 4, as SRAM plays a significant role in chip design. The Intel 7 HP library can put 80 million transistors on a square millimeter, while Intel 4 HP is capable of 160 million transistors per square millimeter.Regarding individual transistor layers, Intel had some fun with them as the company now put 16 layers of metal for logic in the Intel 4 node, compared to 15 in the Intel 7 PDK. The gate is made from Tungsten, while the first four metal layers are made from Copper with Cobalt Cladding, ensuring better performance than plain Copper. For the remaining layers, pure Copper is used for interconnecting the wiring.
In the manufacturing process of Intel 4, the company is using EUV for the first time and achieving great results. The number of steps to manufacture the chip is now reduced, and it is reported that the number of masks for etching is reduced by 20% compared to Intel 7, thanks to more powerful EUV lithography tools. If not for EUV, the number of masks for this type of transistor would need to jump by 30% as the multi-patterning process is very complicated.
And last but not least comes the performance of these new transistors. At iso-power of 0.65 Volts, Intel reports a 21.5% gain in sustainable frequency with Intel 4 compared to Intel 7. At higher power like 0.84 Volts, the curve flattens to about 10% improvement. For iso-frequency tests, the company reports 40% lower power consumption measured at 2.1 GHz transistor switching speed.First products based on the new node are set to arrive sometimes in 2023, with Meteor Lake-P designs hitting the shelves first. Other SKUs are expected to follow and we are eager to see how good this semiconductor manufacturing node turns out to be.
15 Comments on Intel 4 Process Node Detailed, Doubling Density with 20% Higher Performance
And why is the Soc so big, usually the memory controller is as big as a dual core.
This is the shrink we have all been waiting for.., finally moving away from DUV. Its the whole reason TSMC is ahead of the curve right now.
Their 10nm process also had slides like those, and it still isn't going well as indicated by their inability to make huge Xeon dies in high volumes: www.techpowerup.com/295694/intel-xeon-sapphire-rapids-volume-shipping-delayed-again-company
It's also the second time Sapphire Rapids got delayed.
Don't get me wrong, I love competition, and wish Intel well, but they have a history of spamming PR campaigns to mask failures.
All that techno-babble, yet notta nuthin new or betta available yet to install into my rig, so therefore, it just moar V*A*P*O*R*warez to me....
@AleksandarK... was the above an actual press release, some copy/paste of speculations from some unknown insider, or just a compilation of random info from across the interwebz ? just wondering :)
But one thing to keep in mind is the move from 14nm->10 nm was an extremely ambitious step where Intel was trying to accomplish 2.7x density scaling from the node shrink, without using EUV, and instead it used multi patterning. EUV was not ready yet... Now is different. EUV is ready as shown off by TSMC , and with 10nm/Intel7 -> Intel 4 ... intel is using EUV and has a lower density scaling target of only 2x. And apparently, EUV allows them to simplify the lithography process from 4 or more steps to one step.
So the factors and considerations of the node shrink this time around are different from 14->10.
Intel achieved going from Intel7 to Intel4, 2X logic density and 1.3X SRAM density.
They should focus more regarding SRAM density scaling, they will need it in the future!
But if you really must know, my system specs are shown in my profile :)