Samsung has achieved better production results for its advanced memory technology, according to Sedaily, as cited by TrendForce. The company's sixth-generation 10 nm DRAM, called 1c DRAM, now shows yield rates of 50-70% in testing. This represents a significant improvement from last year's results, which were below 30%. Samsung takes a different path from its rivals, while SK Hynix and Micron stick with 1b DRAM technology for HBM4 products, Samsung opts to create the newer 1c DRAM. This choice comes with more risk; however, it might bring bigger rewards, as the improved production rates enable Samsung to expand its manufacturing operations. The company plans to increase 1c DRAM production at its Hwaseong and Pyeongtaek facilities with expansion activities expected to begin before the end of this year.

These developments also support Samsung's HBM4 production schedule since the company aims to begin mass production of HBM4 products later this year. Yet, experts in the field point out that the product is still in its early stages and needs ongoing monitoring. Samsung planned to begin mass-producing sixth-gen 10 nm DRAM by late 2024. Instead, the company chose to remake the chip's design. This decision caused delays of more than one year however it was made to achieve better performance and yields. The new DRAM products will be manufactured at Samsung's Pyeongtaek Line 4 facility as these chips will serve both mobile and server applications. Separately, HBM4-related production will take place at Pyeongtaek Line 3.

The vast majority of High Bandwidth Memory (HBM) new stories—so far, in 2025—have involved or alluded to new-generation SK hynix and Micron products. As mentioned in recently published Samsung Electronics Q1 financial papers, company engineers are still working on "upcoming enhanced HBM3E products." Late last month, a neighbor/main rival publicly showcased their groundbreaking HBM4 memory solution—indicating a market leading development position. Samsung has officially roadmapped a futuristic "sixth-generation" HBM4 technology, but their immediate focus seems to be a targeted sales expansion of incoming "enhanced HBM3E 12H" products. Previously, the firm's Memory Business has lost HBM3 ground—within AI GPU/accelerator market segments—to key competitors.

Industry insiders believe that company leadership will attempt to regain lost market shares in a post-2025 world. As reported by South Korean news outlets, Kim Jae-joon (VP of Samsung's memory department) stated—during a recent earnings call, with analysts—that his team is: "already collaborating with multiple customers on custom versions based on both HBM4 and the enhanced HBM4E." The initiation of commercial shipments is anticipated at some point in 2026, hinging on mass production starting by the second half of this year. The boss notified listeners about development "running on schedule." A Hankyung article alleges that Samsung HBM4 evaluation samples have been sent out to "NVIDIA, Broadcom, and Google." Wccftech posits a positive early outlook: "Samsung will use its own 4 nm process from the foundry division and utilize the 10 nm 6th-generation 1c DRAM, which is known as one of the highest-end in the market. On paper, (their) HBM4 solution will be on par with competing models (from SK hynix), but we will have to wait and see."

Ferroelectric Memory Co. (FMC) and Neumonda have formed a partnership to commercialize "DRAM+," a ferroelectric (FeRAM) memory architecture combining DRAM's speed with non-volatile data retention. The technology substitutes conventional capacitors with ferroelectric hafnium oxide (HfO₂) elements, allowing persistent storage without power while maintaining nanosecond access times. This hybrid technology addresses the performance gap between high-speed DRAM and storage-class memory like NAND flash. Unlike previous European DRAM ventures from Infineon and Qimonda that failed against commodity memory economics, FMC targets specialized applications valuing persistence and power efficiency. The HfO₂-based approach resolves limitations of previous FeRAM memory implementations using lead zirconate titanate (PZT) that couldn't scale beyond megabyte capacities.

Prototypes now demonstrate gigabit-range densities compatible with sub-10 nm fabrication of traditional DRAM made by Micron, Samsung, SK Hynix, and others. By eliminating refresh cycles, DRAM+ reduces static power consumption substantially compared to traditional one-transistor/one-capacitor DRAM cells. Primary applications include AI accelerators requiring persistent model weights, automotive ECUs with immediate startup requirements, and power-constrained medical implants. Neumonda will contribute its test platform suite Rhinoe, Octopus, and Raptor for electrical characterization and analytics at lower capital costs than standard semiconductor test equipment. No production timeline has been announced for commercial DRAM+ products.

Micron Technology, Inc., today announced it is the first in the industry to ship samples of its 1γ (1-gamma), sixth-generation (10 nm-class) DRAM node-based DDR5 memory designed for next-generation CPUs to ecosystem partners and select customers. This 1γ DRAM milestone builds on Micron's previous 1α (1-alpha) and 1β (1-beta) DRAM node leadership to deliver innovations that will power future computing platforms from the cloud to industrial and consumer applications to Edge AI devices like AI PCs, smartphones and automobiles. The Micron 1γ DRAM node will first be leveraged in its 16 Gb DDR5 DRAM and over time will be integrated across Micron's memory portfolio to meet the industry's accelerating demand for high-performance, energy-efficient memory solutions for AI. Designed to offer speed capabilities of up to 9200 MT/s, the 16 Gb DDR5 product provides up to a 15% speed increase and over 20% power reduction compared to its predecessor.

Nanya Technology's Board of Directors today has approved a strategic partnership with PieceMakers Technology, Inc. ("PieceMakers") to jointly develop customized ultra-high-bandwidth memory solutions. As part of the collaboration, Nanya Technology will subscribe to a cash capital increase of up to NT$ 660 million, purchasing up to 22 million common shares at NT$ 30 per share in PieceMakers. Upon completion of the capital increase, Nanya Technology is expected to acquire up to approximately 38% stakes of PieceMakers.

To meet the growing demand for high-performance memory driven by AI and edge computing, this collaboration will combine Nanya Technology's 10 nm-class DRAM innovation with PieceMakers' expertise in customized DRAM design to develop high-value, high-performance, and low-power customized ultra-high-bandwidth memory solutions, unlocking new opportunities in AI and high-performance computing markets.

As a quick follow-up to last week's "Arrow Lake-S" de-lidding by Madness727, we now have a line-up of a de-lidded Core Ultra 9 285K "Arrow Lake-S" processor placed next to a Core i9-14900K "Raptor Lake-S," and the Core i9-12900K "Alder Lake-S." The tile-based "Arrow Lake-S" is visibly larger than the two, despite being made on more advanced foundry nodes. Both the 8P+16E "Raptor Lake-S" and 8P+8E "Alder Lake-S" chips are built on the Intel 7 node (10 nm Enhanced SuperFin). The "Raptor Lake-S" monolithic chip comes with a die-area of 257 mm². The "Alder Lake-S" is physically smaller, at 215 mm². What sets the two apart isn't just the two additional E-core clusters on "Raptor Lake-S," but also larger caches—2 MB of L2 per P-core, increased form 1.25 MB/core, and 4 MB per E-core cluster, increased from 2 MB/cluster.

Thanks to high quality die-shots of the "Arrow Lake-S" by Madness727, we have our first die-area estimations by A Hollow Knight on Twitter. The LGA1851 fiberglass substrate has the same dimensions as the LGA1700 substrate. This is to ensure the socket retains cooler compatibility. Using geometrical measurements, the base tile of the "Arrow Lake-S" is estimated to be 300.9 mm² in area. The base-tile is a more suitable guideline for "die-area," since Intel uses filler tiles to ensure gaps in the arrangement of logic tiles are filled, and the chip aligns with the base-tile below. The base tile, built on an Intel 22 nm foundry node, serves like a silicon interposer, facilitating high-density microscopic wiring between the various logic tiles stacked on top, and an interface to the fiberglass substrate below.

SK hynix announced today that it has developed the industry's first 16 Gb DDR5 built using its 1c node, the sixth generation of the 10 nm process. The success marks the beginning of the extreme scaling to the level closer to 10 nm in the memory process technology. The degree of difficulty to advance the shrinking process of the 10 nm-range DRAM technology has grown over generations, but SK hynix has become the first in the industry to overcome the technological limitations by raising the level of completion in design, thanks to its industry-leading technology of the 1b, the fifth generation of the 10 nm process.

SK hynix said it will be ready for mass production of the 1c DDR5 within the year to start volume shipment next year. In order to reduce potential errors stemming from the procedure of advancing the process and transfer the advantage of the 1b, which is widely applauded for its best performing DRAM, in the most efficient way, the company extended the platform of the 1b DRAM for development of 1c. The new product comes with an improvement in cost competitiveness, compared with the previous generation, by adopting a new material in certain process of the extreme ultraviolet, or EUV, while optimizing the EUV application process of total. SK hynix also enhanced productivity by more than 30% through technological innovation in design.

According to Bloomberg's latest investigation, Huawei and Semiconductor Manufacturing International Corporation (SMIC) have submitted patents on the self-aligned quadruple patterning (SAQP) pattern etching technique to enable SMIC to achieve 5 nm semiconductor production. The two Chinese giants have been working with the Deep Ultra Violet (DUV) machinery to develop a pattern etching technique allowing SMIC to produce a node compliant with the US exporting rules while maintaining the density improvements from the previously announced 7 nm node. In the 7 nm process, SMIC most likely used self-aligned dual patterning (SADP) with DUV tools, but for the increased density of the 5 nm node, a doubling to SAQP is required. In semiconductor manufacturing, lithography tools take multiple turns to etch the design of the silicon wafer.

Especially with smaller nodes getting ever-increasing density requirements, it is becoming challenging to etch sub-10 nm designs using DUV tools. That is where Extreme Ultra Violet (EUV) tools from ASML come into play. With EUV, the wavelengths of the lithography printers are 14 times smaller than DUV, at only 13.5 nm, compared to 193 nm of ArF immersion DUV systems. This means that without EUV, SMIC has to look into alternatives like SAQP to increase the density of its nodes and, as a result, include more complications and possibly lower yields. As an example, Intel tried to use SAQP in its first 10 nm nodes to reduce reliance on EUV, which resulted in a series of delays and complications, eventually pushing Intel into EUV. While Huawei and SMIC may develop a more efficient solution for SAQP, the use of EUV is imminent as the regular DUV can not keep up with the increasing density of semiconductor nodes. Given that ASML can't ship its EUV machinery to China, Huawei is supposedly developing its own EUV machines, but will likely take a few more years to show.

In addition to the 37 Gbps GDDR7 memory, Samsung Electronics prepares to showcase several other memory innovations at the 2024 IEEE-SSCC as compiled by VideoCardz. To begin with, the company is showcasing a new 280-layer 3D QLC NAND flash memory in the 1 Tb density, enabling next generation of mainstream SSDs and smartphone storage. This chip offers an areal density of 28.5 Gb/mm², and a speed of 3.2 GB/s. To put this into perspective, the fastest 3D NAND flash types powering the current crop of flagship NVMe SSDs rely on 2.4 GB/s of I/O data rates.

Next up, is a new generation DDR5 memory chip offers data rates of DDR5-8000 with a density of 32 Gbit (4 GB). This chip uses a symmetric-mosaic DRAM cell architecture, and is built on a 5th generation 10 nm class foundry node Samsung optimized for DRAM products. What's impressive about this chip is that it will allow PC memory vendors to build 32 GB and 48 GB DIMMs in single-rank configuration with DDR5-8000 speeds; as well as 64 GB and 96 GB DIMMs in dual-rank configuration (impressive, provided your platform can play well with DDR5-8000 in dual-rank).

Ayar Labs, a leader in silicon photonics for chip-to-chip connectivity, will showcase its in-package optical I/O solution integrated with Intel's industry-leading Agilex Field-Programmable Gate Array (FPGA) technology. In demonstrating 5x current industry bandwidth at 5x lower power and 20x lower latency, the optical FPGA - packaged in a common PCIe card form factor - has the potential to transform the high performance computing (HPC) landscape for data-intensive workloads such as generative artificial intelligence (AI), machine learning, and support novel new disaggregated compute and memory architectures and more.

"We're on the cusp of a new era in high performance computing as optical I/O becomes a 'must have' building block for meeting the exponentially growing, data-intensive demands of emerging technologies like generative AI," said Charles Wuischpard, CEO of Ayar Labs. "Showcasing the integration of Ayar Labs' silicon photonics and Intel's cutting-edge FPGA technology at Supercomputing is a concrete demonstration that optical I/O has the maturity and manufacturability needed to meet these critical demands."

WEROCK Technologies GmbH, innovative manufacturer of industrial computer technology, continues its innovative Rocksmart model series and introduces the latest member: the Rocksmart RSC612. The powerful industrial panel PC builds on the success of the Rocksmart RSC610 and expands the possibilities for machine and plant construction as well as the automation industry.

The demands placed on modern technological applications are constantly increasing. The new Rocksmart RSC612 Industrial Panel PC has been specially developed to meet these requirements and offers a wide range of functions. Like the recently introduced Rocksmart RSC610, the new model offers a slim aluminium housing for a modern aesthetic and IP65 protection on the front. The completely passive cooling and the wide operating temperature range ensure a wide range of applications. The Panel PC can be mounted in control cabinets or positioned anywhere thanks to VESA mounting points.

SK hynix announced on September 22 that it showcased its latest memory technologies and products at Intel Innovation 2023 held September 19-20 in the western U.S. city of San Jose, California. Hosted by Intel since 2019, Intel Innovation is an annual IT exhibition which brings together the technology company's customers and partners to share the latest developments in the industry. At this year's event held at the San Jose McEnery Convention Center, SK hynix showcased its advanced semiconductor memory products which are essential in the generative AI era under the slogan "Pioneer Tomorrow With the Best."

Products that garnered the most interest were HBM3, which supports the high-speed performance of AI accelerators, and DDR5 RDIMM, a DRAM module for servers with 1bnm process technology. As one of SK hynix's core technologies, HBM3 has established the company as a trailblazer in AI memory. SK hynix plans to further strengthen its position in the market by mass-producing HBM3E (Extended) from 2024. Meanwhile, DDR5 RDIMM with 1bnm, or the 5th generation of the 10 nm process technology, also offers outstanding performance. In addition to supporting unprecedented transfer speeds of more than 6,400 megabits per second (Mbps), this low-power product helps customers simultaneously reduce costs and improve ESG performance.

SK hynix Inc. today reported financial results for the second quarter of 2023. The company recorded revenue of 7.306 trillion won, operating loss of 2.882 trillion won (with operating margin of negative 39%), and net loss of 2.988 trillion won (with net margin of negative 41%) for the three-month period ended June 30, 2023.

"Amid an expansion in generative artificial intelligence (AI) market, which has largely been centered on ChatGPT, demand for AI server memory has increased rapidly," the company said. "As a result, sales of premium products such as HBM3 and DDR5 increased, leading to a 44% sequential increase in revenue for the second quarter, while operating loss narrowed by 15%."

SK hynix Inc. announced today that it has completed the development of the industry's most advanced 1bnm, the fifth-generation of the 10 nm process technology, while the company and Intel began a joint evaluation of 1bnm and validation in the Intel Data Center Certified memory program for DDR5 products targeted at Intel Xeon Scalable platforms.

The move comes after SK hynix became the first in the industry to reach 1anm readiness and completed Intel's system validation of the 1anm DDR5, the fourth-generation of the 10 nm technology. The DDR5 products provided to Intel run at the world's fastest speed of 6.4 Gbps (Gigabits per second), representing a 33% improvement in data processing speed compared with test-run products in early days of DDR5 development.

Finding itself embattled with AMD's EPYC "Genoa" processors, Intel is giving its 4th Gen Xeon Scalable "Sapphire Rapids" processor a rather quick succession in the form of the Xeon Scalable "Emerald Rapids," bound for Q4-2023 (about 8-10 months in). The new processor shares the same LGA4677 platform and infrastructure, and much of the same I/O, but brings about two key design changes that should help Intel shore up per-core performance, making it competitive to EPYC "Zen 4" processors with higher core-counts. SemiAnalysis compiled a nice overview of the changes, the two broadest points of it being—1. Intel is peddling back on the chiplet approach to high core-count CPUs, and 2., that it wants to give the memory sub-system and inter-core performance a massive performance boost using larger on-die caches.

The "Emerald Rapids" processor has just two large dies in its extreme core-count (XCC) avatar, compared to "Sapphire Rapids," which can have up to four of these. There are just three EMIB dies interconnecting these two, compared to "Sapphire Rapids," which needs as many as 10 of these to ensure direct paths among the four dies. The CPU core count itself doesn't see a notable increase. Each of the two dies on "Emerald Rapids" physically features 33 CPU cores, so a total of 66 are physically present, although one core per die is left unused for harvesting, the SemiAnalysis article notes. So the maximum core-count possible commercially is 32 cores per die, or 64 cores per socket. "Emerald Rapids" continues to be based on the Intel 7 process (10 nm Enhanced SuperFin), probably with a few architectural improvements for higher clock-speeds.

Yesterday SK Hynix reported its Q1 2023 results and to say that they were abysmal is being kind, as the company reported a 3.4 trillion won operating loss, or just over US$2.5 billion. That's no small hit to take for any company, especially when it's only the performance for a single quarter. However, SK Hynix is apparently trying to see its situation from a positive perspective and believes that the memory chip market will rebound in the second half of this year. The positive outlook isn't just based on what SK Hynix believes though, as various analysts and securities companies believe in an upswing in the second half of the year.

That said, Micron, one of SK Hynix main competitors, has a more drab outlook for the remainder of 2023 and is expecting a tough year ahead. SK Hynix is expecting production cuts by itself, Micron and Samsung to start to take effect sometime in the second quarter this year, which should see inventory drop to more normal levels for all three companies. SK Hynix is also expecting to see a higher demand for DDR5 DRAM later this year, especially in the mobile and server market space. Finally, SK Hynix is hoping that its customers will buy higher density memory products this year, replacing older, lower density solutions, be that DRAM or NAND flash related. SK Hynix is expecting to launch its Gen 5 10 nm DRAM and 238-layer NAND sometime next year, which the company is also hoping will bring more income to its coffers, but the company still has to make it through the rest of 2023 first.

SK hynix Inc. announced today that it has developed the world's fastest mobile DRAM 'LPDDR5T (Low Power Double Data Rate 5 Turbo)' and provided sample products to customers. The new product, LPDDR5T, operates at a data rate of 9.6 gigabits per second (Gbps), 13% faster than the previous generation LPDDR5X unveiled in November 2022. To highlight the maximum speed the product features, SK hynix added 'Turbo' at the end of the standard name LPDDR5.

LPDDR5T, which operates in the ultra-low voltage range of 1.01 to 1.12 V set by the JEDEC (Joint Electron Device Engineering Council), is a product that not only features utmost speed but ultra-low power consumption. "The company pushed the technology to new limits in just two months after LPDDR5X, mobile DRAM with 8.5 Gbps specification, was introduced to the market in November 2022," SK hynix said. "We will solidify our leadership in the mobile DRAM market by providing products of various storage capacities that meet customers' needs."

SK hynix Inc. (or "the company", www.skhynix.com) announced today that its DDR5 product for servers using 1anm, the fourth generation of the 10 nm process technology, has been validated on the 4th Gen Intel Xeon Scalable processor (formerly codenamed Sapphire Rapids) for the first time in the industry. "The validation of the 1anm DDR5 compatibility by Intel for its newest processor that supports DDR5 for the first time is monumental," SK hynix said. "We will seek a fast turnaround in the semiconductor memory industry by actively responding to the growing server market through DDR5, which is already in mass production."

The validation of the company's 1anm DDR5 product, which adopts 1anm technology using the EUV lithography process, is for 4th Gen Intel Xeon Scalable processors, Intel's latest server CPU launched on January 10th. The 4th Gen Intel Xeon Scalable processor has been cited as a key to a turnaround in the industry, given that the launch of a next-generation server CPU requires server replacement and thus, results in a rapid increase in demand for high-performance memory chips. Experts predict that DDR5, expected to meet customers' such needs, will soon become the flagship product in the server DRAM market.

AMD, in its technical presentation for the new Radeon RX 7900 series "Navi 31" GPU, gave us an elaborate explanation on why it had to take the chiplets route for high-end GPUs, devices that are far more complex than CPUs. The company also enlightened us on what sets chiplet-based packages apart from classic multi-chip modules (MCMs). An MCM is a package that consists of multiple independent devices sharing a fiberglass substrate.

An example of an MCM would be a mobile Intel Core processor, in which the CPU die and the PCH die share a substrate. Here, the CPU and the PCH are independent pieces of silicon that can otherwise exist on their own packages (as they do on the desktop platform), but have been paired together on a single substrate to minimize PCB footprint, which is precious on a mobile platform. A chiplet-based device is one where a substrate is made up of multiple dies that cannot otherwise independently exist on their own packages without an impact on inter-die bandwidth or latency. They are essentially what should have been components on a monolithic die, but disintegrated into separate dies built on different semiconductor foundry nodes, with a purely cost-driven motive.

Samsung Electronics Co., Ltd., a world leader in advanced semiconductor technology, today showcased a series of cutting-edge semiconductor solutions set to drive digital transformation through the decade, at Samsung Tech Day 2022. An annual conference since 2017, the event returned to in-person attendance at the Signia by Hilton San Jose hotel after three years.

This year's event, attended by more than 800 customers and partners, featured presentations from Samsung's Memory and System LSI business leaders—including Jung-bae Lee, President and Head of Memory Business; Yong-In Park, President and Head of System LSI Business; and Jaeheon Jeong, Executive Vice President and Head of Device Solutions (DS) Americas Office—on the company's latest advancements and its vision for the future.

Andreas Schilling with Hardwareluxx.de, as part of the Intel Tech Tour Israel, got to hold a 12-inch wafer full of "Raptor Lake-S" dies. These are dies in their full 8P+16E configuration. The die is estimated to measure 257 mm² in area. We count 231 full dies on this wafer. Intel is building "Raptor Lake" on the same 10 nm Enhanced SuperFin (aka Intel 7) node as "Alder Lake." The die is about 23% larger than "Alder Lake" on account of two additional E-core clusters, possibly larger P-cores, and larger L2 caches for both the P-core and E-core clusters. "Raptor Lake" gains significance as it will be the last client processor from Intel to be built on a monolithic die of a uniform silicon fabrication node. Future generations are expected to take the chiplets route, realizing the company's IDM 2.0 product development strategy.

According to an investigative report by "Chips and Cheese," the larger L2 caches in Intel's 13th Gen Core "Raptor Lake-S" doesn't come with a proportionate increase in cache latency, and Intel seems to have contained the latency increase well. "Raptor Lake-S" significantly increases L2 cache sizes over the previous generation. Each of its 8 "Raptor Cove" P-cores has 2 MB of dedicated L2 cache, compared to the 1.25 MB with the "Golden Cove" P-cores powering the current-gen "Alder Lake-S," which amounts to a 60 percent increase in size. The "Gracemont" E-core clusters (group of four E-cores), sees a doubling in the size of the L2 cache that's shared among the four cores in the cluster, from 2 MB in "Alder Lake," to 4 MB. The last-level L3 cache shared among all P-cores and E-core clusters, sees a less remarkable increase in size, from 30 MB to 36 MB.

Larger caches have a direct impact on performance, as more data is available close to the CPU cores, sparing them a lengthy fetch/store operation to the main memory (RAM). However, making caches larger doesn't just cost die-area, transistor-count, and power/heat, but also latency, even though L2 cache is an order of magnitude faster than the L3 cache, which in turn is significantly faster than DRAM. Chips and Cheese tracked and tabulated the L2 cache latencies of past Intel client microarchitectures, and found a generational increase in latencies with increasing L2 cache sizes, leading up to "Alder Lake." This increase has somehow tapered with "Raptor Lake."

An Intel Core "Raptor Lake" engineering sample was de-lidded by Expreview giving us a first look at what will be Intel's last monolithic silicon client processor before the company switches over to chiplets, with its next-generation "Meteor Lake." The chip de-lidded here is the i9-13900, which maxes out the "Raptor Lake-S" die, in featuring all 8 "Raptor Cove" P-cores and 16 "Gracemont" E-cores physically present on the die, along with 36 MB of shared L3 cache, and an iGPU based on the Xe-LP graphics architecture.

The "Raptor Lake-S" silicon is built on the same Intel 7 (10 nm Enhanced SuperFin) silicon fabrication node as "Alder Lake-S." The "Raptor Lake-S" (8P+16E) die measures 23.8 mm x 10.8 mm, or 257 mm² in area, which is 49 mm² more than that of the "Alder Lake-S" (8P+8E) die (around 209 mm²). The larger die area comes from not just the two additional E-core clusters, but also larger L2 caches for the E-core clusters (4 MB vs. 2 MB), and larger L2 caches for the P-cores (2 MB vs. 1.25 MB); besides the larger shared L3 cache (36 MB vs. 30 MB). The "Raptor Cove" P-core itself could be slightly larger than its "Golden Cove" predecessor.

An engineering sample of a 13th Intel Core "Raptor Lake" Core i9 processor hit the web, courtesy of wxnod on Twitter, which confirms its 8P+16E core-configuration in a CPU-Z screenshot. Based on the same LGA1700 package as "Alder Lake," and backwards compatible with Intel 600-series chipset motherboards, besides new 700-series ones, "Raptor Lake" combines eight "Raptor Cove" performance cores (P-cores), with sixteen "Gracemont" efficiency cores (E-cores).

"Raptor Cove" features a generational IPC increase over the "Golden Cove" P-cores powering "Alder Lake," while the "Gracemont" E-cores, although identical to those on "Alder Lake," are expected to benefit from the doubling in L2 cache per cluster, from 2 MB to 4 MB. The ISA as detected by CPU-Z appears to be identical to that of "Alder Lake." The processor is a monolithic silicon chip built on the Intel 7 (10 nm Enhanced SuperFin) silicon fabrication process.

Nanya Technology, part of the Formosa Plastics Group, which is one of the largest conglomerates in Taiwan, will hold a ground-breaking ceremony for its new 12-inch fab that will be built in New Taipei City later this week. It'll be the biggest investment Nanya has done in the past decade, as the company is investing US$10.1 billion into building the new fab. This is obviously a lot less than TSMC is investing, but DRAM is made on different nodes to those that TSMC makes its customers products on, since DRAM doesn't benefit as much from node shrinking as other types of semiconductors.

The new fab will be located near one of Nanya's current fabs, in the Taishan district. Mass production is scheduled to start some time in 2025 and the fab is said to have a monthly capacity of around 45,000 wafers. Right now it's scheduled for a 10 nm technology node, but this might change by the time that the fab is up and running, especially considering that Nanya is already producing a range of 10 nm based products in some of its current fabs. Nanya's goal is to develop its next generation of 10 nm DRAM independently from other DRAM makers, as to avoid having to pay patent licence fees to its competitors.