Today, in the latest GeekBench 5 submission by ASUS, we have discovered something rather interesting. Intel's Ice Lake-SP processors were rumored to arrive with up to 28 cores and 56 threads at maximum, on a single chip. That was due to the 10 nm process used to make these chips, with suspicions that the yield of the node was not good enough to make any higher core count parts. Thanks to the GB5 listing, discovered by Leakbench on Twitter, the Intel Ice Lake-SP CPU engineering sample appeared with an amazing 36 cores with 72 threads. This is supposedly Intel's efforts to try and match the 64 cores and 128 threads of AMD's EPYC "Rome" CPUs, which are winning many server applications due to their performance.

The 36C/72T chip was paired with another similar chip in a 2P dual-socket configuration, which made the total core count rise to 72 cores and 144 threads, running inside of Asustek's Y4R-A1-ASUS-G1 server. The system was reporting a clock frequency of 3.6 GHz base speed, which means that the possible boost clocks could be higher. The CPU features a 1.25 MB level two (L2) cache per core (45 MB in total) and 54 MB of unified level three (L3) cache. That makes this CPU core quite an improvement over the past Cooper Lake generation. We are waiting for more information about these CPUs, and we are going to report on it in the coming time.

Intel has launched its Tiger Lake-U lineup of products back in September, with the availability of the first products in October. The launched lineup was part of the "U" variant of ultra-portable devices that stretched only to four core, eight threaded configurations. However, given that the new competitor in mobile space, AMD, has a wide portfolio of offerings that are coming with up to 8C/16T variants, Intel needs a proper response to that. Despite having a better single-threaded performance, the multi-threaded capability of the Ryzen 4000 series is delivering better performance. Thanks to the popular hardware leaker, TUM APISAK, we have the first appearance of Intel's 11th generation Tiger Lake-H processor.

Appearing in Userbenchmark, the processor was tested on a platform codenamed "Insyde TigerLake". The processor was spotted running 8 cores and 16 threads, at the average frequency of 2.75 GHz. This is only an engineering sample, meaning that these clocks do not represent the final frequencies of the processor. As a reminder, Intel's Tiger Lake CPU is a Willow Cove based design manufactured on Intel's 10 nm SuperFin silicon node. We are yet to see the capabilities of the new node and how the chip performs once the reviews arrive.

Intel has just recently announced its next-generation Rocket Lake-S processor specifications designed to bring improved performance and newer platform technologies like PCIe 4.0. However, we are yet to see the first 10 nm CPU for desktop users. Today, thanks to the sources over at VideoCardz, we have the first look at Intel's next-next-generation processor called Alder Lake. The Alder Lake-S is a platform that brings many of the "firsts" for Intel. It will be the first architecture being built on the company's 10 nm SuperFin architecture. Alongside the new node, the platform will transition to the next-generation of technologies. Rumored are the transitions to PCIe 5.0 and perhaps, most importantly - DDR5.

Another new approach will be Intel's adaptation of Arm's big.LITTLE heterogeneous core structure. The processor will feature a few of the "little" cores for light tasks, and fire up the "big" cores for heavy computing. All of that will require a new socket to house the processor, which is the LGA1700. You can see the new processor below, compared to LGA1200 CPU from the previous generation.

Intel today launched its Iris Xe MAX discrete graphics processor for thin-and-light notebooks powered by 11th Gen Core "Tiger Lake" processors. Dell, Acer, and ASUS are launch partners, debuting the chip on their Inspiron 15 7000, Swift 3x, and VivoBook TP470, respectively. The Iris Xe MAX is based on the Xe LP graphics architecture, targeted at compact scale implementations of the Xe SIMD for mainstream consumer graphics. Its most interesting feature is Intel DeepLink, and a powerful media acceleration engine that includes hardware encode acceleration for popular video formats, including HEVC, which should make the Iris Xe MAX a formidable video content production solution on the move.

The Iris Xe MAX is a fully discrete GPU built on Intel's 10 nm SuperFin silicon fabrication process. It features an LPDDR4X dedicated memory interface with 4 GB of memory at 68 GB/s of bandwidth, and uses PCI-Express 4.0 x4 to talk to the processor, but those are just the physical layers. On top of these are what Intel calls Deep Link, an all encompassing hardware abstraction layer that not only enables explicit multi-GPU with the Xe LP iGPU of "Tiger Lake" processors, but also certain implicit multi-GPU functions such as fine-grained division of labor between the dGPU and iGPU to ensure that the right kind of workload is split between the two. Intel referred to this as GameDev Boost, and we detailed it in an older article.

Intel's chief architect and senior vice president of discrete graphics division, Mr. Raja Koduri, is said to be scheduled to present at Samsung Electronics Event day. With a presentation titled "1000X More Compute for AI by 2025", the event is called Samsung Foundry SAFE Forum. It is a global virtual conference designed to be available to everyone. So you might be wondering what is Mr. Koduri doing there. Unless you have been living under a rock, you know about Intel's struggles with node manufacturing. Specifically, the 10 nm node delays that show the company's efforts to deliver a node on time. The same is happening with the 7 nm node that also experienced significant delays.

Intel has a contract to develop an exascale supercomputer at Argonne National Laboratory, called Aurora. That supercomputer is using Intel's CPUs and the company's upcoming Xe GPUs. Since the company has problems with manufacturing and has to deliver the products (it is bound by several contracts) to its contractors and customers, it decided to look at external manufacturers for its products, specifically Xe graphics. Being that Mr. Koduri tweeted an image of him visiting Samsung Giheung Fab in Korea, and now presenting at the Samsung Foundry event, it is possible that Intel will tap Samsung's semiconductor manufacturing process for its Xe GPU efforts and that Samsung will be the contractor in charge.

Intel's next-generation Pentium Gold and Celeron entry-level processors based on the "Tiger Lake" microarchitecture could finally receive the AVX2 instruction set. Intel had segmented AVX and AVX2 to be exclusive to the Core and Xeon brands, with the Pentium Gold and Celeron products based on the same microarchitectures to artificially lack these instructions.

Intel updated its ARK product information database with entries for "Tiger Lake" based Pentium Gold and Celeron products. The page for the Pentium Gold 7505 and Celeron 6305, mention support for AVX2 besides SSE4. Both are mobile chips with 15 W TDP, and are built on the same 10 nm SuperFin process as the rest of the 11th Gen Core "Tiger Lake" processor family.

Intel has been preparing the launch of its 10 nm processors for desktop users for some time now, and today we are getting the first pictures of the Alder Lake-S CPU backside. Featuring a package with a size of 37.5×45 mm, the Alder Lake CPU uses more of its area for a pin count increase. Going up from 1200 pins in the LGA1200 socket, the new Alder Lake-S CPU uses 1700 CPU pins, which slots in the LGA1700 socket. In the picture below, there is an engineering sample of the Alder Lake-S CPU, which we see for the first time. While there is no much information about the processor, we know that it will use Intel's 10 nm SuperFin design, paired with hybrid core technology. That means that there will be big (Golden Cove) and little (Gracemont) cores in the design. Other features such as PCIe 5.0 and DDR5 should be present as well. The new CPU generation and LGA1700 motherboards are scheduled to arrive in second half of 2021.

Intel has finally sounded the "full steam ahead" whistle for its Fab 42, set in Arizona. Fab 42 has a storied past to it, as Intel started its construction back in 2011. It was actually finished by 2013, and by 2014 all essential infrastructure for semiconductor fabrication was there - except for the fabrication equipment itself. You see, Intel aimed for this factory to produce 450 mm wafers (instead of the industry standard 300 mm) in the 14 nm process. However, back in 2014, Intel wasn't sure about demand for its 14 nm products - and the company was actually planning to debut 10 nm back in 2016, so it sort of made sense. Of course, then came the 10 nm delays, the 14 nm supply issues, and backporting of certain products to other less cutting-edge processes. If only Intel had had a crystal ball.

TSMC, one of the biggest silicon manufacturers in the world, usually doesn't disclose company pricing of the silicon it manufactures and only shares that with its customers. It appears that RetiredEngineer (@chiakokhua on Twitter) got a hold of the pricing of TSMCs wafers on every manufacturing node starting from 90 nm down to 5 nm. That includes a wide portfolio of 65, 40, 28, 20, 16/12, 10, and 7 nm nodes as well. The table shown below includes information dating to April 2020, so it is possible that some things are now different and they surely are. There are a few quite interesting notes from the image, namely the price increase as the node shrinks.

From 90 nm to 20 nm, the price of the wafer didn't increase as much, however, starting from 16/12 nm node(s), TSMC has seen costs per wafer, and other costs increase exponentially. For example, just compare the 10 nm wafer price of $5992 with the price of a 5 nm wafer which costs an amazing $16988. This is more than a 180% price increase in just three years, however, the cost per transistor is down as you get around 229% higher density in that period, making TSMC actually in line with Moore's Law. That is comparing Transistor density (MTr / mm²) of52.51 million transistors for the 10 nm node and 173 million transistors per mm² of the 5 nm node .

Intel is giving finishing touches to six new Pentium Silver and Celeron "Jasper Lake" entry-level processors. Built on the 10 nm silicon fabrication process, these processors leverage the "Tremont" CPU cores, or the "small" x86-64 cores Intel is deploying on its "Lakefield" Core Hybrid processors. The chips also feature a low-power trim of the company's Gen11 iGPU (same graphics architecture found in "Ice Lake-U" and "Lakefield" processors). The desktop SKUs consist of three parts with TDP rated at 10 W, while the three other mobile SKUs offer 6 W TDP.

The desktop lineup is led by the Pentium Silver J6005, a 4-core/4-thread part with 2.00 GHz clock speeds, up to 3.00 GHz "maximum quad-core burst speed," and 4 MB L2 cache. The Celeron J5105 is next in line, with 2.00 GHz clocks, 2.80 GHz burst speeds, a slightly slower iGPU, and 4 MB L2 cache. At the bottom end of the desktop lineup is the Celeron J4505, a 2-core/2-thread part clocked at 2.00 GHz with 2.90 GHz burst, and 4 MB L2 cache. The mobile lineup is led by the Pentium Silver N6000, a 4-core/4-thread part with 1.10 GHz clocks, 3.10 GHz burst speeds, and 4 MB L2 cache. The Celeron N5100 is right behind, clocked at 1.10 GHz and 2.80 GHz clocks. At the bottom of the stack is the Celeron N4500, a 2-core/2-thread part with 1.10 GHz base and 2.80 GHz burst.An Intel video presentation on the "Tremont" CPU core architecture follows.

Promotional videos of Intel 11th Gen Core "Tiger Lake" processors leaked to the web courtesy h0x0d on Twitter. It confirms the new corporate identity of Intel, along with its new logo artistic language. It also confirms the new EVO Powered by Core brand extension, along with a separate case badge for notebooks that use Iris Xe discrete graphics (DG1) in addition to the Xe Gen12 iGPU of "Tiger Lake." Intel has a technology that can get the Xe LP iGPU and dGPU to work in tandem. VideoCardz compiled some interesting frames from the promotional videos, revealing bits such as clock speeds of up to 4.80 GHz (boost), 3.11 GHz (base), the first "Tiger Lake" parts being 4-core/8-thread, the new 10 nm SuperFin transistor, wafer- and die shots of "Tiger Lake" 4c+96EU die, and unless we're mistaken, pictures of a "Tiger Lake" package that uses a DRAM (HBM?) stack on-package, using EMIB. h0x0d also posted videos of the Lenovo Yoga 9i and HP Spectre notebooks based on "Tiger Lake."

Here's is the first schematic of Intel's upcoming "Whitley" enterprise platform for the upcoming Xeon Scalable "Ice Lake-SP" processors, courtesy momomo_us. The platform sees the introduction of the new LGA4189 socket necessitated by Intel increasing the memory channels per socket to 8, compared to 6 of the current-gen "Cascade Lake-SP." The new platform also sees the introduction of PCI-Express gen 4.0 bus, with each socket putting out up to 64 PCI-Express gen 4.0 CPU-attached lanes. This are typically wired out as three x16 slots, two x8 slots, an x4 chipset bus, and a CPU-attached 10 GbE controller.

The processor supports up to 8 memory channels running at DDR4-3200 with ECC. The other key component of the platform is the Intel C621A PCH. The C621A talks to the "Ice Lake-SP" processor over a PCI-Express 3.0 x4 link, and appears to retain gen 3.0 fabric from the older generation C621. momomo_us also revealed that the 10 nm "Ice Lake-SP" processor could have TDP of up to 270 W.

Intel in the opening presentation of the Hot Chips 32 virtual conference detailed its next-generation Xeon Scalable "Ice Lake-SP" enterprise processor. Built on the company's 10 nm silicon fabrication process, "Ice Lake-SP" sees the first non-client and non-mobile deployment of the company's new "Sunny Cove" CPU core that introduces higher IPC than the "Skylake" core that's been powering Intel microarchitectures since 2015. While the "Sunny Cove" core itself is largely unchanged from its implementation in 10th Gen Core "Ice Lake-U" mobile processors, it conforms to the cache hierarchy and tile silicon topology of Intel's enterprise chips.

The "Ice Lake-SP" die Intel talked about in its Hot Chips 32 presentation had 28 cores. The "Sunny Cove" CPU core is configured with the same 48 KB L1D cache as its client-segment implementation, but a much larger 1280 KB (1.25 MB) dedicated L2 cache. The core also receives a second fused multiply/add (FMA-512) unit, which the client-segment implementation lacks. It also receives a handful new instruction sets exclusive to the enterprise segment, including AVX-512 VPMADD52, Vector-AES, Vector Carry-less Multiply, GFNI, SHA-NI, Vector POPCNT, Bit Shuffle, and Vector BMI. In one of the slides, Intel also detailed the performance uplifts from the new instructions compared to "Cascade Lake-SP".

A lot is riding for Intel on its 11th Gen Core "Tiger Lake" system-on-chip (SoC), which will launch exclusively on mobile platforms, hoping to dominate the 7 W thru 15 W ultraportable form-factors in 2020, while eventually scaling up to the 25 W thru 45 W H-segment form-factors in 2021, with a variant that is rumored to double core-counts. The chip is built on Intel's new 10 nm SuperFin silicon fabrication node that enables a double digit percentage energy efficiency growth over 10 nm, allowing Intel to significantly dial up clock speeds without impacting the power envelope. The CPU and iGPU make up the two key components of the "Tiger Lake" SoC.

The CPU component on the "Tiger Lake" processors that launch in a few weeks from now features four "Willow Cove" CPU cores. Coupled with HyperThreading, this ends up being a 4-core/8-thread setup, although much of Intel's innovation is in giving these cores significant IPC increases over the "Skylake" core powering "Comet Lake" processors, and compared to the "Sunny Cove" cores powering "Ice Lake" a minor IPC (although major net performance increase from clock speeds). The "Willow Cove" CPU core appears to be a derivative of the "Sunny Cove" core, designed to take advantage of the 10 nm SuperFin node, along with three key innovations.

Intel on Thursday made several technological disclosures about its latest silicon fabrication process, the 10 nm SuperFin. With this, the company is changing the nomenclature of its node refinements, away from the ## nm++ naming scheme (with each "+" denoting a refinement, or internode), to a more descriptive naming scheme. The new 10 nm SuperFin node is the first refinement of the company's 10 nm node that debuted with the company's 10th Gen Core "Ice Lake" processors last year, and promises energy efficiency in the ballpark of 7 nm-class nodes by competitors TSMC and Samsung. While past generations of internodes (refinements) delivered energy efficiency improvements of around 3-5%, 10 nm SuperFin offers the kind of improvements expected from a brand new node, according to Intel.

The 10 nm SuperFin node is composed of two key innovations, the SuperMIM capacitor and a redesigned FinFET transistor. The new SuperMIM (metal insulator metal) capacitor offers a 5x increase in capacitance compared to devices in this class. The redesigned FinFET introduces a new barrier that reduces via resistance by 30%. Combined, the 10 nm SuperFin node affords chips a V/F curve comparable to a die-shrink to a whole new silicon fabrication node, without any change in transistor density. The first product built on 10 nm SuperFin is the upcoming Core "Tiger Lake" processor addressing the client-segment. The company is already working on enhancements of this node relevant for data-center processors.

At Intel, we truly believe in the potential of technology to enrich lives and change the world. This has been a guiding principle since the company was founded. It started with the PC era, when technology enabled the mass digitization of knowledge and networking, bringing 1 billion people onto the internet. Then came the mobile and cloud era, a disruption that changed the way we live. We now have over 10 billion devices connected to supercomputers in the cloud.

We believe the next era will be the intelligent era. An era where we will experience 100 billion intelligent connected devices. Exascale performance and architecture will make this intelligence available to all, enriching our lives in more ways than we can imagine today. This is a future that inspires and motivates me and my fellow Intel architects every day.

Database spelunker TUM_APISAK has brought to the surface another revealing entry regarding Intel's upcoming Tiger Lake CPUs. Discovered in SiSoftware's database entries, the Intel Core i3-1115G4 has reared its head sporting a mightily impressive base core clock set at 3.0 GHz. Compare this to the Ice Lake-based Core i3-1005G1, which while making use of the 10 nm process itself, only managed to run on a 1.2 GHz base clock. This increase speaks to Intel's refinement of the 10 nm manufacturing process (even sporting its well-known woes) and the usage of the new Willow Cove architecture core that will power the i3-1115G4.

Whilst still being a 2-core, 4-thread processor (ehrm), the new i3-1115G4 based on Tiger Lake sports a number of improvements on both its CPU and GPU core design. The new architectural improvements baked into Willow Cove are aided by an L3 cache boost from 4 MB to 6 MB, and its GPU is expected to make use of Intel's Xe graphics, featuring 96 EUs (compared to the 64 EUs in Ice Lake's 12th Gen graphics). It remains to be seen exactly how competitive Tiger Lake will be compared to AMD's current (and future) Ryzen offerings, but these are some encouraging leaks.

Intel is preparing to launch an 8-core mobile processor based on its 10 nm "Tiger Lake" microarchitecture, according to a corporate memo by leading notebook OEM Compal, which serves major notebook brands such as Acer. The memo was drafted in May, but unearthed by momomo_us. Compal expects Intel to launch the 8-core "Tiger Lake-H" processor in Q1 2021. This is big, as it would be the first large 10 nm client-segment silicon that goes beyond 4 cores. The company's first 10 nm client silicon, "Ice Lake," as well as the "Tiger Lake-U" silicon that's right around the corner, feature up to 4 cores. As an H-segment part, the new 8-core processor could target TDPs in the range of 35-45 W, and notebooks in the "conventional thickness" form-factor, as well as premium gaming notebooks and mobile workstations.

The 8-core "Tiger Lake-H" silicon is the first real sign of Intel's 10 nm yields improving. Up until now, Intel confined 10 nm to the U- and Y-segments (15 W and below), addressing only ultra-portable form-factors. Even here, Intel launched U-segment 14 nm "Comet Lake" parts at competitive prices, to take the market demand off "Ice Lake-U." The H-segment has been exclusively held by "Comet Lake-H." Intel is planning to launch "Ice Lake-SP" Xeon processors later this year, but like all server parts, these are high-margin + low-volume parts. Compal says Intel will refresh the H-segment with a newer 8-core "Comet Lake-H" part in the second half of 2020, possibly to bolster the high-end against the likes of AMD's Ryzen 9 4900H. Later in 2021, Intel is expected to introduce its 10 nm "Alder Lake" processor, including a mobile variant. These processors will feature Hybrid technology, combining "Golden Cove" big CPU cores with "Gracemont" small ones.

Intel is preparing to launch its next-generation for server processors and the next in line is the Ice Lake-SP 10 nm CPU. Featuring a Golden Cove CPU and up to 28 cores, the CPU is set to bring big improvements over the past generation of server products called Cascade Lake. Today, thanks to the sharp eye of TUM_APISAK, we have a new benchmark of the Ice Lake-SP platform, which is compared to AMD's EPYC Rome offerings. In the latest GeekBench 4 score, appeared an engineering sample of unknown Ice Lake-SP model with 28 cores, 56 threads, a base frequency of 1.5 GHz, and a boost of 3.19 GHz.

This model was put in a dual-socket configuration that ends up at a total of 56 core and 112 threads, against a single 64 core AMD EPYC 7442 Rome CPU. The dual-socket Intel configuration scored 3424 points in the single-threaded test, where AMD configuration scored notably higher 4398 points. The lower score on Intel's part is possibly due to lower clocks, which should improve in the final product, as this is only an engineering sample. When it comes to the multi-threaded test, Intel configuration scored 38079 points, where the AMD EPYC system did worse and scored 35492 points. The reason for this higher result is unknown, however, it shows that Ice Lake-SP has some potential.

Intel is struggling with its node development and it looks like next-generation consumer systems are going to be stuck on 14 nm for a bit more. Preparing for that, Intel will finally break free from Skylake-based architectures and launch something new. The replacement for the current Comet Lake generation is set to be called Rocket Lake and today we have obtained some more information about it. Thanks to popular hardware leaker rogame (_rogame), we know a few stuff about Rocket Lake. Starting off, it is known that Rocket Lake features the backport of 10 nm Willow Cove core, called Cypress Cove. That Cypress Cove is supposed to bring only 10% IPC improvements, according to the latest rumors.

With 10% IPC improvement the company will at least offer some more competitive product than it currently does, however, that should be much slower than 10 nm Tiger Lake processors which feature the original Willow Cove design. It shows that backporting of the design doesn't just bring loses of the node benefits like smaller design and less heat, but rather means that only a fraction of the performance can be extracted. Another point that rogame made is that Rocket Lake will run up to 5 GHz in boost, and it will run hot, which is expected.

Intel's announcement today that their 7 nm node is facing difficulties is being taken one of two ways: as an unmitigated disaster by some, and with a tentative carefulness (lest we see another 10 nm repeat) from others. However one looks at this setback, which means AMD will still enjoy a process lead over Intel for some extra time, this is good news for AMD in more ways than just that one.

Case in point: stock price. While AMD has a much lower market cap than Intel (calculated by multiplying the value of a single stock by the number of total issued stocks), today, for the first time since 2006, AMD's shares were more valuable than Intel's on a per-share basis. AMD's $70 billion market cap still pales in comparison to Intel's $215 billion. At time of writing, AMD's stock pricing is $18 higher than Intel, at $68.67 compared to Intel's $50.79. A first in many years for the green company.

Intel's silicon fabrication woes refuse to torment the company's product roadmaps, with the company disclosing in its Q2-2020 financial results release that the company's first CPUs built on the 7 nanometer silicon fabrication node are delayed by a year due to a further 6-month delay from prior expectations. The company will focus on getting its 10 nm node up to scale in the meantime.

The company mentioned that the 10 nm "Tiger Lake" mobile processor and "Ice Lake-SP" enterprise processor remains on-track for 2020. The company's 12th Generation Core "Alder Lake-S" desktop processors won't arrive before the second half of 2021. In the meantime, Intel will launch its 11th Gen Core "Rocket Lake" processor on the 14 nm node, but with increased IPC from the new "Cypress Cove" CPU cores. Also in 2H-2021, the company will launch its "Sapphire Rapids" enterprise processors that come with next-gen connectivity and updated CPU cores.

Intel Corporation today reported second-quarter 2020 financial results. "It was an excellent quarter, well above our expectations on the continued strong demand for computing performance to support cloud-delivered services, a work- and learn-at-home environment, and the build-out of 5G networks," said Bob Swan, Intel CEO. "In our increasingly digital world, Intel technology is essential to nearly every industry on this planet. We have an incredible opportunity to enrich lives and grow this company with a continued focus on innovation and execution."

Intel achieved record second-quarter revenue with 34 percent data-centric revenue growth and 7 percent PC-centric revenue growth YoY. These results were driven by strong sales of cloud, notebook, memory and 5G products in an environment where digital services and computing performance are essential to how we live, work and stay connected.

As we approach the launch of the Intel's Ice Lake-SP Xeon processors, which will be the company's first 10 nm product for servers, we find more details on the ways CPU operates and today's discovery is an interesting one. In the latest patch submitted to Linux kernel by Intel's engineers, we find out that Intel Ice Lake Xeons have a slower frequency ramp up, meaning that there could be some latency added. However, the engineers have patched this and it should perform as expected. The patch is described as the following: "On ICX platform, the CPU frequency will slowly ramp up when woken up from C-states deeper than/equals to C1E. Although this feature does save energy in many cases this might also cause unexpected result. For example, workload might get unstable performance due to the uncertainty of CPU frequency. Besides, the CPU frequency might not be locked to specific level when the CPU utilization is low."

Intel's upcoming Core i7-1165G7 4-core/8-thread processor based on the 10 nm "Tiger Lake-U" silicon packs a mean punch in comparison to the AMD Ryzen 7 4700U processor, despite half the number of CPU cores. A Geekbench comparison between two Lenovo laptops, one powered by an i7-1165G7, and the other by a 4700U, shows a staggering 36.8% performance lead for the Intel chip in single-threaded performance, while also being 0.5% faster in multi-threaded performance. The i7-1165G7 features a 4-core/8-thread CPU with "Willow Cove" cores, while the 4700U lacks SMT, and is an 8-core/8-thread chip with "Zen 2" CPU cores. The game changes with the Ryzen 7 4800U, where the 8-core/16-thread chip ends up 22.3% faster than the Core i7-1165G7 in the multi-threaded test owing to SMT, while Intel's single-threaded performance lead is lowered to 29.3%.