Intel's next-generation Arc "Battlemage" GPU is expected to numerically-double its shader counts, according to a report by RedGamingTech. The largest GPU from the Arc "Battlemage" series, the "BMG-G10," aims to power SKUs that compete in the performance segment. The chip is expected to be built on a TSMC 4 nm-class EUV node, similar to NVIDIA's GeForce "Ada" GPUs, and have a die-size similar to that of the "AD103" silicon powering the GeForce RTX 4080.

Among the juiciest bits from this report are that the top "Battlemage" chip will see its Xe Core count doubled to 64, up from 32 on the top "Alchemist" part. This would see its execution unit (EU) count doubled to 1,024, and unified shader counts at 8,192. Intel is expected to give the chip clock speeds in excess of 3.00 GHz. The Xe Cores themselves could see several updates, including IPC uplifts, and support for new math formats. The memory sub-system is expected to see an overhaul, with a large 48 MB on-die L2 cache. While the memory bus is unchanged at 256-bit wide, the memory speed could see a significant increase up from the 16-17.5 Gbps on the Arc A770. As for when customers can actually expect products, the RedGamingTech report puts launch of the Arc "Battlemage" series at no sooner than Q2-2024. The company is expected to launch refreshed "Alchemist+" GPUs in 2023.

Business Korea got the scoop on Samsung hiring an ex TSMC executive by the name of Lin Jun-Cheng, who was with TSMC for almost 19 years. His role at Samsung will be as VP of Samsung's advanced packaging business, something he should be more than familiar with, as during his time at TSMC, he was part of no less than 450 patents involving chip packaging. Lin has also worked for Micron and more recently for a company called Skytech, that specialises in advanced IC packaging equipment.

Samsung has relied on third parties when it comes to more advanced chip packaging and has been behind Intel and TSMC in this area. The Business Korea article mentions that Samsung has been spending a lot of resources over the past year to build its own advanced packaging business, including hiring industry experts. Samsung has hired ex Apple, Intel and Qualcomm staff to join or head various teams related to its foundry division, not only for packaging, but also experts in various lithography processes, such as EUV. Samsung is clearly taking its foundry business seriously, even though they have had their fair share of issues with various customers over the past few years.

Intel Foundry Services, the in-house semiconductor foundry of Intel, announced that its 2 nm-class Intel 20A and 1.8 nm-class Intel 18A foundry nodes have completed development, and are on course for mass-producing chips on their roadmap dates. Chips are expected to begin mass-production on the Intel 20A node in the first half of 2024, while those on the Intel 18A node are expected to begin in the second half of 2024. The completion of the development phase means that Intel has finalized the specifications and performance/power targets of the nodes, the tools and software required to make the chips, and can now begin ordering them to build the nodes. Intel has been testing these nodes through 2022, and with the specs being finalized, chip-designers can accordingly wrap up development of their products to align with what these nodes have to offer.

Intel 20A (or 20-angstrom, or 2 nm) node introduces gates-all-around (GAA) RibbonFET transistors with PowerVIAs (an interconnect innovation that contributes to transistor densities). The Intel 20A node is claimed to offer a 15% performance/Watt gain over its predecessor, the Intel 3 node (FinFET EUV, 3 nm-class), which by itself offers an 18% performance/Watt gain over Intel 4 (20% perf/Watt gain over the current Intel 7 node), the node that is entering mass-production very soon. The Intel 18A node is a further refinement of Intel 20A, and introduces a design improvement to the RibbonFET that increases transistor density at scale, and a claimed 10% performance/Watt improvement over Intel 20A.

Although DRAM is using much less refined production processes compared to the latest processors and GPUs, all the major manufacturers are continuing to shrink their manufacturing nodes step by step. Part of the reason for this, is that a node shrink doesn't have the same improvements for DRAM as it does for most types of field-effect transistors or FETs, which are mostly used for making processor logic of some kind. SK Hynix is now said to have entered the partner verification process of its 5th gen 1β DRAM, to make sure its latest 1x nm DRAM is compatible with major applications. In SK Hynix's case this should roughly translate to a 12 nm process node.

According to Chosun Media in Korea, Intel will take part in this verification, with Intel having finished verification of SK Hynix's 4th gen 1α DRAM for its 4th gen Xeon Scalable processor. Initially, SK Hynix's 5th gen 1β DRAM will be targeting server applications, so it's likely it will be tested for compatibility with the same platforms from Intel, among others. The new 1β DRAM is said to increase efficiency by more than 40 percent, although the publication didn't mention if this is power efficiency or something else. The 1β DRAM from SK Hynix, as well as Samsung—who announced its 1β DRAM in December 2022—are made using an EUV lithography process and the two Korean DRAM makers are the only two makers of DRAM that are using EUV so far.

Samsung Electronics today reported financial results for the fourth quarter and the fiscal year 2022. The Company posted KRW 70.46 trillion in consolidated revenue and KRW 4.31 trillion in operating profit in the quarter ended December 31, 2022. For the full year, it reported 302.23 trillion in annual revenue, a record high and KRW 43.38 trillion in operating profit.

The business environment deteriorated significantly in the fourth quarter due to weak demand amid a global economic slowdown. Earnings at the Memory Business decreased sharply as prices fell and customers continued to adjust inventory. The System LSI Business also saw a decline in earnings as sales of key products were weighed down by inventory adjustments in the industry. The Foundry Business posted a new record for quarterly revenue while profit increased year-on-year on the back of advanced node capacity expansion as well as customer base and application area diversification.

According to Bloomberg, Japan and the Netherlands are getting ready to join the US in limiting access to advanced semiconductor manufacturing equipment for China. The three nations are currently in talks—that might end as soon as today—over how they can impose joint limits on what kind of equipment and tools can be exported to China. Apparently there will be no official announcement if a deal is struck, instead the restrictions will simply be implemented as required.

Bloomberg states that the Netherlands will expand export restrictions that ASML is already under, which according to the publication means stricter export rules around DEUV machines, which are used in cutting edge semiconductor nodes. Japan is said to implement similar export restrictions for Nikon as well as Tokyo Electron, with the US already having implemented restrictions for Applied Materials. The export restriction deal is in part being done to appease US equipment makers, who have complained that their international competitors haven't been under the same export restrictions when it comes to China, as they have. The question is if the export restrictions will hinder China in the long run, or if the nation will simply push ahead and develop its own, competing semiconductor manufacturing tools.

Update Jan 28th: Japan and the Netherlands reached an agreement with the US on Friday and the two countries are said to be making individual announcements with regards to their individual agreements with the US.

Intel's server processor lineup led by the 4th Gen Xeon Scalable "Sapphire Rapids" processors face stiff competition from AMD 4th Gen EPYC "Genoa" processors that offer significantly higher multi-threaded performance per Watt on account of a higher CPU core-count. The gap is only set to widen, as AMD prepares to launch the "Bergamo" processor for cloud data-centers, with core-counts of up to 128-core/256-thread per socket. A technologically-embattled Intel is preparing quick counters as many as three new server microarchitecture launches over the next 23 months, according to Intel, in its Q4-2022 Financial Results presentation.

The 4th Gen Xeon Scalable "Sapphire Rapids," with a core-count of up to 60-core/120-thread, and various application-specific accelerators, witnessed a quiet launch earlier this month, and is shipping to Intel customers. The company says that it will be joined by the Xeon Scalable "Emerald Rapids" architecture in the second half of 2023; followed by "Granite Rapids" and "Sierra Forest" in 2024. Built on the same LGA4677 package as "Sapphire Rapids," the new "Emerald Rapids" MCM packs up to 64 "Raptor Cove" CPU cores, which support higher clock-speeds, higher memory speeds, and introduce the new Intel Trust Domain Extensions (TDX) instruction-set. The processor retains the 8-channel DDR5 memory interface, but with higher native memory speeds. The chip's main serial interface is a PCI-Express Gen 5 root-complex with 80 lanes. The processor will be built on the last foundry-level refinement of the Intel 7 node (10 nm Enhanced SuperFin); many of these refinements were introduced with the company's 13th Gen Core "Raptor Lake" client processors.

Today ASML Holding NV (ASML) has published its 2022 fourth-quarter and full-year results. "Our fourth-quarter net sales came in around the midpoint of our guidance at €6.4 billion. The gross margin of 51.5% was above our guidance due to additional upgrades and insurance settlement for last year's ASML Berlin fire. "For ASML, 2022 was another strong year ending with total net sales for the year of €21.2 billion, gross margin of 50.5% and a record backlog at the end of 2022 of €40.4 billion.

"We continue to see uncertainty in the market caused by inflation, rising interest rates, risk of recession and geopolitical developments related to export controls. However, our customers indicate that they expect the market to rebound in the second half of the year. Considering our order lead times and the strategic nature of lithography investments, demand for our systems therefore remains strong.

The online datasheets of some of the first AMD Ryzen 7040 series "Phoenix Point" mobile processors went live, detailing the processor's I/O feature-set. We learn that AMD has decided to give PCI-Express Gen 5 a skip with this silicon, at least in its mobile avatar. The Ryzen 7040 SoC puts out a total of 20 PCI-Express Gen 4 lanes, all of which are "usable" (i.e. don't count 4 lanes toward chipset-bus). This would mean that the silicon has a full PCI-Express 4.0 x16 interface for discrete graphics, and a PCI-Express 4.0 x4 link for a CPU-attached M.2 NVMe slot; unlike the "Raphael" desktop MCM and the "Dragon Range" mobile MCM, whose client I/O dies put out a total of 28 Gen 5 lanes (24 usable, with x16 PEG + two x4 toward CPU-attached M.2 slots).

Another interesting aspect about "Phoenix Point" is its memory controllers. The SoC features a dual-channel (four sub-channel) DDR5 memory interface, besides support for LPDDR5 and LPDDR5x. DDR5-5600 and LPDDR5-7600 are the native speeds supported. What's really interesting is the maximum amount of memory supported, which stands at 256 GB—double that of "Raphael" and "Dragon Range," which top out at 128 GB. This bodes well for the eventual Socket AM5 APUs AMD will design based on the "Phoenix Point" silicon. Older Ryzen 5000G "Cezanne" desktop APUs are known for superior memory overclocking capabilities to 5000X "Vermeer," with the monolithic nature of the silicon favoring latencies. Something similar could be expected from "Phoenix Point."

According to Reuters, Samsung is gearing up to increase the chip production capacity at its P3 factory in Pyeongtaek in South Korea, despite the fact that there's a general slowdown in the semiconductor industry, in addition to the general economic downturn. Samsung is apparently planning on adding 12-inch wafer capacity for DRAM, while also adding more 4 nm chip capacity. The P3 fab kicked off production of Samsung's most cutting-edge NAND flash chips earlier this year and is the company's largest fab overall. According to Reuters, Samsung is aiming to add at least 10 new EUV machines in 2023.

In related news via The Elec, Samsung has seen costs increase significantly when it comes to materials costs relating to the expansion of the P3 fab. So far, the company has racked up extra costs of over a trillion korean Won, or more than US$786 million, largely due to all of its contractors having raised their prices. The report also mentioned that some parts of the expansion of the P3 fab has been delayed by as much as a year, which isn't good news for Samsung and it likely means that the company will see further increases in costs before the expansions are finished.

Huawei, the Chinese technology giant, has reportedly filed patents that it is developing extreme ultraviolet (EUV) scanners for use in the manufacturing process of semiconductors. This news comes amid increasing tensions between Huawei and the US government, which has imposed a series of sanctions on the company in recent years. According to UDN, Huawei has filed a patent that covers the entire EUV scanner with a 13.5 nm EUV light source, mirrors, lithography for printing circuits, and proper system control. While filing a patent is not the same as creating an accurate EUV scanner, it could enable China to produce a class of chips below 7 nm and have a homegrown semiconductor production, despite the ever-increasing US sanctions.

The development of EUV scanners is a significant milestone for Huawei and the semiconductor industry. However, the company's progress in this area may be hindered by the US government's sanctions, which have limited Huawei's access to certain technologies and markets. It is important to note that Chinese SMIC wanted to develop EUV fabrication based on third-party EUV tools; however, those plans were scrapped as the Wassenaar agreement came into action and prohibited the sales of advanced tools to Chinese companies. Huawei's development could represent a new milestone for the entire Chinese industry.

Samsung Electronics Co., Ltd., the world leader in advanced memory technology, today announced the development of its 16-gigabit (Gb) DDR5 DRAM built using the industry's first 12-nanometer (nm)-class process technology, as well as the completion of product evaluation for compatibility with AMD. "Our 12 nm-range DRAM will be a key enabler in driving market-wide adoption of DDR5 DRAM," said Jooyoung Lee, Executive Vice President of DRAM Product & Technology at Samsung Electronics. "With exceptional performance and power efficiency, we expect our new DRAM to serve as the foundation for more sustainable operations in areas such as next-generation computing, data centers and AI-driven systems."

"Innovation often requires close collaboration with industry partners to push the bounds of technology," said Joe Macri, Senior VP, Corporate Fellow and Client, Compute and Graphics CTO at AMD. "We are thrilled to once again collaborate with Samsung, particularly on introducing DDR5 memory products that are optimized and validated on "Zen" platforms."

AMD, in its technical presentation for the new Radeon RX 7900 series "Navi 31" GPU, gave us an elaborate explanation on why it had to take the chiplets route for high-end GPUs, devices that are far more complex than CPUs. The company also enlightened us on what sets chiplet-based packages apart from classic multi-chip modules (MCMs). An MCM is a package that consists of multiple independent devices sharing a fiberglass substrate.

An example of an MCM would be a mobile Intel Core processor, in which the CPU die and the PCH die share a substrate. Here, the CPU and the PCH are independent pieces of silicon that can otherwise exist on their own packages (as they do on the desktop platform), but have been paired together on a single substrate to minimize PCB footprint, which is precious on a mobile platform. A chiplet-based device is one where a substrate is made up of multiple dies that cannot otherwise independently exist on their own packages without an impact on inter-die bandwidth or latency. They are essentially what should have been components on a monolithic die, but disintegrated into separate dies built on different semiconductor foundry nodes, with a purely cost-driven motive.

An alleged leaked company slide details AMD's upcoming 5 nm "Navi 31" GPU powering the next-generation Radeon RX 7900 XTX and RX 7900 XT graphics cards. The slide details the "Navi 31" MCM, with its central graphics compute die (GCD) chiplet that's built on the 5 nm EUV silicon fabrication process, surrounded by six memory cache dies (MCDs), each built on the 6 nm process. The GCD interfaces with the system over a PCI-Express 4.0 x16 host interface. It features the latest-generation multimedia engine with dual-stream encoders; and the new Radiance display engine with DisplayPort 2.1 and HDMI 2.1a support. Custom interconnects tie it with the six MCDs.

Each MCD has 16 MB of Infinity Cache (L3 cache); and a 64-bit GDDR6 memory interface (two 32-bit GDDR6 paths). Six of these add up to the GPU's 384-bit GDDR6 memory interface. In the scheme of things, the GPU has a contiguous and monolithic 384-bit wide memory bus, because every modern GPU uses multiple on-die memory controllers to achieve a wide memory bus. "Navi 31" hence has a total Infinity Cache size of 96 MB—which may be less in comparison to the 128 MB on "Navi 21," but AMD has shored up cache sizes across the GPU. The L0 caches on the compute units is now increased numerically by 240%. The L1 caches by 300%, and the L2 cache shared among the shader engines, by 50%. The RX 7900 XTX is confirmed to use 20 Gbps GDDR6 memory in this slide, for 960 GB/s of memory bandwidth.

Here's the first picture of the "Navi 31" GPU at the heart of AMD's fastest next-generation graphics cards. Based on the RDNA3 graphics architecture, this will mark an ambitious attempt by AMD to build the first multi-chip module (MCM) client GPU featuring more than one logic die. MCM GPUs aren't new in the enterprise space with Intel's "Ponte Vecchio," but this would be the first such GPU meant for hardcore gaming graphics products. AMD had made MCM GPUs in the past, but those have been packages with just one logic die, surrounded by memory stacks. "Navi 31" is an MCM of as many as eight logic dies, and no memory stacks (no, those aren't HBM stacks in the picture below).

It's rumored that "Navi 31" features one or two SIMD chiplets dubbed GCDs, featuring the GPU's main number crunching machinery, the RDNA3 compute units. These chiplets are likely built on the most advanced silicon fabrication node, likely TSMC 5 nm EUV, but we'll see. The GDDR6 memory controllers handling the chip's 384-bit wide GDDR6 memory interface, will be located on separate chiplets built on a slightly older node, such as TSMC 6 nm. This is not multi-GPU-a-stick, because both SIMD chiplets have uniform access to the entire 384-bit wide memory bus (which is not 2x 192-bit but 1x 384-bit), besides the other ancillaries. The "Navi 31" MCM are expected to be surrounded by JEDEC-standard 20 Gbps GDDR6 memory chips.

The Intel Labs and Components Research organizations have demonstrated the industry's highest reported yield and uniformity to date of silicon spin qubit devices developed at Intel's transistor research and development facility, Gordon Moore Park at Ronler Acres in Hillsboro, Oregon. This achievement represents a major milestone for scaling and working towards fabricating quantum chips on Intel's transistor manufacturing processes.

The research was conducted using Intel's second-generation silicon spin test chip. Through testing the devices using the Intel cryoprober, a quantum dot testing device that operates at cryogenic temperatures (1.7 Kelvin or -271.45 degrees Celsius), the team isolated 12 quantum dots and four sensors. This result represents the industry's largest silicon electron spin device with a single electron in each location across an entire 300 millimeter silicon wafer.

In an interview with Bits & Chips, ASML's CTO Martin van den Brink said that he believes that we might be reaching the end of the road for current semiconductor lithography technology in the not so distant future. However, for the time being, ASML is executing on its roadmap and after EUV, the next step is high-NA or high-numerical aperture and ASML is currently planning to have its first research high-NA scanner ready for a joint R&D venture with Imec in 2023. Assuming everything goes to plan, ASML is then planning on delivering the first R&D machines to its customers in 2024, followed by deliver of the first volume production machines using high-NA sometime in 2025. Van den Brink points out that due to the current supply chain uncertainties could affect the timing, in combination with the fact that ASML has a high demand for its EUV machines and the two technologies share a lot of components.

As such, current orders are the priority and high-NA development might be put on the back burner if need be, or as Van den Brink puts it "today's meal takes priority over tomorrow's." High-NA scanners are expected to be even more power hungry than EUV machines and are as such expected to pull around two Megawatts for the various stages. The next step in the evolution of semiconductor lithography is where ASML is expecting things to get problematic, as what the company is currently calling hyper-NA is expected to be prohibitively costly to manufacture and use. If the cost of hyper-NA grows as fast as we've seen in high-NA, it will pretty much be economically unfeasible," Van den Brink said. ASML is hoping to overcome the cost issues, but for now, the company has a plan for the next decade and things could very well change during that time and remove some of the obstacles that are currently being seen.

Here's our first look at the "AD103" and "AD104" chips powering the GeForce RTX 4080 16 GB and RTX 4080 12 GB, respectively, thanks to Ryan Smith from Anandtech. These are the second- and third-largest implementations of the GeForce "Ada" graphics architecture, with the "AD102" powering the RTX 4090 being the largest. Both chips are built on the same TSMC 4N (4 nm EUV) silicon fabrication process as the AD102, but are significantly distant from it in specifications. For example, the AD102 has a staggering 80 percent more number-crunching machinery than the AD103, and a 50 percent wider memory interface. The sheer numbers at play here, enable NVIDIA to carve out dozens of SKUs based on the three chips alone, before we're shown the mid-range "AD106" in the future.

The AD103 die measures 378.6 mm², significantly smaller than the 608 mm² of the AD102, and it reflects in a much lower transistor count of 45.9 billion. The chip physically features 80 streaming multiprocessors (SM), which work out to 10,240 CUDA cores, 320 Tensor cores, 80 RT cores, and 320 TMUs. The chip is endowed with a healthy ROP count of 112, and has a 256-bit wide GDDR6X memory interface. The AD104 is smaller still, with a die-size of 294.5 mm², a transistor count of 35.8 billion, 60 SM, 7,680 CUDA cores, 240 Tensor cores, 60 RT cores, 240 TMUs, and 80 ROPs. Ryan Smith says that the RTX 4080 12 GB maxes out the AD104, which means its memory interface is physically just 192-bit wide.

The AD102 silicon on which NVIDIA's new flagship graphics card, the GeForce RTX 4090, is based, is a marvel of semiconductor engineering. Built on the 4 nm EUV (TSMC 4N) silicon fabrication process, the chip has a gargantuan transistor-count of 76.3 billion, a nearly 170% increase over the previous GA102, and a die-size of 608 mm², which is in fact smaller than the 628 mm² die-area of the GA102. This is thanks to TSMC 4N offering nearly thrice the transistor-density of the Samsung 8LPP node on which the GA102 is based.

The AD102 physically features 18,432 CUDA cores, 568 fourth-generation Tensor cores, and 142 third-generation RT cores. The streaming multiprocessors (SM) come with special components that enable the Shader Execution Reordering optimization, which has a significant performance impact on both raster- and ray traced graphics rendering performance. The silicon supports up to 24 GB of GDDR6X or up to 48 GB of GDDR6+ECC memory (the latter will be seen in the RTX Ada professional-visualization card), across a 384-bit wide memory bus. There are 568 TMUs, and a mammoth 192 ROPs on the silicon.

Intel's next-generation "Meteor Lake" processor is the first mass-production client processor to embody the company's IDM 2.0 manufacturing strategy—one of building processors with multiple logic tiles interconnected with Foveros and a base-tile (essentially an interposer). Each tile is built on a silicon fabrication process most suitable to it, so that the most advanced node could be reserved for the component that benefits from it the most. For example, while you need the SIMD components of the iGPU to be built on an advanced low-power node, you don't need its display controller and media engine to, and these could be relegated to a tile built on a less advanced node. This way Intel is able to maximize its use of wafers for the most advanced nodes in a graded fashion.

Japanese tech publication PC Watch has annotated the "Meteor Lake" SoC, and points out that the vast majority of the chip's tiles and logic die-area is manufactured on TSMC nodes. The MCM consists of four logic tiles—the CPU tile, the Graphics tile, the SoC tile, and the I/O tile. The four sit on a base tile that facilitates extreme-density microscopic wiring interconnecting the logic tiles. The base tile is built on the 22 nm HKMG silicon fabrication node. This tile lacks any logic, and only serves to interconnect the tiles. Intel has an active 22 nm node, and decided it has the right density for the job.

Today ASML Holding NV (ASML) has published its 2022 second-quarter results. Q2 net sales of €5.4 billion, gross margin of 49.1%, net income of €1.4 billion. Record quarterly net bookings in Q2 of €8.5 billion. ASML expects Q3 2022 net sales between €5.1 billion and €5.4 billion and a gross margin between 49% and 50%. Expected sales growth for the full year of around 10%.

The value of fast shipments*in 2022 leading to delayed revenue recognition into 2023 is expected to increase from around €1 billion to around €2.8 billion.
"Our second-quarter net sales came in at €5.4 billion with a gross margin of 49.1%. Demand from our customers remains very strong, as reflected by record net bookings in the second quarter of €8.5 billion, including €5.4 billion from 0.33 NA and 0.55 NA EUV systems as well as strong DUV bookings.

Samsung Electronics Co., Ltd., the world leader in advanced memory technology, today announced that it has begun sampling the industry's first 16-gigabit (Gb) Graphics Double Data Rate 6 (GDDR6) DRAM featuring 24-gigabit-per-second (Gbps) processing speeds. Built on Samsung's third-generation 10-nanometer-class (1z) process using extreme ultraviolet (EUV) technology, the new memory is designed to significantly advance the graphics performance for next-generation graphics cards (Video Graphics Arrays), laptops and game consoles, as well as artificial intelligence-based applications and high-performance computing (HPC) systems.

"The explosion of data now being driven by AI and the metaverse is pushing the need for greater graphics capabilities that can process massive data sets simultaneously, at extremely high speeds," said Daniel Lee, executive vice president of the Memory Product Planning Team at Samsung Electronics. "With our industry-first 24 Gbps GDDR6 now sampling, we look forward to validating the graphics DRAM on next-generation GPU platforms to bring it to market in time to meet an onslaught of new demand."

ASML is one of the critical semiconductors companies, as they provide tools for making actual silicon. Located in the Netherlands, they are famous for their DUV and EUV lithography tools, used to etch designs onto silicon wafers. According to the report from Bloomberg, the United States governing body is negotiating with the Dutch government to restrict the export of ASML's products to China. This came to affection following US Deputy Commerce Secretary Don Graves's visit to the Netherlands to discuss supply chain issues and meeting with ASML Chief Executive Officer Peter Wennink. While these suggested export restrictions could be beneficial to the strategic placement of US against China, it would hurt ASML's revenue as sales in China accounted for a 16% share of the company's revenue in 2021.

It is recorded that the Chinese spending spree on tools has been the greatest among every country, lasting for two years in a row. By banning ASML from exporting its lithography tools to China, the US could theoretically halt Chinese plans for achieving the government's intended semiconductor independence. The talks with the Dutch government and ASML are still a work in progress, so we are yet to see if the deal is finalized. Additionally, it is worth pointing out that the major US semiconductor manufacturing tool makers like Applied Materials and Lam Research are already banned from exporting to China.

Samsung Electronics, the world leader in semiconductor technology, today announced that it has started initial production of its 3-nanometer (nm) process node applying Gate-All-Around (GAA) transistor architecture. Multi-Bridge-Channel FET (MBCFET), Samsung's GAA technology implemented for the first time ever, defies the performance limitations of FinFET, improving power efficiency by reducing the supply voltage level, while also enhancing performance by increasing drive current capability. Samsung is starting the first application of the nanosheet transistor with semiconductor chips for high performance, low power computing application and plans to expand to mobile processors.

"Samsung has grown rapidly as we continue to demonstrate leadership in applying next-generation technologies to manufacturing, such as foundry industry's first High-K Metal Gate, FinFET, as well as EUV. We seek to continue this leadership with the world's first 3 nm process with the MBCFET," said Dr. Siyoung Choi, President and Head of Foundry Business at Samsung Electronics. "We will continue active innovation in competitive technology development and build processes that help expedite achieving maturity of technology."

Intel's semiconductors nodes have been quite controversial with the arrival of the 10 nm design. Years in the making, the node got delayed multiple times, and only recently did the general public get the first 10 nm chips. Today, at IEEE's annual VLSI Symposium, we get more details about Intel's upcoming nodes, called Intel 4. Previously referred to as a 7 nm process, Intel 4 is the company's first node to use EUV lithography accompanied by various technologies. The first thing when a new process node is discussed is density. Compared to Intel 7, Intel 4 will double the transistor count for the same area and enable 20% higher performing transistors.

Looking at individual transistor size, the new Intel 4 node represents a very tiny piece of silicon that is even smaller than its predecessor. With a Fin Pitch of 30 nm, Contact Gate Poly Pitch of 50 nm between gates, and Minimum Metal Pitch (M0) of 50 nm, the Intel 4 transistor is significantly smaller compared to the Intel 7 cell, listed in the table below. For scaling, Intel 4 provides double the number of transistors in the same area compared to Intel 7. However, this reasoning is applied only to logic. For SRAM, the new PDK provides 0.77 area reduction, meaning that the same SoC built on Intel 7 will not be half the size of Intel 4, as SRAM plays a significant role in chip design. The Intel 7 HP library can put 80 million transistors on a square millimeter, while Intel 4 HP is capable of 160 million transistors per square millimeter.