Samsung and ARM announced a collaborative project last week—the partners are aiming to deliver an "optimized next generation Arm Cortex -X CPU" developed on the latest Gate-All-Around (GAA) process technology. Semiconductor industry watchdogs believe that Samsung Foundry's 3 nm GAA process did not meet sales expectations—reports suggest that many clients decided to pursue advanced three nanometer service options chez TSMC. The South Korean multinational manufacturing conglomerate is setting its sights forward—with an in-progress SF2 GAAFET process in the pipeline—industry insiders reckon that Samsung leadership is hoping to score a major victory within this next-gen market segment.

Lately, important industry figures have been hyping up Backside Power Supply Delivery Network (BSPDN) technology—recent Intel Foundry Services (IFS) press material lays claim to several technological innovations. A prime example being an ambitious five-nodes-in-four-years (5N4Y) process roadmap that: "remains on track and will deliver the industry's first backside power solution." A Chosun Business report proposes that Samsung is working on Backside Power Supply designs—a possible "game changer" when combined with in-house 2 nm SF2 GAAFET. Early experiments, allegedly, involving two unidentified ARM cores have exceeded expectations—according to Chosun's sources, engineers were able to: "reduce the chip area by 10% and 19%, respectively, and succeeded in improving chip performance and frequency efficiency to a single-digit level." Samsung Foundry could be adjusting its mass production timetables, based on freshly reported technological breakthroughs—SF2 GAAFET + BSPDN designs could arrive before the original targeted year of 2027. Prior to the latest developments, Samsung's BSPDN tech was linked to a futuristic 1.7 nm line.

Smartphone chipset industry watchdogs believe that the Samsung 3 nm GAA process did not meet customer expectations, due to alleged yield issues. TSMC is seemingly victorious in this segment, as reports suggest that a next-generation 3 nm node production goal of "100,000 monthly wafers by the end of 2024" has been set. Three days ago, Samsung Foundry revealed that it is working on a very advanced SF2 GAAFET process—press outlets in South Korea propose that the manufacturing giant is hoping to outmuscle its main rival in a future 2 nm node category. Tuesday's press introduction stated that a development partnership is set: "to deliver optimized next generation ARM Cortex -X CPU developed on Samsung Foundry's latest Gate-All-Around (GAA) process technology."

A Sedaily article posits that the company's cutting-edge manufacturing tech has already attracted interest from notable parties: "Samsung Electronics is taking advantage of these advantages to win orders for the 2 nm project. Samsung Electronics took its first step by winning an order to produce a 2 nm AI accelerator from Preferred Networks (PFN), Japan's largest AI company. Qualcomm, the world's largest system semiconductor design company, has entered into discussions with Samsung Electronics' System LSI Division, which designs high-performance chips, to produce 2 nm prototypes." December 2023 news reports suggested that Samsung leadership was considering a 2 nm wafer price discount—in order to stay competitive with competing foundry services. It is possible that Qualcomm is evaluating the 2 nm SF2 GAAFET process for a distant Snapdragon 8 "Gen 5" chipset, while Samsung LSI could be working on a 2 nm "Exynos 2600" SoC design.

The cutting edge 2 nm EUV foundry node by TSMC is expected to enter risk product in Q4 2024, according to a report by Taiwan-based industry observer DigiTimes. 2 nm would be an important milestone for the foundry company, as it would be the first from the company to implement GAA (gates all around) FETs, the technological successor to FinFETs, which drove silicon fabrication node development for almost a decade, from 16 nm to 3 nm. The GAAFET technology will be critical for the foundry's journey between 2 nm and 1 nm.

TSMC is expected to risk-produce chips on its 2 nm node in its new fab at the Baoshan campus in the Hsinchu Science Park, located in northern Taiwan. Should all go well with risk production, one can expect mass production of chips by Q2-2025. Until then, refinements to the company's final FinFET node, the N3 family, will remain the cutting-edge of silicon fabrication. Samsung has a similar 2025 target set for mass production on its 2 nm node, dubbed SF2. Across the Pacific, Intel Foundry Services has its Intel 20A node, which implements GAAFET (aka RibbonFET) technology aiming for similar timelines, including an ambitious 2024 mass production target.

Samsung Electronics foundry has reportedly bagged a mass production order for its cutting edge 2 nm EUV foundry node from Japanese AI chip startup PFN (Preferred Networks). This is reportedly the first major third party order for the 2 nm node. Founded in 2014, PFN specializes in AI and IoT chips, and spun off from Preferred Infrastructure. Samsung's 2 nm node, called the SF2, is on track for delivery of mass produced chips in 2025, which means much of 2024 will be spent on testing, validation, and risk production, with the node expected to go live toward the end of the year. Samsung SF2 is being designed to offer 25% higher power efficiency (at iso-clocks), and 12% increase in performance, over SF3 (3 nm EUV FinFET). In the semiconductor fabrication market, Samsung SF2 competes against TSMC N2 and Intel 20A.

DigiTimes Asia has reached out to insiders at fabrication toolmakers in an effort to delve deeper into claims made by industry analysts at the start of 2024—both SemiAnalysis and China Renaissance have proposed that TSMC is unlikely to adopt High-NA EUV production techniques within a five year period. The latest news article explores a non-upgrade approach for the next couple of years: "TSMC has not placed orders for high-numerical aperture (High-NA) extreme ultraviolet (EUV) tools and is unlikely to use the technology in 2 nm and 1.4 nm (A14) process manufacturing." Intel Foundry Services (IFS) will be one of the first semiconductor manufacturers to go online with ASML's latest and greatest machinery, although no firm timeframes have been confirmed. Team Blue's Taiwanese rival (and occasional business partner) is seemingly happy with its existing infrastructure, but industry watchdogs propose that cost considerations are key factors behind TSMC's cautious planning for the next decade.

The DigiTimes insider sources believe that TSMC will not budge until at least 2029, possibly coinciding with a 1 nm production node—analysts at China Renaissance reckon that High-NA EUV machines could be delivered in the future when facilities are readied for an "A10" codenamed process. TSMC published a very ambitious "transistor count" product timeline in early January (see below)—the first "1 nm" products are supposedly targeted for a 2030 rollout, but this schedule could change due to unforeseen circumstances. Intel is expected to "phase in" its fanciest ASML gear collection once the 18A process becomes old hat—Tom's Hardware thinks that 2026 - 2027 is a feasible timeframe.

This week in its earnings call, Samsung announced that its foundry business has received a significant order for a two nanometer AI chips, marking a major win for its advanced fabrication technology. The unnamed customer has contracted Samsung to produce AI accelerators using its upcoming 2 nm process node, which promises significant gains in performance and efficiency over today's leading-edge chips. Along with the AI chips, the deal includes supporting HBM and advanced packaging - indicating a large-scale and complex project. Industry sources speculate the order may be from a major hyperscaler like Google, Microsoft, or Alibaba, who are aggressively expanding their AI capabilities. Competition for AI chip contracts has heated up as the field becomes crucial for data centers, autonomous vehicles, and other emerging applications. Samsung said demand recovery in 2023 across smartphones, PCs and enterprise hardware will fuel growth for its broader foundry business. It's forging ahead with 3 nm production while eyeing 2 nm for launch around 2025.

Compared to its 3 nm process, 2 nm aims to increase power efficiency by 25% and boost performance by 12% while reducing chip area by 5%. The new order provides validation for Samsung's billion-dollar investments in next-generation manufacturing. It also bolsters Samsung's position against Taiwan-based TSMC, which holds a large portion of the foundry market share. TSMC landed Apple as its first 2 nm customer, while Intel announced 5G infrastructure chip orders from Ericsson and Faraday Technology using its "Intel 18A" node. With rivals securing major customers, Samsung is aggressively pricing 2 nm to attract clients. Reports indicate Qualcomm may shift some flagship mobile chips to Samsung's foundry at the 2 nm node, so if the yields are good, the node has a great potential to attract customers.

A Taiwan Economic Daily news article proposes that a couple of high profile clients are considering TSMC's 2 nanometer process—Apple is widely believed to be the first customer to join the foundry's queue for cutting edge services. The report posits that Intel is also signed up on the Taiwanese firm's 2 nm reservation list—TSMC is expected to start production in 2025—insiders reckon that Team Blue's "Nova Lake" CPU family is the prime candidate here. Its CPU tile is alleged to utilize TSMC 2 nm node. Intel's recent "Core" processor roadmaps do not display any technologies beyond 2025—many believe that "Nova Lake" is pencilled in for a loose 2026 launch window, perhaps within the second half of the year.

The existence of "Nova Lake" was revealed late last year by HWiNFO patch notes—a short entry mentioned preliminary support for the family's integrated GPU. Intel is engaged in hyping up of its own foundry's 20A and 18A processes, but remain reliant on TSMC plants for various bits of silicon. Industry tipsters reckon that aspects of "Lunar Lake" CPUs are based on the Taiwanese foundry's N3B node. Team Blue Corporation and United Microelectronics Corporation (UMC) announced a new development partnership last week, but initial offerings will arrive on a relatively passé "12-nanometer semiconductor process platform." TSMC's very advanced foundry services seem to be unmatched at this juncture.

Japanese tech giant Canon hopes to shake up the semiconductor manufacturing industry by shipping new low-cost nanoimprint lithography (NIL) machines as early as this year. The technology, which stamps chip designs onto silicon wafers rather than using more complex light-based etching like market leader ASML's systems, could allow Canon to undercut rivals and democratize leading-edge chip production. "We would like to start shipping this year or next year...while the market is hot. It is a very unique technology that will enable cutting-edge chips to be made simply and at a low cost," said Hiroaki Takeishi, head of Canon's industrial group overseeing nanoimprint lithography technological advancement. Nanoimprint machines target a semiconductor node width of 5 nanometers, aiming to reach 2 nm eventually. Takeishi said the technology has primarily resolved previous defect rate issues, but success will depend on convincing customers that integration into existing fabrication plants is worthwhile.

There is skepticism about Canon's ability to significantly disrupt the market led by ASML's expensive but sophisticated extreme ultraviolet (EUV) lithography tools. However, if nanoimprint can increase yields to nearly 90% at lower costs, it could carve out a niche, especially with EUV supply struggling to meet surging demand. Canon's NIL machines are supposedly 40% the cost of ASML machinery, while operating with up to 90% lower power draw. Initially focusing on 3D NAND memory chips rather than complex processors, Canon must contend with export controls limiting sales to China. But with few options left, Takeishi said Canon will "pay careful attention" to sanctions risks. If successfully deployed commercially after 15+ years in development, Canon's nanoimprint technology could shift the competitive landscape by enabling new players to manufacture leading-edge semiconductors at dramatically lower costs. But it remains to be seen whether the new machines' defect rates, integration challenges, and geopolitical headwinds will allow Canon to disrupt the chipmaking giants it aims to compete with significantly.

A DigiTimes Asia report posits that TSMC is preparing another VVIP foundry lane for Apple Inc.—insiders claim that the Taiwanese foundry giant is in the process of expanding production capacity into next generation 2 nm nanometer fields. This expensive and time consuming endeavor is only made possible with the reassurance of big customers being added to the foundry's order books. TSMC's 2 nm-class N2, N2P, and N2X process technologies are due in 2025 and beyond (according to recent presentation slides)—these advanced packages are set to drop with all sorts of innovations: nanosheet gate-all-around (GAA) transistors, backside power delivery, and super-high-performance metal-insulator-metal (SHPMIM). According to a DigiTimes source "Apple is widely believed to be the initial client to utilize the (next-gen) process."

Apple and NVIDIA were reported to be ahead of many important clients in the queue for TSMC's 3 nm process nodes, so it is not surprising to see old patterns repeat (according to industry rumors) again. Apple is expected to update its next generation iPhones, iPad, and Mac laptop product lines with more advanced Bionic and M-series chipsets in 2025. Last year's roster included a rollout of 3 nm TSMC silicon across Apple A17 Pro and M3 ARM-based processors.

TSMC's 2 nm-class foundry node, dubbed N2, will enter mass production only in 2025, a report by the Financial Times says. The premier Taiwan-based foundry has been reportedly showcasing TSMC N2 to its biggest customer for advanced nodes, Apple. The node will likely power Apple's in-house silicon that drives the iPhone 17 Pro and Pro Max devices that are slated for 2025. This implies that the current 3 nm class nodes from TSMC will continue to power Apple silicon into 2024 and its iPhone 16 Pro/Pro Max.

The current Apple A17 Pro and M3 chips powering the iPhone 15 Pro/Max and the H2-2023 Macs are based on TSMC's N3 node, with a 183 MTr/mm² transistor density. TSMC has four other 3 nm-class nodes, with the N3E node that just entered mass production to offer a jump to 215.6 MTr/mm², and its 2024 successor, the N3P, pushing transistor densities further up to 224 MTr/mm². TSMC's first 2 nm-class node, the N2, offers a jump to around 259 MTr/mm², which makes the N3P a nice halfway point for Apple between the N3 and N2, for its 2024 silicon.

TrendForce's research indicates a dynamic third quarter for the global foundry industry, marked by an uptick in urgent orders for smartphone and notebook components. This surge was fueled by healthy inventory levels and the release of new iPhone and Android devices in 2H23. Despite persisting inflation risks and market uncertainties, these orders were predominantly executed as rush orders. Additionally, TSMC and Samsung's high-cost 3 nm manufacturing process had a positive impact on revenues, driving the 3Q23 value of the top ten global foundries to approximately US$28.29 billion—a 7.9% QoQ increase.

Looking ahead to 4Q23, the anticipation of year-end festive demand is expected to sustain the inflow of urgent orders for smartphones and laptops, particularly for smartphone components. Although the end-user market is yet to fully recover, pre-sales season stockpiling for Chinese Android smartphones appears to be slightly better than expected, with demand for mid-to-low range 5G and 4G phone APs and continued interest in new iPhone models. This scenario suggests a continued upward trend for the top ten global foundries in Q4, potentially exceeding the growth rate seen in Q3.

Rapidus Corporation, a company involved in the research, development, design, manufacture, and sales of advanced logic semiconductors, today announced an agreement with Tenstorrent Inc., a next-generation computing company building computers for AI, to jointly develop semiconductor IP (design assets) in the field of AI edge devices based on 2 nm logic semiconductors.

In addition to its AI processors and servers, Tenstorrent built and owns the world's most performant RISC-V CPU IP and licenses that technology to its customers around the world. Through this technological partnership with Rapidus, Tenstorrent will accelerate the development of cutting-edge devices to meet the needs of the ever-evolving digital society.

Socionext today announced a collaboration with Arm and TSMC for the development of an innovative power-optimized 32-core CPU chiplet in TSMCʼs 2 nm silicon technology, delivering scalable performance for hyperscale data center server, 5/6G infrastructure, DPU and edge-of- network markets.

The engineering samples are targeted to be available in 1H2025. This advanced CPU chiplet proof-of-concept using Arm Neoverse CSS technology is designed for single or multiple instantiations within a single package, along with IO and application-specific custom chiplets to optimize performance for a variety of end applications.

According to TechNews.tw, TSMC could postpone its 2 nm semiconductor manufacturing node for 2026. If the rumors about TSMC's delayed 2 nm production schedule are accurate, the implications could reverberate throughout the semiconductor industry. TSMC's alleged hesitancy could be driven by multiple factors, including the architectural shift from FinFET to Gate-All-Around (GAA) and potential challenges related to scaling down to 2 nm. The company is a crucial player in this space, and a delay could offer opportunities for competitors like Samsung, which has already transitioned to GAA transistor architecture for its 3 nm chips. Given the massive demand for advanced nodes due to the rise of AI, IoT, and other next-gen technologies, it is surprising to hear "sluggish" demand reports.

However, it's also possible that it's too early for customers to make firm commitments for 2025 and beyond. TSMC has dismissed these rumors, stating that construction is progressing according to plan, which includes having 2 nm pilot run in 2024, and mass production in the second half of 2025.. Despite this, any delay in TSMC's roadmap could serve as a catalyst for shifts in market dynamics. Companies that rely heavily on TSMC's advanced nodes might need to reassess their timelines and strategies. Moreover, if Samsung can capitalize on this opportunity, it could somewhat level the playing field. As of now, though, it's essential to approach these rumors with caution until more concrete information becomes available.

Samsung Electronics today reported financial results for the second quarter ended June 30, 2023. The Company posted KRW 60.01 trillion in consolidated revenue, a 6% decline from the previous quarter, mainly due to a decline in smartphone shipments despite a slight recovery in revenue of the DS (Device Solutions) Division. Operating profit rose sequentially to KRW 0.67 trillion as the DS Division posted a narrower loss, while Samsung Display Corporation (SDC) and the Digital Appliances Business saw improved profitability.

The Memory Business saw results improve from the previous quarter as its focus on High Bandwidth Memory (HBM) and DDR5 products in anticipation of robust demand for AI applications led to higher-than-guided DRAM shipments. System semiconductors posted a decline in profit due to lower utilization rates on weak demand from major applications.

Semiconductor industry research firm TechInsights said it has found that Samsung's 3 nm GAA (gate-all-around) process has been incorporated into the crypto miner ASIC (Whatsminer M56S++) from a Chinese manufacturer, MicroBT. In a Disruptive Technology Event Brief exclusively provided to DIGITIMES Asia, TechInsights points out that the significance of this development lies in the commercial utilization of GAA technology, which facilitates the scaling of transistors to 2 nm and beyond. "This development is crucial because it has the potential to enhance performance, improve energy efficiency, keep up with Moore's Law, and enable advanced applications," said TechInsights, identifying the MicroBT ASIC chip the first commercialized product using GAA technology in the industry.

But this would also reveal that Samsung is the foundry for MicroBT, using the 3 nm GAA process. DIGITIMES Research semiconductor analyst Eric Chen pointed out that Samsung indeed has started producing chips using the 3 nm GAA process, but the capacity is still small. "Getting revenues from shipment can be defined as 'commercialization', but ASIC is a relatively simple kind of chip to produce, in terms of architecture."

According to Taiwanese media, TSMC will start production of its first 1.4 nm fab in 2026, with chip production in the fab said to start sometime in 2027 or 2028. The new fab will be located in Longtan Science Park outside of Hsinchu in Taiwan, where many of TSMC's current fabs are located. TSMC is currently constructing a 2 nm and below node R&D facility at a nearby plot of land to where the new fab is expected to be built. This facility is expected to be finished in 2025 and TSMC has been allocated a total area of just over 158 hectares of land for future expansion in the area.

In related news, TSMC is expected to be charging US$25,000 per 2 nm GAA wafer, which is an increase of about a fifth compared to its 3 nm wafers which are going for around US$20,000. This is largely due to the nodes being fully booked and TSMC being able to charge a premium for its cutting edge nodes. TSMC is also expanding in CoWoS packaging facilities due to increased demand from both AMD and NVIDIA for AI related products. Currently TSMC is said to be able to output 12,000 CoWoS wafers per month and this is twice as much as last year, yet TSMC is unable to meet demand from its customers.

Samsung Electronics, a world leader in advanced semiconductor technology, today announced its latest foundry technology innovations and business strategy at the 7th annual Samsung Foundry Forum (SFF) 2023. Under the theme "Innovation Beyond Boundaries," this year's forum delved into Samsung Foundry's mission to address customer needs in the artificial intelligence (AI) era through advanced semiconductor technology.

Over 700 guests, from customers and partners of Samsung Foundry, attended this year's event, of which 38 companies hosted their own booths to share the latest technology trends in the foundry industry.

TrendForce reports that the global top 10 foundries witnessed a significant 18.6% QoQ decline in revenue during the first quarter of 2023. This decline—amounting to approximately US$27.3 billion—can be attributed to sustained weak end-market demand and the compounded effects of the off-peak season. The rankings also underwent notable changes, with GlobalFoundries surpassing UMC to secure the third position, and Tower Semiconductor surpassing PSMC and VIS to claim the seventh spot.

Declining capacity utilization rate and shipment volume contribute to widened revenue decline
The revenue decline in Q1 was primarily influenced by declining capacity utilization rates and shipment volume across the top 10 foundries. For instance, TSMC generated US$16.74 billion in revenue—marking a 16.2% QoQ drop in revenue. Weakened demand for mainstream applications such as laptops and smartphones led to a significant decline in the utilization rates and revenue of the 7/6 nm and 5/4 nm processes, falling over 20% and 17%, respectively. While the second quarter may see temporary relief coming from rush orders, the persistently low capacity utilization rate indicates that revenue is likely to continue declining, albeit at a slower pace compared to Q1.

Samsung Electronics today reported financial results for the first quarter ended March 31, 2023. The Company posted KRW 63.75 trillion in consolidated revenue, a 10% decline from the previous quarter, as overall consumer spending slowed amid the uncertain global macroeconomic environment. Operating profit was KRW 0.64 trillion as the DS (Device Solutions) Division faced decreased demand, while profit in the DX (Device eXperience) Division increased.

The DS Division's profit declined from the previous quarter due to weak demand in the Memory Business, a decline in utilization rates in the Foundry Business and continued weak demand and inventory adjustments from customers. Samsung Display Corporation (SDC) saw earnings in the mobile panel business decline quarter-on-quarter amid a market contraction, while the large panel business slightly narrowed its losses. The DX Division's results improved on the back of strong sales of the premium Galaxy S23 series as well as an enhanced sales mix focusing on premium TVs.

TSMC today showcased its latest technology developments at its 2023 North America Technology Symposium, including progress in 2 nm technology and new members of its industry-leading 3 nm technology family, offering a range of processes tuned to meet diverse customer demands. These include N3P, an enhanced 3 nm process for better power, performance and density, N3X, a process tailored for high performance computing (HPC) applications, and N3AE, enabling early start of automotive applications on the most advanced silicon technology.

With more than 1,600 customers and partners registered to attend, the North America Technology Symposium in Santa Clara, California is the first of the TSMC's Technology Symposiums around the world in the coming months. The North America symposium also features an Innovation Zone spotlighting the exciting technologies of 18 emerging start-up customers.

Future Japanese chipmaker Rapidus has announced that their first fab will be located in Chitose, Hokkaido, located in northern Japan. The planned 2 nm fab will be one of the most advanced fabs in the world once it's ready and construction is said to be starting in September, thanks to approval by the related Japanese government agencies. So far, the Japanese government has approved 330 billion yen for Rapidus, with the most recent investment being 260 billion yen or the equivalent of US$1.94 billion.

However, the total investment into the 2 nm fab is expected to end up somewhere around 5 trillion yen (~US$37.5 billion) in total investments before the fab is ready for mass production. Rapidus is collaborating with IBM and has already sent a group of researchers to its Albany Nanotech facility in upstate New York, which is one of the world's most advanced semiconductor research facilities. At the same time, Japan is working on building a local talent pool of researchers and semiconductor plant workers, by spearheading specialised training for select university students from Japan's top universities. Time will tell if this gamble pays off for Japan, as it's going to be a huge investment before the new fab stands ready in early 2025.

TrendForce reports that the US Department of Commerce recently released details regarding its CHIPS and Science Act, which stipulates that beneficiaries of the act will be restricted in their investment activities—for more advanced and mature processes—in China, North Korea, Iran, and Russia for the next ten years. The scope of restrictions in this updated legislation will be far more extensive than the previous export ban, further reducing the willingness of multinational semiconductor companies to invest in China for the next decade.

CHIPS Act will mainly impact TSMC; and as the decoupling of the supply chain continues, VIS and PSMC capture orders rerouted from Chinese foundries
In recent years, the US has banned semiconductor exports and passed the CHIPS Act, all to ensure supply chains decoupling from China. Initially, bans on exports were primarily focused on non-planar transistor architecture (16/14 nm and more advanced processes). However, Japan and the Netherlands have also announced that they intend to join the sanctions, which means key DUV immersion systems, used for producing both sub-16 nm and 40/28 nm mature processes, are likely to be included within the scope of the ban as well. These developments, in conjunction with the CHIPS Act, mean that the expansion of both Chinese foundries and multinational foundries in China will be suppressed to varying degrees—regardless of whether they are advanced or mature processes.

An AMD engineer inadvertently leaked the core codenames of the company's upcoming "Zen 5" and "Zen 6" microarchitectures. It's important to understand here what has been leaked. "Zen 5" and "Zen 6" are microarchitecture names, just like the current "Zen 4" and past "Zen 3" or older. AMD uses codenames for the CCD (CPU complex dies) based on these microarchitectures, which it shares between Ryzen client and EPYC enterprise processors. For example, the CCD codename for "Zen 3" is "Brekenridge," and for "Zen 4" it is "Durango." AMD also uses codenames for the CPU cores themselves. "Zen 3" CPU cores are codenamed "Cerebrus," and "Zen 4" CPU cores "Persphone." And now, the leak:

The CCD based on the upcoming "Zen 5" microarchitecture is codenamed "Eldora," and the "Zen 5" CPU core itself is codenamed "Nirvana." There's no codename for the CCD based on "Zen 6," but its CPU cores are codenamed "Morpheus." The "Zen 5" microarchitecture will be based on the 3 nm EUV foundry node; while "Zen 6" will be 2 nm EUV. The engineer in the screenshot is contributing to the power-management technology behind "Zen 5" and "Zen 6," and states that their work on "Zen 5" spanned January-December of 2022, which means the development phase of the next "Zen" architecture is probably complete, and the architecture is undergoing testing and refinement. It's also claimed that work on at least the power-management aspect of "Zen 6" has started from January 2023.

Intel Foundry Services, the in-house semiconductor foundry of Intel, announced that its 2 nm-class Intel 20A and 1.8 nm-class Intel 18A foundry nodes have completed development, and are on course for mass-producing chips on their roadmap dates. Chips are expected to begin mass-production on the Intel 20A node in the first half of 2024, while those on the Intel 18A node are expected to begin in the second half of 2024. The completion of the development phase means that Intel has finalized the specifications and performance/power targets of the nodes, the tools and software required to make the chips, and can now begin ordering them to build the nodes. Intel has been testing these nodes through 2022, and with the specs being finalized, chip-designers can accordingly wrap up development of their products to align with what these nodes have to offer.

Intel 20A (or 20-angstrom, or 2 nm) node introduces gates-all-around (GAA) RibbonFET transistors with PowerVIAs (an interconnect innovation that contributes to transistor densities). The Intel 20A node is claimed to offer a 15% performance/Watt gain over its predecessor, the Intel 3 node (FinFET EUV, 3 nm-class), which by itself offers an 18% performance/Watt gain over Intel 4 (20% perf/Watt gain over the current Intel 7 node), the node that is entering mass-production very soon. The Intel 18A node is a further refinement of Intel 20A, and introduces a design improvement to the RibbonFET that increases transistor density at scale, and a claimed 10% performance/Watt improvement over Intel 20A.