Tuesday, December 3rd 2024
TSMC Boosts 2 nm Yields by 6%, Passing Savings to Customers
Being the leading-edge semiconductor manufacturing company, TSMC actively works on increasing the efficiency of its upcoming nodes, even when they are finalized and ready for high-volume manufacturing. According to a TSMC employee identified as Dr. Kim on X, recent test runs of the 2 nm N2 nodes show a 6% improvement in production yields compared to baseline expectations. This advancement could translate into substantial cost savings for the company's customers when mass production begins in late 2025. However, specific details about whether the gains were achieved in SRAM or logic test chips remain undisclosed. The timing is particularly noteworthy as TSMC prepares to launch its shuttle test wafer services for 2 nm technology in January. The N2 process represents a giant leap for TSMC, marking its first gate-all-around (GAA) nanosheet transistors implementation, the first step to derive from the classical FinFET design.
According to TSMC's projections, chips manufactured using the N2 process will consume 25-30% less power while maintaining the same transistor count and frequency as its N3E node. Additionally, the technology is expected to deliver 10-15% performance improvements and achieve a 15% increase in transistor density. A key innovation in the N2 process is the enhanced design of its GAA nanosheet transistors, which offers improved electrostatic control and reduced gate leakage compared to 3 nm FinFET transistors, given that the gate can be controlled from all sides. This advancement enables smaller high-density transistors to maintain reliable performance through better threshold voltage tuning capabilities. With approximately seven to eight months until full-scale volume production begins, the company has a substantial window to optimize the manufacturing process further and potentially achieve additional yield improvements, although that is less likely.
Source:
via Tom's Hardware
According to TSMC's projections, chips manufactured using the N2 process will consume 25-30% less power while maintaining the same transistor count and frequency as its N3E node. Additionally, the technology is expected to deliver 10-15% performance improvements and achieve a 15% increase in transistor density. A key innovation in the N2 process is the enhanced design of its GAA nanosheet transistors, which offers improved electrostatic control and reduced gate leakage compared to 3 nm FinFET transistors, given that the gate can be controlled from all sides. This advancement enables smaller high-density transistors to maintain reliable performance through better threshold voltage tuning capabilities. With approximately seven to eight months until full-scale volume production begins, the company has a substantial window to optimize the manufacturing process further and potentially achieve additional yield improvements, although that is less likely.
14 Comments on TSMC Boosts 2 nm Yields by 6%, Passing Savings to Customers
Last I checked, fabs sold wafer allocation, not individual chips. As long as the price doesn't go up, then the customer is the one who benefits. And IIRC the 2nm contracts were already signed.
INTC - 18A, >200MTr/mm^2
TSMC - N2, >250MTr/mm^2
SMSG - SF2, >200MTr/mm^2
BTW, that's an extreme shredding of Intel process roadmaps that forecasted Intel 3, 20A and 18A all by the end of this year.
Quick back of the hand math means 75% of the energy cost for 110% of the performance, or a die of the same size theoretically having 1.1/0.75=1.467 of the performance per watt, or a 46.7% uplift in performance per watt. If we look at the generational gap as about 15% per price bracket, that's mean a middle tier card can have either a much smaller die size (factoring in the 15% density increase in transistors) while running cooler and having the same performance, or have roughly the same die size without melting down.
This would be great if we actually saw any of this savings as consumers...but given that all of this wafer production is going to go to AI accelerators, given they are the biggest margin product on the market right now, it's not going to do anything but pad budgets. Sigh...wish we could see some of that price decrease...
nonetheless this will probably blow Intel out of the water, same with Samsung.
But good job non the less TSMC.
Intel has had 14nm with pluses for how many years? Today, they can't get right even the first step after 14nm, the 10nm process is still broken.
So yes, you can't make the transistors smaller :D