According to The Korea Economic Daily, an unlikely alliance—involving Samsung Electronics and Palantir Technologies—was formed at the end of last year. Late last week, insiders posited that the South Korean megacorporation's Foundry business was going through troubled times. It is not clear whether the assistance provided by Palantir's AI-infused suite has produced pleasing results chez Samsung's flagship production hubs, but insiders reckon that utilization of the software started just before Christmas. Local media outlets view this unusual pairing as a "gamble"—reportedly, the new-ish initiative has targeted an improved "semiconductor yield (ratio of good products in total production), quality, and productivity."

The Samsung Foundry appears to be going "all-in" with its 2 nm GAA node process; industry moles picked up on signals transmitted by an alleged special "task force (TF)." This elite team is reportedly entrusted with a challenging two-pronged goal; get 2 nm GAA over the finish line by late 2025, alongside the (connected) finalization of a much-rumored "Exynos 2600" mobile chipset. The Korea Economic Daily news article mentions the expansion of a "Samsung DS Division AI Center" back in December (2025), but falls short of labelling this department as the aforementioned "special task force." Despite a previous reluctance to share sensitive data with external companies, the latest report suggests a significant change in strategy. Further details were disclosed: "(Samsung's) collaboration with Palantir is handled by the DS Division AI Center...The AI Center is an organization that merged the DS Division Innovation Center and SAIT (formerly Samsung Advanced Institute of Technology) AI Center, and is developing DS Division-specific technologies using AI, advancing development software, building AI platforms, and controlling and advancing facilities and infrastructure." Around late February, industry inside trackers predicted continued "smooth" progress with the 2 nm GAA node. Samsung Foundry's fully upgraded "S2" mass production line is expected to come online by Q4 2025.

Samsung's foundry operation has experienced many setbacks over the past six months, according to a steady feed of insider reports. Last November, industry moles leaked details of an apparent abandonment of the company's 3 nm Gate-All-Around (GAA) process. Significant yield problems prompted an alleged shift into 2 nm territories, with a next-gen flagship Exynos mobile processor linked to this cutting-edge node. According to a mid-week Chosun Daily article, Samsung and its main rival—TSMC—are in a race to establish decent yields of 2 nm wafers, ahead of predicted "late 2025" mass production kick-offs. The publication's inside track points to the Taiwanese foundry making the most progress (with an estimated 60%), but watchdogs warn that it is too early to bet against the South Korean competitor.

Despite murmurs of current 20 - 30% yields, the Samsung's Hwaseong facility is touted to make "smooth" progress over the coming months. Chosun's sources believe that Samsung engineers struggled to get 3 nm GAA "up to snuff," spending around three years on development endeavors (in vain). In comparison, the making of 2 nm GAA is reported to be less bumpy. A fully upgraded "S3" foundry line is expected to come online by the fourth quarter of this year. An unnamed insider commented on rumors of better than anticipated forward motion chez Samsung Electronics: "there are positive aspects to this as it has shown technological improvements, such as the recent increase in the yield of its 4 nm process by up to 80%." Recent-ish reports suggest that foundry teams have dealt with budget cuts, as well as mounting pressure from company leadership to hit deadlines.

Lam Research Corporation today announced that its innovative dry photoresist (dry resist) technology has been qualified for direct-print 28 nm pitch back end of line (BEOL) logic at 2 nm and below by imec, a leading research and innovation hub in nanoelectronics and digital technologies. An advanced patterning technique introduced by Lam, dry resist enhances the resolution, productivity and yield of extreme ultraviolet (EUV) lithography, a pivotal technology used in the production of next-generation semiconductor devices.

"Lam's dry photoresist technology provides unparalleled low-defectivity, high-resolution patterning," said Vahid Vahedi, chief technology and sustainability officer at Lam Research. "We are excited to offer this technology to imec and its partners as a critical process in the design and manufacturing of leading-edge semiconductor devices."

Being the leading-edge semiconductor manufacturing company, TSMC actively works on increasing the efficiency of its upcoming nodes, even when they are finalized and ready for high-volume manufacturing. According to a TSMC employee identified as Dr. Kim on X, recent test runs of the 2 nm N2 nodes show a 6% improvement in production yields compared to baseline expectations. This advancement could translate into substantial cost savings for the company's customers when mass production begins in late 2025. However, specific details about whether the gains were achieved in SRAM or logic test chips remain undisclosed. The timing is particularly noteworthy as TSMC prepares to launch its shuttle test wafer services for 2 nm technology in January. The N2 process represents a giant leap for TSMC, marking its first gate-all-around (GAA) nanosheet transistors implementation, the first step to derive from the classical FinFET design.

According to TSMC's projections, chips manufactured using the N2 process will consume 25-30% less power while maintaining the same transistor count and frequency as its N3E node. Additionally, the technology is expected to deliver 10-15% performance improvements and achieve a 15% increase in transistor density. A key innovation in the N2 process is the enhanced design of its GAA nanosheet transistors, which offers improved electrostatic control and reduced gate leakage compared to 3 nm FinFET transistors, given that the gate can be controlled from all sides. This advancement enables smaller high-density transistors to maintain reliable performance through better threshold voltage tuning capabilities. With approximately seven to eight months until full-scale volume production begins, the company has a substantial window to optimize the manufacturing process further and potentially achieve additional yield improvements, although that is less likely.

The American semiconductor landscape reached a significant milestone as TSMC's new Arizona manufacturing facility demonstrated remarkable production efficiency, exceeding its Taiwanese counterparts by 4% in yield rates. This achievement, revealed at a recent industry webinar by the company's US division chief, represents a major step forward in America's push to strengthen domestic chip manufacturing capabilities. Since initiating its 4 nm node production operations this spring, the Phoenix-based facility has demonstrated impressive technical proficiency, achieving production standards that match and surpass TSMC's established Taiwanese facilities. The project, backed by substantial federal support, including $11.6 billion in combined grants and loans plus significant tax incentives, aims to establish three cutting-edge manufacturing plants in Arizona.

The company's global leadership praised the facility's performance, noting its strategic importance in demonstrating TSMC's ability to maintain exceptional manufacturing standards across international locations. This success carries particular weight given the project's earlier hurdles, which included workforce challenges and timeline adjustments that shifted the entire production schedule by approximately one year. This development gains additional significance against industry-wide challenges, particularly as competitors like Intel and Samsung face operational and financial obstacles. The semiconductor giant's plans now extend to potential further expansion, with the Phoenix site capable of hosting up to six manufacturing facilities. Future growth prospects could be enhanced by proposed additional government initiatives supporting domestic chip production.

The grass isn't always greener on the other side, especially as we're running out of sides in the advanced semiconductor manufacturing sector. A recent report by Business Korea highlights Samsung Securities' July publication titled "Geopolitical Paradigm Shift and Industry," which paints a less-than-optimistic picture of Samsung's current state of affairs. The report even evaluates a possible spinoff of Samsung Foundry. The Korean tech giant has faced various business setbacks related to its state-of-the-art 3 nm Gate-All-Around (GAA) FET node. Reports indicate that this node only manages to yield 10-20% of working silicon, making potential customers reluctant to secure partnerships with Samsung. Samsung Securities projects that Samsung Foundry, along with the LSI division, will suffer a 500 billion won (about $385 million) loss this year.

Poor yields and difficulty securing customers have left Samsung facing tough choices, including the possible sale of its massive Foundry unit, which manufactures logic for external customers. It's noteworthy that Samsung is one of only three companies left in the advanced semiconductor manufacturing field, alongside TSMC and Intel. Many companies struggled to deliver results when transitioning to sub-7 nm nodes. Global Foundries dropped out of the race to focus on mature nodes, while Intel faced delays. TSMC has been the only company so far to consistently set and execute its goals, positioning itself as the industry leader. With low yields on the 3 nm GAA FET node, Samsung currently holds 11.5% of the global foundry market share in Q2, while TSMC dominates with 62.3%.

Samsung's foundry plans have again hit a major setback. The company notified staff at its Taylor, Texas facility that it was temporarily removing workers from the site because it is still experiencing challenges with 2 nm semiconductor yields, delaying mass production timelines from late 2024 to 2026. The Taylor site had been anticipated as the flagship facility for Samsung's sub-4 nm production, allowing access to potential customers near the facility. While Samsung has moved rapidly in terms of process development, its yields for advanced nodes have outstripped them, the company's yields for sub-3 nm processes hover around 50%, with Gate-All-Around (GAA) technology witnessing yields of only 10-20%, significantly lower than neighboring competitor TSMC's 60-70% for corresponding nodes.

The yield gaps that the company is experiencing have exacerbated the gap in market share, with TSMC capturing 62.3% of the global foundry market share in Q2 versus Samsung's 11.5%. The company is struggling to gain share despite efforts by Chairman Lee Jae-yong - including visits to component suppliers ASML, and Zeiss - and these yields put at risk as much as 9 trillion won in U.S. CHIP Act potential subsidies that are dependent upon operational milestones.

In a conversation with Intel's CEO Pat Gelsinger, industry analyst Patrick Moorhead revealed that Intel's Meteor Lake CPU platform suffers from some production issues. More specifically, Intel has been facing some yield and/or back-end production issues with its Meteor Lake platform, resulting in a negative impact on Intel's margins when producing the chip. The market is showing great demand for these chips, and Intel has been forced to run productions of "hot lots"-- batch production of silicon with the highest priority that gets moved to the front of the production line so they can get packaged as fast as possible. While this is a good sign that the demand is there, running hot lots increases production costs overall as some other wafers have to go back so Meteor Lake can pass.

The yield issues associated with Meteor Lake could be stemming from the only tile made by Intel in the MTL package: the compute tile made on the Intel 4 process. Intel 4 process is specific to Meteor Lake. No other Intel product uses it, not even the Xeon 6, which uses Intel 3, or any of the upcoming CPUs like Arrow Lake, which uses the Intel 20A node. So, Intel is doing multiple nodes for multiple generations of processors, further driving up costs as typical high-volume production with a single node for multiple processors yields lower costs. Additionally, the company is left with lots of "wafers to burn" with Intel 4 node, so even with Meteor Lake having yield issues, the production is ultimately fine, while the operating costs and margins take a hit.

Industry insiders reckon that Samsung Electronics is transitioning to molded underfill (MR-MUF) production techniques—rival memory manufacturer, SK Hynix, champions this chip making technology. A Reuters exclusive has cited claims made by five industry moles—they believe that Samsung is reacting to underwhelming HBM production yields. The publication proposes that: "one of the reasons Samsung has fallen behind (competing producers) is its decision to stick with chip making technology called non-conductive film (NCF) that causes some production issues, while Hynix switched to the mass reflow molded underfill (MR-MUF) method to address NCF's weakness." The report suggests that Samsung is in the process of ordering new MUF-related equipment.

One anonymous source stated: "Samsung had to do something to ramp up its HBM (production) yields... adopting MUF technique is a little bit of swallow-your-pride type thing for (them), because it ended up following the technique first used by SK Hynix." Reuters managed to extract a response from the giant South Korean multinational—a company spokesperson stated: "we are carrying out our HBM3E product business as planned." They indicated that NCF technology remains in place as an "optimal solution." Post-publication, another official response was issued: "rumors that Samsung will apply MR-MUF to its HBM production are not true." Insiders propose a long testing phase—Samsung is rumored to be sourcing MUF materials, but mass production is not expected to start this year. Three insiders allege that Samsung is planning to "use both NCF and MUF techniques" for a new-generation HBM chip.

According to Korean business news publication ChosunBiz, both Samsung and TSMC are struggling with their 3 nm node yields. The two companies have different approaches to their 3 nm nodes, with Samsung using GAA FET (Gate All Around), whereas TSMC is continuing with its FinFET technology. That said, TSMC has at least five known 3 nm nodes, of which two should be in production by now, assuming N3E has proved to be reliable enough to kick off. Samsung on the other hand has three known 3 nm nodes, with only one in production so far, called 3GAE.

ChosunBiz reports that neither company is getting the kind of yields that you'd expect from a node that should have been in volume production for around a year by now, with Samsung apparently being somewhat better than TSMC. At 60 and 50 percent respectively, neither Samsung nor TSMC are anywhere near decent yields. Anything below 70 percent is considered very poor and even the 60 percent claim in Samsungs case, is apparently limited to some kind of Chinese mining ASIC and doesn't include the SRAM you find in most modern processors. ChosunBiz also mentions a source familiar with Samsung's foundry business who mentions a yield closer to 50 percent for the company. The same source also mentions that Samsung needs to reach at least 70 percent yield to be able to attract major customers to its 3 nm node.

Competition between Samsung and TSMC in the 4 nm and 3 nm foundry process markets is about to heat up, with the Korean foundry claiming yields competitive to those of TSMC, according to a report in the Kukmin Ilbo, a Korean daily newspaper. 4 nm is the final silicon fabrication process to use the FinFET technology that powered nodes ranging between 16 nm to 4 nm. Samsung Foundry is claiming 4 nm wafer yields of 75%, against the 80% yields figure put out by TSMC. 4 nm powers several current-generation mobile SoCs, PC processors, and more importantly, the GPUs driving the AI gold-rush.

Things get very interesting with 3 nm, the node that debuts GAA-FET (gates all around FET) technology. Here, Samsung claims to offer higher yields than TSMC, with its 3 nm GAA node clocking 60% yields, against 55% put out by TSMC. Samsung was recently bitten by a scandal where its engineers allegedly falsified yields figures to customers to score orders, which had a cascading effect on the volumes and competitiveness of their customers. We're inclined to think that Samsung has taken lessons and is more careful with the yields figures being reported in the press. Meanwhile, Intel Foundry Services competes with the Intel 3 node, which is physically 7 nm FinFET, but with electrical characteristics comparable to those of 3 nm.

Lam Research Corp. (Nasdaq: LRCX) today introduced Coronus DX, the industry's first bevel deposition solution optimized to address key manufacturing challenges in next-generation logic, 3D NAND and advanced packaging applications. As semiconductors continue to scale, manufacturing becomes increasingly complex with hundreds of process steps needed to build nanometer-sized devices on a silicon wafer. In a single step, Coronus DX deposits a proprietary layer of protective film on both sides of the wafer edge that helps prevent defects and damage that can often occur during advanced semiconductor manufacturing. This powerful protection increases yield and enables chipmakers to implement new leading-edge processes for the production of next-generation chips. Coronus DX is the newest addition to the Coronus product family and extends Lam's leadership in bevel technology.

"In the era of 3D chipmaking, production is complex and costly," said Sesha Varadarajan, senior vice present of the Global Products Group at Lam Research. "Building on Lam's expertise in bevel innovation, Coronus DX helps drive more predictable manufacturing and significantly higher yield, paving the way for adoption of advanced logic, packaging and 3D NAND production processes that weren't previously feasible."

Accelerating the integration of heterogeneous dies to enable the next level of system scalability and functionality, Synopsys, Inc. (Nasdaq: SNPS) has strengthened its collaboration with TSMC and Ansys for multi-die system design and manufacturing. Synopsys provides the industry's most comprehensive EDA and IP solutions for multi-die systems on TSMC's advanced 7 nm, 5 nm and 3 nm process technologies with support for TSMC 3DFabric technologies and 3Dblox standard. The integration of Synopsys implementation and signoff solutions and Ansys multi-physics analysis technology on TSMC processes allows designers to tackle the biggest challenges of multi-die systems, from early exploration to architecture design with signoff power, signal and thermal integrity analysis.

"Multi-die systems provide a way forward to achieve reduced power and area and higher performance, opening the door to a new era of innovation at the system-level," said Dan Kochpatcharin, head of Design Infrastructure Management Division at TSMC. "Our long-standing collaboration with Open Innovation Platform (OIP) ecosystem partners like Synopsys and Ansys gives mutual customers a faster path to multi-die system success through a full spectrum of best-in-class EDA and IP solutions optimized for our most advanced technologies."

Intel's upcoming Sapphire Rapids processors have faced multiple delays over the past few years. Built on Intel 7 manufacturing process, the CPU is supposed to bring new advances for Intel's clients and significant performance uplifts. However, TrendForce reports that the mass production of Sapphire Rapids processors will be delayed from Q4 of 2022 to the first half of 2023. The reason for this (yet another) delay is that the Sapphire Rapids MCC die is facing a meager yield on Intel 7 manufacturing technology, estimated to be at only 50-60% at the time of writing. Economically, this die-yielding percentage is not profitable for Intel since many dies are turning out to be defective.

This move will stop many OEMs and cloud service providers (CSPs) from rolling out products based on the Sapphire Rapids design and will have to delay it until next year's mass production. On the contrary, AMD is likely to reap the benefits of Intel's delay, and AMD's x86 server market share will jump from 15% in 2022 to 23% in 2023. Given that AMD ships processors with the highest core counts, many companies will opt for AMD's solutions in their data centers. With more companies being concerned by their TCO measures with rising energy costs, favors fall in the hand of single-socket servers.

Back in March there were reports of TSMC's N3E node having been moved from 2024 to the end of 2023. However, it seems like the node is already seeing better than expected yields and is now being pulled in further and TSMC is expecting to start volume production as early as Q2 in 2023. The node does appear to have been frozen when it comes to further development as of the end of March. Yields are said to be much higher than the N3B node, which is also under development, but with limited information available about it.

The first customer for the new node is expected to be Apple, as the company is largely paying for much of the cutting edge node development at TSMC. However, both Intel and Qualcomm are said to be some of the first customers for the new node. More details should hopefully be announced tomorrow during TSMC's first quarter earnings call. The N3E node is a reduced layer EUV process, but before it goes into mass production, it's likely we'll be seeing the N3 node first. Early production of 3 nm parts later this year is expected to be at around 10 to 20k wafers per month initially, rising to about 25 to 35k a month once TSMC's new fab is ready. Once the N3E node is in full swing, the monthly capacity of 3 nm parts should be around 50k wafers a month, but depending on customer demand, it might end up being even higher.

Samsung Electronics is hit by a major scandal involving current and former employees. It's being alleged that these employees are involved in falsifying information about the semiconductor fabrication yields of the company's 3/4/5 nanometer nodes to clear them for commercial activity. This came to light when Samsung was observing lower than expected yields after the nodes were approved for mass-production of logic chips for Samsung, as well as third-party chip-designers. A falsified yield figure can have a cascading impact across the supply-chain, as wafer orders and pricing are decided on the basis of yields. Samsung however, has downplayed the severity of the matter. The group has initiated an investigation into Samsung Device Solutions, the business responsible for the foundry arm of the company. This includes a thorough financial audit of the foundry to investigate if the investments made to improve yields were properly used.

Semiconductor manufacturing is no easy task. Every company in that business knows that, and the hardships of silicon manufacturing have been felt by even the greatest players like Samsung and Intel. Today, according to the latest report from Business Korea, Samsung is again in trouble with its 5 nm node. It has been reported previously that Samsung is struggling with yields of its 5 nm node, however, we didn't know just how much until now. According to the sources over at Business Korea, Samsung's 5 nm semiconductor node is experiencing less than 50% yields. That means, for example, that out of 100 chips manufactured on a single silicon wafer, only half are functional. And that is not good at all.

Usually, for a node to go into high-volume manufacturing (HVM), the yielding rate needs to be around 95%. In case it is not at that level, manufacturing of that node is not very efficient and not very profitable. The V1 Line in Hwaseong, where this Samsung 5 nm is made, uses EUV tools to manufacture the new node. While the yields are currently below 50%, it is expected to improve as Samsung engineers tweak and tune the node and the tools that are running the facility. We can expect to hear more about the yields of this node in the coming months.

In a recent ASUS investor call from March 17th, a company representative explained the company's financial outlook and what it sees as its successes and failures in Q42020. In it, the company referenced the lack of NVIDIA graphics cards to satisfy demand as one of the major hurdles it has had to face. As the company said, "Our guess is that the gap might have been caused by lower yields upstream. As for when [Nvidia] can increase that yield is something hard for us to predict."

This is likely the clearest indicator we've had since NVIDIA's RTX 30-series launch that there is more than a demand problem for NVIDIA's Ampere graphics cards - there's a yield one as well. NVIDIA could have simply failed to predict demand for its graphics cards in wake of the recent cryptomining craze, and asome theorize a miscalculated allocation of wafers with Samsung on expectations of lower demand post-holiday season. That one doesn't make much sense, as by that time, COVID and its effects on tech market demand were already pretty clear. And while NVIDIA certainly doesn't have all available capacity at Samsung's 8 nm at its disposal, there should certainly be more available capacity for NVIDIA's RTX 30-series than say, for AMD's Navi graphics cards, which have to share the 7 nm wafers with virtually all other AMD products (from CPUs to mobile chips to enterprise solutions). The idea of lower upstream yields than would be ideal for NVIDIA does certainly come as a possible reason - a change in foundry partner comes with certain additional difficulties in adapting the design to that given processes' strengths and issues. As always, we'll just have to wait and see.

Today we have found out that Sony has reportedly cut PlayStation 5 launch supply due to bad yields of the SoC powering the console. Previously, we reported that Sony has doubled production of the new console amid high demand, where the company expected to sell 10 million units in the fiscal year. The original plan was to have around 15 million units of the new console available by March 31st, 2021. Sony has been spending a lot of resources to get as many units out to consumers, however, the bad SoC yields have held the company back significantly.

It is reported by Bloomberg that instead of the original 15 million units Sony plans to supply, there will be only 11 million of them. That represents a massive reduction of 4 million units. And you are wondering how bad the yields of the new SoC are to have that big reduction. According to the source, TSMC and Sony are seeing only 50% yields on the production run. It is reported that the yields are gradually improving but have not yet reached the level needed to have a stable supply. This represents a big problem for the company and we don't know who is to blame. TSMC has been very good at manufacturing 7 nm silicon, however, it could be bad design from AMD and Sony that is making the production difficult. We are waiting for more information.

Semiconductor manufacturing is a difficult process. Often when a new node is being developed, there are new materials introduced that may cause some yield issues. Or perhaps with 7 nm and below nodes, they are quite difficult to manufacture due to their size, as the transistor can get damaged by the smallest impurity in silicon. So manufacturers have to be extra careful and must spend more time on the development of new nodes. According to industry sources over at DigiTimes, we have information that Samsung is struggling with its 5 nm EUV node.

This unfortunate news comes after the industry sources of DigiTimes reported that Qualcomm's next-generation 5G chipsets could be affected if Samsung doesn't improve its yields. While there are no specific pieces of information on what is the main cause of bad yields, there could be a plethora of reasons. From anything related to manufacturing equipment to silicon impurities. We don't know yet. We hope that Samsung can sort out these issues in time, so Qualcomm wouldn't need to reserve its orders at rival foundries and port the design to a new process.

3D QLC (quad-level cell) is the latest, manufacture-ready technology to grace the NAND panorama, with promises of increased density over 3D TLC (triple-level cell), thus bringing pricing per GB even lower. However, as with all wafer-based PC components, yields are an extremely important part of that process. Cost reduction can only be attained if manufacturing allows for a given percentage of a wafer to be fully functional and without defects that compromise its feature-set or performance. However, as cell design becomes more complex in a bid to increase areal density, yields have taken longer to mature.

According to DigiTimes, 3D TLC yields have only gotten off the ground in the beginning of this year - right around the time companies were rolling out their 3D QLC designs. And if TLC took longer than expected to achieve respectable yields, it seems that QLC memory will take even longer - we already knew that the Intel-Micron venture on QLC was facing less than 50% yields, but DigiTimes has now extended this struggle to what seems to be the entire NAND manufacturing industry (Samsung Electronics, SK Hynix, Toshiba/ Western Digital and Micron Technology/Intel). The result? Expected price fluctuations in the beginning of 2019, as predicted production volume fails to meet both projected and actual demand, with 3D TLC supplies having to cope with increased market demands.

With Moore's Law being pronounced as within its death throes, historic monolithic die designs are becoming increasingly expensive to manufacture. It's no secret that both AMD and NVIDIA have been exploring an MCM (Multi-Chip-Module) approach towards diverting from monolithic die designs over to a much more manageable, "chiplet" design. Essentially, AMD has achieved this in different ways with its Zen line of CPUs (two CPU modules of four cores each linked via the company's Infinity Fabric interconnect), and their own R9 and Vega graphics cards, which take another approach in packaging memory and the graphics processing die in the same silicon base - an interposer.