Tenstorrent hosted their "Nerds Talking to Nerds About RISC-V" event this week in India where a dozen high profile industry experts hosted technical talks and panels about every facet of the RISC-V landscape and future. Among these are some familiar names to anyone who's been keeping up on the CPU industry; Raja Koduri of his own AI Generative Gaming startup company, Lars Bergstrom of Google, Naveed Sherwani of Rapid Silicon, and of course Jim Keller the CEO of Tenstorrent itself. On the first day of the event a mere 42 minutes into the YouTube live stream during his keynote talk, Jim Keller is providing an overview of Tenstorrent's latest silicon design goals. He presents a slide showing a wide comparison of various competitor's integer performance in SPEC CPU 2017 INT wherein a raw performance value for AMD's yet released "Zen 5" is listed, as well as the operating frequency and TDP of the supposed sample.

The slide shows all of AMD's recent architectures starting with the original "Zen" (Naples) and the improvements each successive generation has made. Also shown is one of Intel's latest "Sapphire Rapids" Xeons, a projected performance point of NVIDIA's in-house CPU architecture "Grace", Amazon's "Graviton" series with a projected result for "Graviton 3," and Tenstorrent's own 8-wide RISC-V architecture as it currently performs in their labs. While all of these are fascinating results in their own right, we're going to narrow in on the "Zen 4" (Genoa) and "Zen 5" results. We can see from the Frequency and TDP charts that "Zen 4" is clocked at 3.8 GHz as it's equal to the Xeon Platinum 8480+ (which itself boosts to 3.8 GHz in light threaded workloads such as this) so is therefore likely a variant of EPYC 9354 or 9454 with its TDP configured at the minimum 240 W. The unnamed "Zen 5" CPU is shown to be running at around 4.0 GHz with the same 240 W TDP, a tiny 5% bump in core clock, while delivering a substantial 30% jump in performance. The most interesting detail here is that nowhere is it listed—as with "Grace" and "Graviton 3"—that this is a projected result.

ASUS IoT, the global AIoT solution provider, today announced the all-new Tinker V—a versatile single-board computer (SBC) powered by a 64-bit RISC-V-based processor, which supports both Linux Debian and Yocto operating systems. Tinker V packs features rich connectivity into a compact Pico-ITX form factor, and pairs assured longevity with reliable support, making it the ideal choice for diverse IoT and gateway applications.

The RISC-V processor in Tinker V employs the open-source Instruction Set Architecture (ISA), based on Reduced Instruction Set (RISC) principles. Compared with traditional x86 and Arm platforms, the defining benefit of RISC-V is that ISA is open source. Both individual developers and enterprises can change, optimize and deploy freely based on the RISC-V architecture—bypassing licensing and copyright fees.

Think Silicon, the leading provider of ultra-low-power GPU IP for embedded systems, will showcase its latest graphics and AI solutions for edge computing devices in Hall 4, Booth 476 at Embedded World 2023 taking place in Nuremberg, Germany from March 14-16. The solutions demonstrate how Think Silicon is meeting the complex needs of ultra-low-power graphics and AI applications in the wearables, smart home, industrial and automotive markets.

Think Silicon's booth will feature the industry's first RISC-V-based GPU - the NEOX IP Series. NEOX represents a new era of smart GPU architectures with programmable compute shaders, running on a real-time operating system (RTOS) and supported by lightweight graphics and machine learning programming frameworks. NEOX serves as a GPU platform addressing a wide variety of vertical markets, including next-generation ultra-low-power smartwatches, augmented reality (AR) eyewear, surveillance and entertainment video, and smart displays for point-of-sale/point-of-interaction terminals.

Yesterday, Intel reported that the company experienced one of the most challenging quarters and year overall revenue results, which led the company's share price to plummet and erase almost 10 billion dollars from its market cap. Amid the economic downtrend, the company is preparing to axe unnecessary developments and research costs that it would get in low-margin markets. Today, this has been reflected in the company's network switch business and the RISC-V pathfinder program. In 2019, the company acquired Barefoot Networks, which ended up in a line of Tofino series of standalone network switches. Apparently, this has been a low-margin or unprofitable business for Intel. "NEX continues to do well and is a core part of our strategic transformation, but we will end future investments in our network switching product line, while still fully supporting existing products and customers," noted Intel CEO Pat Gelsinger, adding, "Since my return, we have exited seven businesses, providing in excess of $1.5 billion in savings". Intel NICs are not affected, and the company's investments in other networking businesses continue.

Additionally, the company is also doing a shutdown of its RISC-V Pathfinder program. Thanks to Yusuke Ohara, who questioned Intel's Pathfinder for RISC-V program support, we have information that the company is discontinuing the program "effective immediately." The support also advises that Intel will not provide additional advancements or bug fixes, so everyone should consult 3rd parties for any software and development.

Back in February 2022 SiFive announced its partnership with Intel Foundry Services (IFS), to bring its "Horse Creek" SoC to market and now SiFive has announced that it's getting ready to launch its first development board on said SoC. This summer, SiFive will launch the HiFive Pro P550 development board, which will kick things up a serious notch when it comes to embedded SoC development boards, regardless of the CPU core the SoC is built around. The HiFive Pro P550 will be one of few microATX based embedded SoC development boards out there and so far, to our knowledge, the only one with a RISC-V based SoC. The Horse Creek SoC sports quad core, 2.2 GHz, 13-stage, triple-issue, out-of-order pipeline RISC-V RV64GBC CPU built on the Intel 4 node. The SoC also has a DDR5 5600 MHz memory interface, support for eight lanes of PCIe 5.0 and comes in a 19 x 19 mm FBGA package.

The HiFive Pro P550 will offer 16 GB of DDR5 memory, but based on the render of the motherboard, this is soldered to the board, rather than relying on standard DDR5 DIMMs. Furthermore, the board has two x16 PCIe 3.0 expansion slots, although it's unclear how many PCIe each slot features, as well as a PCIe 3.0 M.2 2280 M-key slot for NVMe SSDs and a PCIe 3.0 M.2 E-key slot for a WiFi/Bluetooth module. The board also sports multiple USB/USB 3.0 ports and even a pair of USB-C ports. The press release also mentions both Gigabit and 10 Gbps Ethernet support, as well as support for onboard graphics and remote system management, without going into any further details. It'll be interesting to see if the Horse Creek SoC can deliver on its expected performance target, especially as SiFive has a lot to prove, especially as the company calls the RISC-V architecture inevitable.

Ventana Micro Systems Inc. today announced its Veyron family of high performance RISC-V processors. The Veyron V1 is the first member of the family, and the highest performance RISC-V processor available today. It will be offered in the form of high performance chiplets and IP. Ventana Founder and CEO Balaji Baktha will make the public announcement during his RISC-V Summit keynote today.

The Veyron V1 is the first RISC-V processor to provide single thread performance that is competitive with the latest incumbent processors for Data Center, Automotive, 5G, AI, and Client applications. The Veyron V1 efficient microarchitecture also enables the highest single socket performance among competing architectures.

Phison Electronics Corp., a global leader in NAND flash and storage solutions, announced today that its 8 TB M.2 2280 SSD solution has completed flight qualification tests required for Lonestar Data Holdings' historic first lunar data center mission. This SSD has been selected by Lonestar's contractor and Phison's partner, space logistics company Skycorp. Skycorp is also Lonestar's engineering design and manufacturing partner for the lunar data center mission scheduled for the second half of 2023.

"After comprehensive testing and certification process, Phison is thrilled that our SSD technology has passed all the rigorous requirements for Lonestar's upcoming Moon mission," said K.S. Pua, Phison CEO. "We are excited about playing a vital role on this important mission, and other future ones as we continue our foray into the new frontier. We also want to thank our outstanding customer, Lonestar, and partner, Skycorp, for helping to make this happen."

Today, at Linley Fall Processor Conference 2022, Andes Technology, a leading provider of high efficiency, low power 32/64-bit RISC-V processor cores and founding premier member of RISC-V International, reveals its top-of-the-line AndesCore AX60 series of power and area efficient out-of-order 64-bit processors. The family of processors are intended to run heavy-duty OS and applications with compute intensive requirements such as advanced driver-assistance systems (ADAS), artificial intelligence (AI), augmented/virtual reality (AR/VR), datacenter accelerators, 5G infrastructure, high-speed networking, and enterprise storage.

The first member of the AX60 series, the AX65, supports the latest RISC-V architecture extensions such as the scalar cryptography extension and bit manipulation extension. It is a 4-way superscalar with Out-of-Order (OoO) execution in a 13-stage pipeline. It fetches 4 to 8 instructions per cycle guided by highly accurate TAGE branch predictor with loop prediction to ensure fetch efficiency. It then decodes, renames and dispatches up to 4 instructions into 8 execution units, including 4 integer units, 2 full load/store units, and 2 floating-point units. Besides the load/store units, the AX65's aggressive memory subsystem also includes split 2-level TLBs with multiple concurrent table walkers and up to 64 outstanding load/store instructions.

SiFive, Inc. the founder and leader of RISC-V computing, today announced two new products that address the need for high performance and efficiency in a small size in high volume applications like wearables, smart home, industrial automation, AR/VR, and other consumer devices. The SiFive Performance P670 and P470 RISC-V processors bring unparalleled compute performance and efficiency that is significantly raising the bar for innovative designs in these high-volume markets. The modern and innovative SiFive design methodologies bring raw compute density that is a substantial advantage for SiFive Performance products and also translates into significant cost savings for customers.

"The P670 and P470 are specifically designed for, and capable of handling the most demanding workloads for wearables and other advanced consumer applications. These new products offer powerful performance and compute density for companies looking to upgrade from legacy ISAs," said Chris Jones, SiFive VP of Product. "We have optimized these new RISC-V Vector enabled products to deliver the performance and efficiency improvements the industry has long been asking for, and we are in evaluations with a number of top-tier customers. Additionally, as the upstream enablement of RISC-V has started within the Android Open Source Project, (AOSP), designers will have unrivaled choice and flexibility as they consider the positive implications with that platform for future designs."

In December of 2021, we covered the appearance of Russia's home-grown Baikal-S processor, which has 48 cores based on Arm Cortex-A75 cores. Today, thanks to the famous chip photographer Fritzchens Fritz, we have the first die shows that show us exactly how Baikal-S SoC is structured internally and what it is made up of. Manufactured on TSMC's 16 nm process, the Baikal-S BE-S1000 design features 48 Arm Cortex-A75 cores running at a 2.0 GHz base and a 2.5 GHz boost frequency. With a TDP of 120 Watts, the design seems efficient, and the Russian company promises performance comparable to Intel Skylake Xeons or Zen1-based AMD EPYC processors. It also uses a home-grown RISC-V core for management and controlling secure boot sequences.

Below, you can see the die shots taken by Fritzchens Fritz and annotated details by Twitter user Locuza that marked the entire SoC. Besides the core clusters, we see that a slum of cache connects everything, with six 72-bit DDR4-3200 PHYs and memory controllers surrounding everything. This model features a pretty good selection of I/O for a server CPU, as there are five PCIe 4.0 x16 (4x4) interfaces, with three supporting CCIX 1.0. You can check out more pictures below and see the annotations for yourself.

According to Dylan Patel of SemiAnalysis sources, Apple is moving its embedded cores from Arm to RISC-V. In Apple's Silicon designs, there are far more cores than the main ones that power the operating system and end-user applications. For example, embedded cores are present, and there are 30+ in M1 SoCs responsible for all kinds of workloads not related to the operating system. These tasks are usually associated with other functions such as WiFi/BlueTooth, ThunderBolt retiming, touchpad control, NAND chips having their own core, etc. They run their own firmware and power everything around the central cores that run the OS, so the whole SoC functions appropriately.

It appears that a lot of these cores are based on Arm M-series or lower-end A-series IP that Apple is currently looking to replace with RISC-V. Given that a large portion of software runs on the main big.LITTLE configuration, other secondary SoC tasks can migrate to a different ISA like RISC-V, with a small firmware adjustment. Given that these cores can be placed with custom IPs, Apple would save licensing fees if custom RISC-V cores were used. Additionally, developing firmware for these cores at an Apple engineering team size shouldn't be a problem. Of course, we have no information about when these custom cores will appear inside Apple Silicon. Even when they are used, no formal announcement is expected given that the main cores remain to be powered by Arm ISA, with everything else invisible to the end-user.

SiFive, Inc., the founder and leader of RISC-V computing, today announced it has been selected by NASA to provide the core CPU for NASA's next generation High-Performance Spaceflight Computing (HPSC) processor. HPSC is expected to be used in virtually every future space mission, from planetary exploration to lunar and Mars surface missions. HPSC will utilize an 8-core, SiFive Intelligence X280 RISC-V vector core, as well as four additional SiFive RISC-V cores, to deliver 100x the computational capability of today's space computers. This massive increase in computing performance will help usher in new possibilities for a variety of mission elements such as autonomous rovers, vision processing, space flight, guidance systems, communications, and other applications.

"As the leading RISC-V, U.S. based, semiconductor company we are very proud to be selected by the premier world space agency to power their most mission critical applications," said Jack Kang, SVP Business Development, SiFive. "The X280 demonstrates orders of magnitude performance gains over competing processor technology and our SiFive RISC-V IP allows NASA to take advantage of the support, flexibility, and long-term viability of the fast-growing global RISC-V ecosystem. We've always said that with SiFive the future has no limits, and we're excited to see the impact of our innovations extend well beyond our planet."

MIPS, a leading developer of highly scalable RISC processor IP, announced it is working with Intel to accelerate innovation in open computing. As part of this effort, MIPS' eVocore is being incorporated into the new Intel Pathfinder for RISC-V, a platform designed to deliver new capabilities for pre-silicon development. Intel Pathfinder allows new ways for System-on-a-Chip (SoC) architects and system software developers to define new products and pursue pre-silicon software development on RISC-V.

"MIPS is thrilled to be part of the Intel Pathfinder for RISC-V platform, providing high performance cores with support for multi-cluster, multi-core and multi-threading to accelerate innovation," said Desi Banatao, MIPS CEO. "These multiprocessors have unique features and a high level of scalability that make them ideal for compute-intensive tasks across a broad range of markets and applications."

The UEFI Forum today announced the release of the Unified Extensible Firmware Interface (UEFI) 2.10 specification and Advanced Configuration and Power Interface (ACPI) 6.5 specification. The new specification versions expand support for new processor types, memory interfaces and platform types, while allowing for crypto agility in post-quantum system security.

"We are excited to share the new Conformance Profiles feature, responsive to community pull for a way to make the UEFI Forum's work useful," said Mark Doran, UEFI Forum President. "The Conformance Profiles feature will expand the platform types UEFI can support to an ever wider range of platform types like IoT, embedded and automotive spaces - beyond general purpose computers."

DeepComputing and Xcalibyte today opened pre-orders for the industry's first native RISC-V development laptop. The hotly anticipated ROMA development platform features an unannounced quad-core RISC-V processor with a companion NPU/GPU for the fastest, seamless RISC-V native software development available.

"Native RISC-V compile is a major milestone," said Mark Himelstein, Chief Technology Officer for RISC-V International. "The ROMA platform will benefit developers who want to test their software running natively on RISC-V. And it should be easy to transfer code developed on this platform to embedded systems."

Headquartered in Aachen and emerging from stealth mode in May, MachineWare is set to revolutionize semiconductor design with its high-speed functional RISC-V simulator, SIM-V. SIM-V, the company's flagship product, combines unprecedented simulation performance with exceptional customizability for applications ranging from the tiniest embedded devices to warehouse-scale supercomputers. SIM-V enables software developers to test full software stacks - including firmware, operating system kernel and complex user-space applications, such as (Java-) virtual machines or rich graphical environments - in real time.

Today's hardware-software systems are becoming increasingly complex, with even tiny edge systems executing millions of lines of code. SIM-V gives software developers the ability to interactively debug even the most complex designs without the need for physical hardware, even before first prototypes are available. Integrating SIM-V into continuous integration systems minimizes test execution times, saves compute resources and allows developers to continue their work sooner.

Imagination Technologies announces IMG RTXM-2200, its first real-time embedded RISC-V CPU, a highly scalable, feature-rich, 32-bit embedded solution with a flexible design for a wide range of high-volume devices. IMG RTXM-2200 is one of the first commercial cores in Imagination's Catapult CPU family, previously announced in December 2021. Accelerating the expansion of its RISC-V offering, Imagination's IMG RTXM-2200 can be integrated into complex SoCs for a range of applications including networking solutions, packet management, storage controllers, and sensor management for AI cameras and smart metering. Together with its market-leading GPU and AI accelerator IP, Imagination's new CPU cores offer customers access to innovative heterogeneous solutions.

This real-time embedded core features up to 128 KB of tightly coupled memories (both instruction and data) for deterministic response and Level 1 cache sizes of up to 128 KB for robust performance. The new CPU offers a range of floating-point formats including single-precision and bfloat16. The latter enables manufacturers to deploy AI applications through this core without the need for an additional chip. This reduces silicon area, for a cost-effective and optimised design in AI cameras and smart metering applications.

SiFive Inc., the founder and leader of RISC-V computing, today announced the release of the latest version of its SiFive Intelligence X280 processor, which introduces significant new features including scalability up to a 16-core cache-coherent complex, WorldGuard trusted protection, and a new interface allowing for seamless integration between the X280 vector unit and customer-designed external AI accelerators or other coprocessors, called VCIX (Vector Coprocessor Interface eXtension). Collectively, these enhanced features deliver unmatched scalability, security, and interoperability to the SiFive X280, the most widely adopted implementation of the RISC-V Vector extension. This latest version of the X280 is a powerful solution for those looking for alternatives to legacy SIMD-style architectures.

Publicly available since April 2021, the SiFive Intelligence X280 has seen rapid adoption as customers gravitate towards its unique combination of performance, power efficiency, and an intuitive programming model. The X280 has claimed double-digit design wins in the past six months alone, in a wide variety of data-driven applications, including AI inference, image processing, datacenter acceleration, and automotive use cases.

Researchers from Università di Bologna and CINECA, the largest supercomputing center in Italy, have been playing with the concept of developing a RISC-V supercomputer. The team has laid the grounds for the first-ever implementation that demonstrates the capability of the relatively novel ISA to run high-performance computing. To create a supercomputer, you need pieces of hardware that seem like Lego building blocks. Those are called clusters, made from a motherboard, processor, memory, and storage. Italian researchers decided to try and use something different than Intel/AMD solution to the problem and use a processor based on RISC-V ISA. Using SiFive's Freedom U740 SoC as the base, researchers named their RISC-V cluster "Monte Cimone."

Monte Cimone features four dual-board servers, each in a 1U form factor. Each board has a SiFive's Freedom U740 SoC with four U74 cores running up to 1.4 GHz and one S7 management core. In total, eight nodes combine for a total of 32 RISC-V cores. Paired with 16 GB of 64-bit DDR4 memory operating at 1866s MT/s, PCIe Gen 3 x8 bus running at 7.8 GB/s, one gigabit Ethernet port, USB 3.2 Gen 1 interfaces, the system is powered by two 250 Watt PSUs to support future expansion and addition of accelerator cards.

During the International Supercomputing Conference on May 31, 2022, in Hamburg, Germany, Jeff McVeigh, vice president and general manager of the Super Compute Group at Intel Corporation, announced Rialto Bridge, Intel's data center graphics processing unit (GPU). Using the same architecture as the Intel data center GPU Ponte Vecchio and combining enhanced tiles with Intel's next process node, Rialto Bridge will offer up to 160 Xe cores, more FLOPs, more I/O bandwidth and higher TDP limits for significantly increased density, performance and efficiency.

"As we embark on the exascale era and sprint towards zettascale, the technology industry's contribution to global carbon emissions is also growing. It has been estimated that by 2030, between 3% and 7% of global energy production will be consumed by data centers, with computing infrastructure being a top driver of new electricity use," said Jeff McVeigh, vice president and general manager of the Super Compute Group at Intel Corporation.

SiFive, Inc., the founder and leader of RISC-V computing, today announced it has raised $175 million in a Series F financing round, valuing the company at over $2.5 billion. The Series F round was led by Coatue Management, a global technology investment firm that invests in companies at all stages - from venture to growth through public markets. SiFive is substantially accelerating the development of the company's RISC-V products, future roadmap, and ecosystem to achieve the unlimited potential that RISC-V has for SiFive's customers and partners.

Founded six years ago by the inventors of RISC-V, SiFive introduced the world to the open standard ISA and transformed the future of compute. Today, RISC-V is firmly established as one of the major global compute platforms, with adoption all around the world, as evidenced by recent industry announcements including the Intel $1B innovation fund, featuring a goal of catalyzing the RISC-V ecosystem. SiFive has design wins with more than 100 customers including several of the world's largest hyperscale companies and 8 of the top 10 semiconductor companies, in applications ranging from automotive, AR/VR, client computing, data center, and intelligent edge.

SiFive, Inc., the founder and leader of RISC-V computing, today announced the company will support Intel Foundry Services (IFS) innovation fund's goal to build innovative new RISC-V computing platforms optimized for Intel process technology. The $1B Intel fund will support the creation of disruptive technologies to address modern computing challenges, with the Intel-SiFive collaboration aiming to extend the RISC-V ecosystem. Compute blocks in future silicon chips, optimized for specific classes of workloads, require a vibrant market of semiconductor IP that is further enabled by SiFive's leading RISC-V processor IP optimized and available to customers of IFS. The open nature of the RISC-V instruction set architecture creates freedom to innovate, with specifications and extensions developed by expert contributors from leaders in the semiconductor industry, research institutions, and academia.

SiFive has partnered with IFS to develop a RISC-V development platform, codenamed "Horse Creek," featuring a multi-core SiFive Performance P550 processor, and implemented on the Intel 4 technology platform, on track for availability in 2022. The "Horse Creek" SoC will enable a new generation of RISC-V developer boards, continuing the tradition of SiFive HiFive boards that have helped drive the growth of the RISC-V ecosystem. To be informed of updates on the "Horse Creek" RISC-V developer board, please register here.

As part of its IDM 2.0 (Integrated Device Manufacturer) plan, Intel has announced it has setup a $1 Billion fund to support early-stage startups and established companies building disruptive technologies for the foundry ecosystem. A collaboration between Intel Capital and Intel Foundry Services (IFS), the move aims to capitalize on what Intel sees as the future of the industry: with a focus on an Open Chiplet platform and Open Interconnect Standard, Intel is looking to enable partners to deploy packaging technologies that bring together multiple ISAs (Instruction Set Architectures) within the same chip. The idea is simple: customers will be looking to mix and match several IPs on their semiconductor designs, taking advantage of different strengths (particularly in the power/performance/area equation) from each.

Foundry customers are rapidly embracing a modular design approach to differentiate their products and accelerate time to market. Intel Foundry Services is well-positioned to lead this major industry inflection. With our new investment fund and open chiplet platform, we can help drive the ecosystem to develop disruptive technologies across the full spectrum of chip architectures.

Pat Gelsinger, Intel CEO

The European High Performance Computing Joint Undertaking (EuroHPC JU) has launched 3 new research and innovation projects. The projects aim to bring the EU and its partners in the EuroHPC JU closer to developing independent microprocessor and HPC technology and advance a sovereign European HPC ecosystem. The European Processor Initiative (EPI SGA2), The European PILOT and the European Pilot for Exascale (EUPEX) are interlinked projects and an important milestone towards a more autonomous European supply chain for digital technologies and specifically HPC.

With joint investments of €140 million from the European Union (EU) and the EuroHPC JU Participating States, the three projects will carry out research and innovation activities to contribute to the overarching goal of securing European autonomy and sovereignty in HPC components and technologies, especially in anticipation of the European exascale supercomputers.

In 2016, NVIDIA announced that the company is working on replacing its Fast Logic Controller processor codenamed Falcon with a new GPU System Processor (GSP) solution based on RISC-V Instruction Set Architecture (ISA). This novel RISC-V processor is codenamed NV-RISCV and has been used as GPU's controller core, coordinating everything in the massive pool of GPU cores. Today, NVIDIA has decided to open this NV-RISCV CPU to a broader spectrum of applications starting with 510.39 drivers. According to the NVIDIA documents, this is only available in the select GPUs for now, mainly data-centric Tesla accelerators.

NVIDIA DocumentsSome GPUs include a GPU System Processor (GSP) which can be used to offload GPU initialization and management tasks. This processor is driven by the firmware file /lib/firmware/nvidia/510.39.01/gsp.bin. A few select products currently use GSP by default, and more products will take advantage of GSP in future driver releases.
Offloading tasks which were traditionally performed by the driver on the CPU can improve performance due to lower latency access to GPU hardware internals.