Amid the US sanctions, Chinese technology giant Huawei has reportedly developed tools to create processors with 14 nm and above lithography. According to Chinese media Yicai, Huawei and its semiconductor partners have teamed up to create replacement tools in place of US chip toolmakers like Cadence, Synopsys, and Mentor/Siemens. These three companies control all of the world's Electronic Design Automation (EDA) tools used for every step of chip design, from architecture to placement and routing to the final physical layout. Many steps need to be taken before making a tapeout of a physical chip, and Huawei's newly developed EDA tools will help the Chinese industry with US sanctions which crippled Huawei for a long time.

Having no access to US-made chipmaking tools, Huawei has invested substantial time into making these EDA tools. However, with competing EDA makers supporting lithography way below 14 nm, Huawei's job still needs to be completed. Chinese semiconductor factories are currently capable of 7 nm chip production, and Huawei itself is working on making a sub-7 nm EUV scanner to aid manufacturing goals and compete with the latest from TSMC and other. If Huawei can create EUV scanners that can achieve transistor sizes smaller than 7 nm, we expect to see their EDA tools keep pace as well. It is only a matter of time before they announce adaptation for smaller nodes.

NVIDIA today announced a breakthrough that brings accelerated computing to the field of computational lithography, enabling semiconductor leaders like ASML, TSMC and Synopsys to accelerate the design and manufacturing of next-generation chips, just as current production processes are nearing the limits of what physics makes possible.

The new NVIDIA cuLitho software library for computational lithography is being integrated by TSMC, the world's leading foundry, as well as electronic design automation leader Synopsys into their software, manufacturing processes and systems for the latest-generation NVIDIA Hopper architecture GPUs. Equipment maker ASML is working closely with NVIDIA on GPUs and cuLitho, and is planning to integrate support for GPUs into all of its computational lithography software products.

The US Government has instituted a ban on supply of GAA-FET EDA software to China (the Chinese government and companies in China). Humans can no longer design every single circuit on chips with tens of billions of transistors, and so EDA (electronics design automation) software is used to micromanage design based broadly on what chip architects want. Synopsys, Cadence, and Siemens are major EDA software suppliers. Intel is rumored to use an in-house EDA software that it doesn't sell, although this could change with the company roping in third-party foundries, such as TSMC, for cutting-edge logic chips (which will need the software to make sense of Intel's designs).

GAA or "gates-all-around" technology is vital to building transistors in the 3 nm and 2 nm silicon fabrication nodes. Samsung is already using GAA for its 3 nm node, while TSMC intends to use it with its 2N (2 nm) node. Intel is expected to use it with its Intel 20A (20 angstrom, or 2 nanometers) node. Both Intel and TSMC will debut nodes powered by GAAFETs for mass-production in 2024. The US Government has already banned the sales of EUV lithography machines to China, as well as machines fabricating 3D NAND flash chips with greater than 128 layers or 14 nm. In the past, technology embargoes have totally stopped China from copying or reverse-engineering western tech, or luring Taiwanese engineers armed with industry secrets away on the promise of wealth and a comfortable life in the Mainland.

Samsung Electronics, the world leader in semiconductor technology, today announced that it has started initial production of its 3-nanometer (nm) process node applying Gate-All-Around (GAA) transistor architecture. Multi-Bridge-Channel FET (MBCFET), Samsung's GAA technology implemented for the first time ever, defies the performance limitations of FinFET, improving power efficiency by reducing the supply voltage level, while also enhancing performance by increasing drive current capability. Samsung is starting the first application of the nanosheet transistor with semiconductor chips for high performance, low power computing application and plans to expand to mobile processors.

"Samsung has grown rapidly as we continue to demonstrate leadership in applying next-generation technologies to manufacturing, such as foundry industry's first High-K Metal Gate, FinFET, as well as EUV. We seek to continue this leadership with the world's first 3 nm process with the MBCFET," said Dr. Siyoung Choi, President and Head of Foundry Business at Samsung Electronics. "We will continue active innovation in competitive technology development and build processes that help expedite achieving maturity of technology."

Addressing increasing performance requirements for artificial intelligence (AI) systems on chip (SoCs), Synopsys, Inc. today announced its new neural processing unit (NPU) IP and toolchain that delivers the industry's highest performance and support for the latest, most complex neural network models. Synopsys DesignWare ARC NPX6 and NPX6FS NPU IP address the demands of real-time compute with ultra-low power consumption for AI applications. To accelerate application software development for the ARC NPX6 NPU IP, the new DesignWare ARC MetaWare MX Development Toolkit provides a comprehensive compilation environment with automatic neural network algorithm partitioning to maximize resource utilization.

"Based on our seamless experience integrating the Synopsys DesignWare ARC EV Processor IP into our successful NU4000 multi-core SoC, we have selected the new ARC NPX6 NPU IP to further strengthen the AI processing capabilities and efficiency of our products when executing the latest neural network models," said Dor Zepeniuk, CTO at Inuitive, a designer of powerful 3D and vision processors for advanced robotics, drones, augmented reality/virtual reality (AR/VR) devices and other edge AI and embedded vision applications. "In addition, the easy-to-use ARC MetaWare tools help us take maximum advantage of the processor hardware resources, ultimately helping us to meet our performance and time-to-market targets."

JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, today announced the publication of the next version of its High Bandwidth Memory (HBM) DRAM standard: JESD238 HBM3, available for download from the JEDEC website. HBM3 is an innovative approach to raising the data processing rate used in applications where higher bandwidth, lower power consumption and capacity per area are essential to a solution's market success, including graphics processing and high-performance computing and servers.

Synopsys, Inc. today announced the industry's first complete HBM3 IP solution, including controller, PHY, and verification IP for 2.5D multi-die package systems. HBM3 technology helps designers meet essential high-bandwidth and low-power memory requirements for system-on-chip (SoC) designs targeting high-performance computing, AI and graphics applications. Synopsys' DesignWare HBM3 Controller and PHY IP, built on silicon-proven HBM2E IP, leverage Synopsys' interposer expertise to provide a low-risk solution that enables high memory bandwidth at up to 921 GB/s.

The Synopsys verification solution, including Verification IP with built-in coverage and verification plans, off-the-shelf HBM3 memory models for ZeBu emulation, and HAPS prototyping system, accelerates verification from HBM3 IP to SoCs. To accelerate development of HBM3 system designs, Synopsys' 3DIC Compiler multi-die design platform provides a fully integrated architectural exploration, implementation and system-level analysis solution.

The U.S. Department of Defense, through the NSTXL consortium-based S2MARTS OTA, has awarded Intel an agreement to provide commercial foundry services in the first phase of its multi-phase Rapid Assured Microelectronics Prototypes - Commercial (RAMP-C) program. The RAMP-C program was created to facilitate the use of a U.S.-based commercial semiconductor foundry ecosystem to fabricate the assured leading-edge custom and integrated circuits and commercial products required for critical Department of Defense systems. Intel Foundry Services, Intel's dedicated foundry business launched this year, will lead the work.

"One of the most profound lessons of the past year is the strategic importance of semiconductors, and the value to the United States of having a strong domestic semiconductor industry. Intel is the sole American company both designing and manufacturing logic semiconductors at the leading edge of technology. When we launched Intel Foundry Services earlier this year, we were excited to have the opportunity to make our capabilities available to a wider range of partners, including in the U.S. government, and it is great to see that potential being fulfilled through programs like RAMP-C." -Pat Gelsinger, Intel CEO.

Synopsys, Inc. today announced the industry's first complete IP solution for the PCI Express (PCIe ) 6.0 technology that includes controller, PHY and verification IP, enabling early development of PCIe 6.0 system-on-chip (SoC) designs. Built on Synopsys' widely deployed and silicon-proven DesignWare IP for PCIe 5.0, the new DesignWare IP for PCIe 6.0 supports the latest features in the standard specification including, 64 GT/s PAM-4 signaling, FLIT mode and L0p power state. Synopsys' complete IP solution addresses evolving latency, bandwidth and power-efficiency requirements of high-performance computing, AI and storage SoCs.

To achieve the lowest latency with maximum throughput for all transfer sizes, the DesignWare Controller for PCI Express 6.0 utilizes a MultiStream architecture, delivering up to 2X the performance of a single-stream design. The Controller, with available 1024-bit architecture, allows designers to achieve 64 GT/s x16 bandwidth while closing timing at 1 GHz. In addition, the controller provides optimal flow with multiple data sources and in multi-virtual channel implementations. To facilitate accelerated testbench development with built-in verification plan, sequences and functional coverage, the VC Verification IP for PCIe uses native SystemVerilog/UVM architecture that can be integrated, configured and customized with minimal effort.

GLOBALFOUNDRIES (GF ) today announced the release and distribution of OpenAccess iPDK libraries optimized for its 22FDX (22nm FD-SOI) platform. With its best-in-class performance, power consumption, and broad feature integration capability, GF's differentiated 22FDX platform is the solution of choice for designers and innovators working in 5G mmWave, edge AI, Internet of Things (IoT), automotive, satellite communications, security, and other applications.

The open-standard based iPDK offers the same level of functionality and performance as PDKs designed for specific vendor tools, while helping enable interoperability and compatibility among different design tool suites. Tools including: the Custom Compiler solution from Synopsys; TannerTM software solutions from Mentor, a Siemens business; PathWave Advanced Design System (ADS) from Keysight Technologies; and any other tool supporting OpenAccess will now be able to use GF iPDK libraries for its 22FDX platform. GF's iPDK will consist of OpenAccess technology files, symbols, component description format (CDF), TCL callbacks, netlisting information, and PyCells.

The 22FDX iPDK is released and available alongside other EDA-specific 22FDX PDK bundles.

Micron Technology, Inc., today announced a comprehensive enablement program which will provide early access to technical resources, products and ecosystem partners. The Technology Enablement Program will aid in the design, development and qualification of next-generation computing platforms that use DDR5, the most technologically advanced DRAM available.

Today's news builds on Micron's January announcement of DDR5 RDIMM samples and brings the industry one step closer to unlocking the value in next-generation, data-centric applications. Companies joining Micron in the DDR5 Technology Enablement Program include Cadence, Montage, Rambus, Renesas and Synopsys.

Today Starblaze announced the availability of the STAR1000P NVMe solid state drive (SSD) controller for high-end client and entry-level enterprise applications. Performance optimizations enable the new controller to achieve sequential reads at 3.6GB/second and sequential writes at 3.2GB/second, up to 50% higher than Starblaze's previous generation controller, STAR1000. The STAR1000P achieves random reads at 750K input/output operations per second (IOPS) and random writes at 600K IOPS, up to 120% higher than Starblaze's STAR1000. The STAR1000P features PCIe Gen3x4, NVMe 1.3 and eight flash channels to support up to 32 terabytes (TB) of storage. The STAR1000P also incorporates a multicore implementation of Synopsys' DesignWare ARC HS38 processor, taking advantage of ARC's extensible architecture with custom instructions that improve scheduling efficiency.

"Enterprise SSD applications need increasing processor performance to support much higher throughput with reduced latency," said John Koeter, vice president of marketing for IP at Synopsys. "Synopsys' ARC HS processors deliver the scalability that Starblaze needs to extend the performance of their STAR1000P platform for the rapidly evolving SSD controller market."

GLOBALFOUNDRIES today announced the establishment of Avera Semiconductor LLC, a wholly owned subsidiary dedicated to providing custom silicon solutions for a broad range of applications. Avera Semi will leverage deep ties with GF to deliver ASIC offerings on 14/12nm and more mature technologies while providing clients new capabilities and access to alternate foundry processes at 7nm and beyond.

Avera Semi is built upon an unrivaled legacy of ASIC expertise, tapping into a world-class team that has executed more than 2,000 complex designs in its 25-year history. With more than 850 employees, annual revenues in excess of $500 million, and over $3 billion in 14nm designs in execution, Avera Semi is well positioned to serve clients developing products across a wide range of markets, including wired and wireless networking, data centers and storage, artificial intelligence and machine learning, and aerospace and defense.

Synopsys has successfully carried out the world's first USB 3.2 demonstration. The host system was running on a Windows 10 operating system with the standard USB drivers without any modifications whatsoever. The USB 3.2 host controller was implemented on a HAPS-80 FPGA platform connected to the PHY board through a Type-C connector. The target system, which ran on Linux, used an identical hardware setup as the host system with the exception that it was configured as a Mass Storage device. The PHY employed in the demonstration was manufactured on the FinFET process and capable of operating at speeds up to 10 Gbps per lane. Therefore, Synopsys's solution consisted of pairing both lanes to achieve a combined throughput of 20 Gbps. The company also emphasized the fact that USB 3.2 doesn't require the use of special cables. For the demonstration, they utilized a pair of conventional Belkin USB 3.1 Type-C cables that you can find at your local Target store.

Micron Technology, Inc., today announced XTRMFlash memory, a faster NOR flash solution designed to revolutionize the way the electronics industry develops systems to meet the demand for "instant-on" performance and fast system responsiveness in automotive, industrial and consumer applications. Utilizing its new, low pin count interface that uses as little as 11 active signals, Micron's XTRMFlash memory outperforms other industry NOR Flash while also significantly reducing pin counts by as much as 75 percent from those found in Parallel NOR flash available in the market today. XTRMFlash memory provides system designers the ideal and fastest possible direct code execution NOR flash memory solution available to enable high-performance, yet small form-factor designs.

"Micron is committed to continued innovation in NOR flash memory," said Richard De Caro, director of NOR Flash for Micron's Embedded Business Unit. "We worked closely with our ecosystem partners and customers to understand their next-generation requirements for high-performance memory, and we have developed XTRMFlash memory as a result. XTRMFlash memory and the XTRMFlash interface have the potential to dramatically change the paradigm of the existing memory landscape by enabling a new category of high-performance and low pin count memory devices that can also extend beyond NOR Flash."

Synopsys, Inc., a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced that it has collaborated with TSMC to provide support for voltage-dependent design rules in TSMC's 16-nm Custom Design Reference Flow. As part of TSMC's custom design infrastructure, TSMC has also certified Synopsys' Laker custom design solution and circuit simulation tools that deliver new capabilities for TSMC V0.5 16-nm FinFET process layout design rules, device models, and electromigration and IR-drop (EM/IR) analysis. TSMC and Synopsys will continue to collaborate on certification of the Synopsys tool set until 16 nm FinFET reaches V1.0.

"TSMC works with Synopsys to ensure our customers have access to analog and mixed-signal design tools for TSMC's 16-nanometer FinFET process," said Suk Lee, senior director of design infrastructure marketing at TSMC. "The Custom Design Reference Flow is another milestone of the long term collaboration between the two companies."

Synopsys, Inc., a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced TSMC's certification of Synopsys' Laker custom design solution for the TSMC 16-nanometer (nm) FinFET process Design Rule Manual (DRM) V0.5 as well as the availability of a 16-nm interoperable process design kit (iPDK) from TSMC.

With its robust support for the iPDK standard, Synopsys' Laker custom design solution provides users with access to a wide range of TSMC process technologies, from 180-nm to 16-nm. Along with support for the TSMC 16-nm V0.5 iPDK, the Laker tool has been enhanced to enable full use of FinFET technology.

Synopsys, Inc., a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced the delivery of lithography compliance checking technology for the TSMC 20-nanometer (nm) DFM Data Kit (DDK) encapsulated with Synopsys Proteus mask synthesis technologies. As a result of the design-for-manufacturing collaboration between TSMC and Synopsys, the compliance checking engine in the DDK helps designers identify lithography-related problems early in the design development phase, avoid litho-related manufacturing issues and late-stage schedule slips resulting from re-design.

The TSMC 20-nm DDK complements traditional physical verification rules with a highly accurate simulation-based solution to identify design non-compliance using a direct simulation of the manufacturing process. Lithography correction and verification tools used in the manufacturing mask synthesis flow are embedded in the DDK, resulting in accurate hotspot detection to avoid litho-related manufacturing issues.

Synopsys, Inc., a global leader accelerating innovation in the design, verification and manufacture of chips and systems, today announced 20-nanometer (nm) process technology support for the TSMC 20 nm Reference flow. This includes Synopsys Galaxy Implementation Platform support for the latest TSMC 20 nm design rules and models. The collaboration between TSMC and Synopsys on 20nm technology allows designers to gain performance, power efficiency and chip density advantages while achieving predictable design closure with the industry-proven Synopsys RTL to GDSII solution.

TSMC's 20 nm Reference Flow addresses 20 nm design challenges with a transparent double patterning aware design flow enabling double patterning technology (DPT) compliance, pre-coloring capability, new RC extraction methodology, DPT sign-off, and integrated design-for-manufacturing (DFM). The new Reference Flow's transparent DPT enablement reduces DPT design complexity, achieves required accuracy, minimizes 20 nm design flow setup and learning curve, and accelerates 20 nm process adoption.

Synopsys, Inc., a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced a multi-year agreement to provide Advanced Micro Devices, Inc. (AMD) with its next-generation Discovery Verification IP (VIP). Based on the new VIPER architecture, the recently announced Discovery VIP family provides inherent performance, ease-of-use and extensibility to speed and simplify verification of the most complex system-on-chip (SoC) designs. This agreement covers a variety of VIP titles including USB 3.0, ARM AMBA AXI interconnect, SATA 3.0, PCI Express Gen 3, and MIPI, as well as Synopsys' Protocol Analyzer, a unique protocol-aware SoC debug environment.

"In our verification environment for Southbridge SoCs and IP cores, we utilize several interfaces, including AXI3 and USB 3.0. After an extensive evaluation, we selected Synopsys' next-generation Discovery VIP for several of our leading SoC designs," said Thomas Bodmer, manager of design engineering at AMD. "With Discovery VIP, we have seen benefits in minimizing our simulation runs and achieving higher coverage. We have used Synopsys' Protocol Analyzer technology to narrow down protocol violations and debug the root causes."