As demand for ever-growing AI compute power continues to rise and manufacturing advanced nodes becomes more difficult, packaging is undergoing its golden era of development. Today's advanced accelerators often rely on TSMC's CoWoS modules, which are built on wafer cuts measuring no more than 120 × 150 mm in size. In response to the need for more space, TSMC has unveiled plans for CoPoS, or "Chips on Panel on Substrate," which could expand substrate dimensions to 310 × 310 mm and beyond. By shifting from round wafers to rectangular panels, CoPoS offers more than five times the usable area. This extra surface makes it possible to integrate additional high-bandwidth memory stacks, multiple I/O chiplets and compute dies in a single package. It also brings panel-level packaging (PLP) to the fore. Unlike wafer-level packaging (WLP), PLP assembles components on large, rectangular panels, delivering higher throughput and lower cost per unit. Systems with PLP will be actually viable for production runs and allow faster iterations over WLP.

TSMC will establish a CoPoS pilot line in 2026 at its Visionchip subsidiary. In 2027, the pilot facility will focus on refining the process, to meet partner requirements by the end of the year. Mass production is projected to begin between the end of 2028 and early 2029 at TSMC's Chiayi AP7 campus. That site, chosen for its modern infrastructure and ample space, is also slated to host production of multi-chip modules and System-on-Wafer technologies. NVIDIA is expected to be the launch partner for CoPoS. The company plans to leverage the larger panel area to accommodate up to 12 HBM4 chips alongside several GPU chiplets, offering significant performance gains for AI workloads. At the same time, AMD and Broadcom will continue using TSMC's CoWoS-L and CoWoS-R variants for their high-end products. Beyond simply increasing size, CoPoS and PLP may work in tandem with other emerging advances, such as glass substrates and silicon photonics. If development proceeds as planned, the first CoPoS-enabled devices could reach the market by late 2029.

Alphawave Semi, a global leader in high-speed connectivity and compute silicon for the world's technology infrastructure, announced the successful tape out of one of the industry's first UCIe IP subsystem on TSMC's N2 process, supporting 36G die-to-die data rates. The solution is fully integrated with TSMC's Chip-on-Wafer-on-Substrate (CoWoS ) advanced packaging technology, unlocking breakthrough bandwidth density and scalability for next-generation chiplet architectures.

This milestone builds on the recent release of the Alphawave Semi AI Platform, proving readiness to support the future of disaggregated SoCs and scale-up infrastructure for hyperscale AI and HPC workloads. With this tape-out, Alphawave Semi becomes one of the industry's first to enable UCIe connectivity on 2 nm nanosheet technology, marking a major step forward for the open chiplet ecosystem.

This year marks the 40th anniversary of the first commercially available field-programmable gate array (FPGA), introducing the idea of reprogrammable hardware. By creating "hardware as flexible as software," FPGA reprogrammable logic changed the face of semiconductor design. For the first time, developers could design a chip, and if specs or requirements changed mid-stream, or even after manufacturing, they could redefine its functionality to perform a different task. This flexibility enabled more rapid development of new chip designs, accelerating time to market for new products and providing an alternative to ASICs.

The impact on the market has been phenomenal. FPGAs launched a $10+ billion industry and over the past four decades we have shipped more than 3 billion FPGAs and adaptive SoCs (devices combining FPGA fabric with a system-on-chip and other processing engines) to more than 7,000 customers across diverse market segments. In fact, we've been the programmable logic market share leader for the past 25 consecutive years, and we believe we are well positioned for continued market leadership based on the strength of our product portfolio and roadmap.

This week at the Electronic Components Technology Conference (ECTC), Intel introduced EMIB-T, an important upgrade to its embedded multi-die interconnect bridge packaging. First showcased at the Intel Foundry Direct Connect 2025 event, EMIB-T incorporates through-silicon vias (TSVs) and high-power metal-insulator-metal capacitors into the existing EMIB structure. According to Dr. Rahul Manepalli, Intel Fellow and vice president of Substrate Packaging Development, these changes allow a more reliable power supply and stronger communication between separate chiplets. Conventional EMIB designs have struggled with voltage drops because of their cantilevered power delivery paths. In contrast, EMIB-T routes power directly through TSVs from the package substrate to each chiplet connection. The integrated capacitors compensate for fast voltage fluctuations and preserve signal integrity.

This improvement will be critical for next-generation memory, such as HBM4 and HBM4e, where data rates of 32 Gb/s per pin or more are expected over a UCIe interface. Intel has confirmed that the first EMIB-T packages will match the current energy efficiency of around 0.25 picojoules per bit while offering higher interconnect density. The company plans to reduce the bump pitch below today's standard of 45 micrometers. Beginning in 2026, Intel intends to produce EMIB-based packages measuring 120 by 120 millimeters, roughly eight times the size of a single reticle. These large substrates could integrate up to twelve stacks of high-bandwidth memory alongside multiple compute chiplets, all connected by more than twenty EMIB bridges. Looking further ahead, Intel expects to push package dimensions to 120 by 180 millimeters by 2028. Such designs could accommodate more than 24 memory stacks, eight compute chiplets, and 38 or more EMIB bridges. These developments closely mirror similar plans announced by TSMC for its CoWoS technology. In addition to EMIB-T, Intel also presented a redesigned heat spreader that reduces voids in the thermal interface material by approximately 25%, as well as a new thermal-compression bonding process that minimizes warping in large package substrates.

According to SemiAnalysis, AMD has planned its first-ever rack-scale GPU cluster for the second half of 2026, when it shows its first rack‑scale accelerator, the Instinct MI450X IF128. Built on what's expected to be a 3 nm‑class TSMC process and packaged with CoWoS‑L, each MI450X IF128 card will include at least 288 GB of HBM4 memory. That memory will sustain up to 18 TB/s of bandwidth, driving around 50 PetaFLOPS of FP4 compute while drawing between 1.6 and 2.0 kW of power. In our recent article, we outlined that AMD split the Instinct MI400 series into HPC-first MI430X and MI450X for AI. Now for AI-focused MI450X, the company created both an "IF64" backplane for simpler single‑rack installs and the full‑blown "IF128" for maximum density. The IF128 version links 128 GPUs over an Ethernet‑based Infinity Fabric network and uses UALink instead of PCIe to connect each GPU to three built‑in Pensando 800 GbE NICs. That design delivers about 1.8 TB/s of unidirectional bandwidth per GPU and a total of 2,304 TB/s across the rack.

With 128 GPUs each offering 50 PetaFLOPS of FP4 compute and 288 GB of HBM4 memory, the MI450X IF128 system delivers a combined 6,400 PetaFLOPS and 36.9 TB of high‑bandwidth memory, and MI450X IF64 provides about half of that. Since AI deployments require massive density of rack systems, AMD plans to possibly outnumber NVIDIA's upcoming system known as "Vera Rubin" VR200 NVL144 (144 compute dies, 72 GPUs), which tops out at 3,600 PetaFLOPS and 936 TB/s of memory bandwidth—about half of what AMD's IF128 approach promises. AMD will have a possibly more powerful system architecture than NVIDIA until the launch of VR300 "Ultra" NVL576, which has 144 GPUs, each carrying four compute dies, totaling 576 compute chiplets.

At this year's Technology Symposium, TSMC unveiled an engaging multi-year roadmap for its packaging technologies. TSMC's strategy splits into two main categories: Advanced Packaging and System-on-Wafer. Back in 2016, CoWoS-S debuted with four HBM stacks paired to N16 compute dies on a 1.5× reticle-limited interposer, which was an impressive feat at the time. Fast forward to 2025, and CoWoS-S now routinely supports eight HBM chips alongside N5 and N4 compute tiles within a 3.3× reticle budget. Its successor, CoWoS-R, increases interconnect bandwidth and brings N3-node compatibility without changing that reticle constraint. Looking toward 2027, TSMC will launch CoWoS-L. First up are large N3-node chiplets, followed by N2-node tiles, multiple I/O dies, and up to a dozen HBM3E or HBM4 stacks—all housed within a 5.5× reticle ceiling. It's hard to believe that eight HBM stacks once sounded ambitious—now they're just the starting point for next-gen AI accelerators inspired by AMD's Instinct MI450X and NVIDIA's Vera Rubin.

Integrated Fan-Out, or InFO, adds another dimension with flexible 3D assemblies. The original InFO bridge is already powering AMD's Instinct cards. Later this year, InFO-POP (package-on-package) and InFO-2.5D arrive, promising even denser chip stacking and unlocking new scaling potential on a single package, away from the 2D and 2.5D packaging we were used to, going into the third dimension. On the wafer scale, TSMC's System-on-Wafer lineup—SoW-P and SoW-X—has grown from specialized AI engines into a comprehensive roadmap mirroring logic-node progress. This year marks the first SoIC stacks from N3 to N4, with each tile up to 830 mm² and no hard limit on top-die size. That trajectory points to massive, ultra-dense packages, which is exactly what HPC and AI data centers will demand in the coming years.

Cadence today announced it is furthering its longstanding collaboration with TSMC to accelerate time to silicon for 3D-IC and advanced-node technologies through certified design flows, silicon-proven IP and ongoing technology collaboration. As a leading provider of IP for TSMC N2P, N5 and N3 process nodes, Cadence continues to deliver cutting-edge AI-driven design solutions to the TSMC ecosystem for multiple horizontal applications from chiplets and SoCs to advanced packaging and 3D-ICs. The deep collaboration encompasses certified tools and flows for TSMC's N2P and A16 technologies, paves the way for TSMC's A14 and further unlocks 3D-IC possibilities by extending support for TSMC 3DFabric design and packaging. In addition, Cadence and TSMC are extending tool certification for newly announced TSMC N3C technology based on available N3P design solutions.

Cadence is driving innovation in AI chip design with certified tools and optimized IP for TSMC's advanced N2P and A16 process technologies. Reinforcing its memory IP leadership, Cadence offers TSMC9000 pre-silicon-certified DDR5 12.8G IP for N2P. Cadence digital, custom/analog design and thermal analysis solutions are certified for TSMC N2P and A16 technologies. Combined with continued collaboration on AI-driven digital design solutions for N2P, including leveraging large language models (LLMs), these advancements play an important role in improving digital design flows for future process nodes.

TSMC today unveiled its next cutting-edge logic process technology, A14, at the Company's North America Technology Symposium. Representing a significant advancement from TSMC's industry-leading N2 process, A14 is designed to drive AI transformation forward by delivering faster computing and greater power efficiency. It is also expected to enhance smartphones by improving their on-board AI capabilities, making them even smarter. Planned to enter production in 2028, the current A14 development is progressing smoothly with yield performance ahead of schedule.

Compared with the N2 process, which is about to enter volume production later this year, A14 will offer up to 15% speed improvement at the same power, or up to 30% power reduction at the same speed, along with more than 20% increase in logic density. Leveraging the Company's experience in design-technology co-optimization for nanosheet transistor, TSMC is also evolving its TSMC NanoFlex standard cell architecture to NanoFlex Pro, enabling greater performance, power efficiency and design flexibility.

Global Unichip Corp. (GUC), the Advanced ASIC Leader, announced today that it has successfully taped-out the world's first HBM4 controller and PHY IP. This test chip was implemented using TSMC's cutting-edge N3P process technology and CoWoS -R advanced packaging technology.

The HBM4 IP supports data rates of up to 12 Gbps under all operating conditions. By leveraging a proprietary interposer layout, GUC has optimized signal integrity (SI) and power integrity (PI) to achieve these high speeds for all types of CoWoS technology. Comparing with HBM3, GUC's HBM4 PHY delivers 2.5x bandwidth while improving 1.5x power efficiency and 2x area efficiency. In line with previous GUC HBM, GLink, and UCIe IPs, this HBM4 IP integrates proteanTecs' interconnect monitoring solution to provide high visibility for testing and characterizing the PHY while improving in-field performance and reliability for end products.

Global Unichip Corp. (GUC), the Advanced ASIC Leader, today announced the successful launch of industry's first Universal Chiplet Interconnect Express (UCIe) PHY silicon, achieving a data rate of 32 Gbps per lane, the highest speed defined in the UCIe specification. The 32G UCIe IP, supporting UCIe 2.0, delivers an impressive bandwidth density of 10 Tbps per 1 mm of die edge (5 Tbps/mm full-duplex). This milestone was achieved using TSMC's advanced N3P process and CoWoS packaging technologies, targeting AI, high-performance computing (HPC), xPU, and networking applications.

In this test chip, several dies with North-South and East-West IP orientations are interconnected through CoWoS interposer. The silicon measurements show robust 32 Gbps operation with wide horizontal and vertical eye openings. GUC is working aggressively on the full-corner qualification, and the complete silicon report is expected to be available in the coming quarter.

Rumors previously suggested that NVIDIA might scale back its CoWoS orders from TSMC. However, according to a report from Economic Daily News, orders for TSMC's advanced packaging have instead seen a surge. NVIDIA's Blackwell architecture GPUs are in strong demand, leading the company to secure over 70% of TSMC's CoWoS-L advanced packaging capacity for 2025. Shipment volumes are projected to rise by more than 20% each quarter, with total annual shipments expected to surpass 2 million units.

Meanwhile, following the U.S. announcement of the Stargate project—which is anticipated to drive new AI server demand—NVIDIA is reportedly considering placing additional orders with TSMC. During TSMC's earnings call in January, Chairman C.C. Wei stated that the company is continuously expanding its advanced packaging capacity to keep pace with customer demand. According to reports, advanced packaging revenue accounted for roughly 8% in 2024 and is projected to exceed 10% in 2025.

According to a well-known industry analyst, Ming-Chi Kuo, NVIDIA has restructured its "Blackwell" architecture roadmap, emphasizing dual-die designs using CoWoS-L packaging technology. The new roadmap eliminates several single-die products that would have used CoWoS-S packaging, changing NVIDIA's manufacturing strategy. The 200 Series will exclusively use dual-die designs with CoWoS-L packaging, featuring the GB200 NVL72 and HGX B200 systems. Notably absent is the previously expected B200A single-die variant. The 300 Series will include both dual-die and single-die options, though NVIDIA and cloud providers are prioritizing the GB200 NVL72 dual-die system. Starting Q1 2025, NVIDIA will reduce H series production, which uses CoWoS-S packaging, while ramping up 200 Series production. This transition indicates significantly decreased demand for CoWoS-S capacity through 2025.

While B300 systems using single-die CoWoS-S are planned for 2026 mass production, the current focus remains on dual-die CoWoS-L products. From TSMC's perspective, the transition between Blackwell generations requires minimal process adjustments, as both use similar front-end-of-line processes with only back-end-of-line modifications needed. Supply chain partners heavily dependent on CoWoS-S production face significant impact, reflected in recent stock price corrections. However, NVIDIA maintains this change reflects product strategy evolution rather than market demand weakness. TSMC continues expanding CoWoS-R capacity while slowing CoWoS-S expansion, viewing AI and high-performance computing as sustained growth drivers despite these packaging technology transitions.

Alphawave Semi (LSE: AWE), a global leader in high-speed connectivity and compute silicon for the world's technology infrastructure, proudly introduces the industry's first 64 Gbps Universal Chiplet Interconnect Express (UCIe) Die-to-Die (D2D) IP Subsystem to deliver unprecedented chiplet interconnect data rates, setting a new standard for ultra-high-performance D2D connectivity solutions in the industry. The third generation, 64 Gbps IP Subsystem builds on the successes of the most recent Gen 2 36 Gbps IP subsystem and silicon-proven Gen 1 24 Gbps and is available in TSMC's 3 nm Technology for both Standard and Advanced packaging. The silicon proven success and tapeout milestones pave the way for Alphawave Semi's Gen 3 UCIe IP subsystem offering.

Alphawave Semi is set to revolutionize connectivity with its Gen 3 64 Gbps UCIe IP, delivering a bandwidth density of over 20 Tbps/mm, with ultra-low power and latency. This solution is highly configurable supporting multiple protocols, including AXI-4, AXI-S, CXS, CHI and CHI-C2C to address the growing demands for high-performance connectivity across disaggregated systems in High-Performance Computing (HPC), Data Centers, and Artificial Intelligence (AI) applications.

TSMC is reportedly negotiating with NVIDIA to manufacture advanced "Blackwell" GPUs in its Arizona facility. First reported by Reuters, this partnership could mark another major shift in AI chip production toward US soil. The discussion centers around TSMC's Fab 21 in Phoenix, Arizona, specializing in 4 nm and 5 nm chip production. NVIDIA's Blackwell GPUs utilize TSMC's 4NP process technology, making the Arizona facility a technically viable production site. However, the proposed arrangement faces several logistical challenges. A key issue is the absence of advanced packaging facilities in the United States. There is Amkor that planned to do advanced packaging, but it's only scheduled to begin packaging in 2027. TSMC's sophisticated CoWoS packaging technology is currently available only in Taiwan. This means that chips manufactured in Arizona would need to be shipped back to Taiwan for final assembly, potentially increasing production costs.

While alternative solutions exist, such as redesigning the chips to use Intel's packaging technology or focusing on gaming GPU production in Arizona, these options present their own complications. Intel's packaging methods would likely increase costs, and the current absence of graphics card manufacturing infrastructure in the US makes domestic gaming GPU production less practical. Both TSMC and NVIDIA have declined to comment on the ongoing negotiations, as this is confidential information unknown to the public. Interestingly, TSMC's Arizona facility has already attracted a few more US firms for domestic manufacturing, like Apple, rumored to manufacture its A16 Bionic chip and AMD with high-performance designs, likely either EPYC or Instinct MI chips.

According to The Information, NVIDIA's latest "Blackwell" processors are reportedly encountering significant thermal management issues in high-density server configurations, potentially affecting deployment timelines for major tech companies. The challenges emerge specifically in NVL72 GB200 racks housing 72 GB200 processors, which can consume up to 120 kilowatts of power per rack, weighting a "mere" 3,000 pounds (or about 1.5 tons). These thermal concerns have prompted NVIDIA to revisit and modify its server rack designs multiple times to prevent performance degradation and potential hardware damage. Hyperscalers like Google, Meta, and Microsoft, who rely heavily on NVIDIA GPUs for training their advanced language models, have allegedly expressed concerns about possible delays in their data center deployment schedules.

The thermal management issues follow earlier setbacks related to a design flaw in the Blackwell production process. The problem stemmed from the complex CoWoS-L packaging technology, which connects dual chiplets using RDL interposer and LSI bridges. Thermal expansion mismatches between various components led to warping issues, requiring modifications to the GPU's metal layers and bump structures. A company spokesperson characterized these modifications as part of the standard development process, noting that a new photomask resolved this issue. The Information states that mass production of the revised Blackwell GPUs began in late October, with shipments expected to commence in late January. However, these timelines are unconfirmed by NVIDIA, and some server makers like Dell confirmed that these GB200 NVL72 liquid-cooled systems are shipping now, not in January, with CoreWave GPU cloud provider as a customer. The original report could be using older information, as Dell is one of NVIDIA's most significant partners and among the first in the supply chain to gain access to new GPU batches.

At TSMC's earnings call on the 17th, the company revealed that its CoWoS (Chip-on-Wafer-on-Substrate) capacity will double each year in 2024 and 2025, but demand will continue to outpace supply. According to a report from Money DJ, the CoWoS expansion wave is expected to extend into 2026, promising strong growth for equipment suppliers for at least the next two to three years.

TSMC stated that advanced packaging currently accounts for approximately 7-9% of its revenue, and growth in this segment is expected to outpace the company's average over the next five years. While the gross margin for advanced packaging is slightly below the company average, it is steadily approaching it. Regarding CoWoS capacity, customer demand significantly exceeds TSMC's ability to supply, even with production capacity doubling year-on-year in both 2024 and 2025.

TSMC announced that its revenue for September 2024 reached NT$251.87 billion (US$7.80 billion), representing a 39% increase compared to the same month last year. The cumulative revenue for the first three quarters of 2024 climbed to NT$2,025.85 billion (US$62.72 billion), showing a 32% year-over-year growth. The company's third-quarter revenue amounted to NT$759.7 billion (US$23.52 billion), exceeding TSMC's own guidance of NT$706.6 billion to NT$731.5 billion (US$22.4 billion to US$23.2 billion). TSMC will report full third-quarter earnings on Oct. 17.

A report from Data Center Dynamics quotes sources saying that, due to increasing demand from NVIDIA and others, TSMC has been forced to change its CoWoS capacity expansion plan several times. In response, TSMC is building two more fabs, named P4 and P5, in Kaohsiung, Taiwan, raising the company's total number of facilities in the region to five. Four months ago, the company announced that it would build a third 2 nm fab at Nanzih Technology Industrial Park in Kaohsiung. The company's P1 fab, which started in August 2022, is expected to begin mass production next year, while P2 and P3 are still in the construction phase. TSMC's CoWoS monthly capacity is expected to reach more than 40,000 wafers by the end of 2024, 65,000 wafers in 2025, and at least 80,000 wafers in 2026.

After Apple, we just learned that AMD is the next company in line for US-based manufacturing in the TSMC Arizona facility. Industry analyst Tim Culpan reports that TSMC's Fab 21 in Arizona will soon be producing AMD's high-performance computing (HPC) processors, with tape out and manufacturing expected to commence on TSMC's 5 nm node next year. This move comes after previously reported Apple's A16 SoC production, which is already in progress at the facility and could see shipments before the end of this year, significantly ahead of the initially projected early 2025 schedule. The production of AMD's HPC chips in Arizona marks a crucial step towards establishing an AI-hardware supply chain operating entirely on American soil, which is expected to further expand with Intel Foundry and Samsung Texas facility.

Making HPC processors domestically serves as a significant milestone in reducing dependence on overseas semiconductor manufacturing and strengthening the US's position in the global chip industry. Adding to the momentum, TSMC and Amkor recently announced a collaboration on advanced packaging technologies, including Integrated Fan-Out (InFO) and Chip-on-Wafer-on-Substrate (CoWoS), which are vital for high-performance AI chips. However, as Amkor facilities are yet to be built, these chips are going to be shipped back to Taiwan for packaging before being integrated into the final product. Once the Amkor facility is up and running, Arizona will become the birthplace of fully manufactured and packaged silicon chips.

Amkor Technology, Inc. and TSMC announced today that the two companies have signed a memorandum of understanding to collaborate and bring advanced packaging and test capabilities to Arizona, further expanding the region's semiconductor ecosystem.

Amkor and TSMC have been closely collaborating to deliver high volume, leading-edge technologies for advanced packaging and testing of semiconductors to support critical markets such as high-performance computing and communications. Under the agreement, TSMC will contract turnkey advanced packaging and test services from Amkor in their planned facility in Peoria, Arizona. TSMC will leverage these services to support its customers, particularly those using TSMC's advanced wafer fabrication facilities in Phoenix. The close collaboration and proximity of TSMC's front-end fab and Amkor's back-end facility will accelerate overall product cycle times.

Synopsys, Inc. today announced its continued, close collaboration with TSMC to deliver advanced EDA and IP solutions on TSMC's most advanced process and 3DFabric technologies to accelerate innovation for AI and multi-die designs. The relentless computational demands in AI applications require semiconductor technologies to keep pace. From an industry leading AI-driven EDA suite, powered by Synopsys.ai for enhanced productivity and silicon results to complete solutions that facilitate the migration to 2.5/3D multi-die architectures, Synopsys and TSMC have worked closely for decades to pave the path for the future of billion to trillion-transistor AI chip designs.

"TSMC is excited to collaborate with Synopsys to develop pioneering EDA and IP solutions tailored for the rigorous compute demands of AI designs on TSMC advanced process and 3DFabric technologies," said Dan Kochpatcharin, head of the Ecosystem and Alliance Management Division at TSMC. "The results of our latest collaboration across Synopsys' AI-driven EDA suite and silicon-proven IP have helped our mutual customers significantly enhance their productivity and deliver remarkable performance, power, and area results for advanced AI chip designs.

During the Semicon Taiwan 2024 summit event, TSMC VP of Advanced Packaging Technology, Jun He, spoke about the importance of merging AI chip memory and logic chips using 3D IC technology. He predicted that by 2030 the worldwide semiconductor industry would hit the $1 trillion milestone with HPC and AI leading 40 percent of the market share. In 2027, TSMC will introduce the 2.5D CoWoS technology that includes eight A16 process chipsets and 12 HBM4. AI processors that use this technology will not only be much cheaper to produce but will also provide engineers with a greater level of convenience. Engineers will have the option to write new codes into them instead. Manufacturers are cutting the SoC and HBM architectural conversion and mass production costs down to nearly one-fourth.

Nevertheless, the increasing production capacities of 3D IC technology remain the main challenge, as the size of chips and the complexity of manufacturing are decisive factors. However, the higher the size of the chips, the more chiplets are added, and thus the performance is improved, but this now makes the process even more complicated and is associated with more risks of misalignment, breakage, and extraction failure.

Despite recent rumors speculating on NVIDIA's supposed cancellation of the B100 in favor of the B200A, TrendForce reports that NVIDIA is still on track to launch both the B100 and B200 in the 2H24 as it aims to target CSP customers. Additionally, a scaled-down B200A is planned for other enterprise clients, focusing on edge AI applications.

TrendForce reports that NVIDIA will prioritize the B100 and B200 for CSP customers with higher demand due to the tight production capacity of CoWoS-L. Shipments are expected to commence after 3Q24. In light of yield and mass production challenges with CoWoS-L, NVIDIA is also planning the B200A for other enterprise clients, utilizing CoWoS-S packaging technology.

Alphawave Semi, a global leader in high-speed connectivity and compute silicon for the world's technology infrastructure, has launched the industry's first 3 nm successful silicon bring-up of Universal Chiplet Interconnect Express (UCIe) Die-to-Die (D2D) IP with TSMC's Chip-on-Wafer-on-Substrate (CoWoS) advanced packaging technology.

The complete PHY and Controller subsystem was developed in collaboration with TSMC and targets applications such as hyperscaler, high-performance computing (HPC) and artificial intelligence (AI).

Taiwanese semiconductor giant TSMC is reportedly planning to increase its wafer prices by up to 10% in 2025, according to a Morgan Stanley note cited by investor Eric Jhonsa. The move comes as demand for cutting-edge processors in smartphones, PCs, AI accelerators, and HPC continues to surge. Industry insiders reveal that TSMC's state-of-the-art 4 nm and 5 nm nodes, used for AI and HPC customers such as AMD, NVIDIA, and Intel, could see up to 10% price hikes. This increase would push the cost of 4 nm-class wafers from $18,000 to approximately $20,000, representing a significant 25% rise since early 2021 for some clients and an 11% rise from the last price hike. Talks about price hikes with major smartphone manufacturers like Apple have proven challenging, but there are indications that modest price increases are being accepted across the industry. Morgan Stanley analysts project a 4% average selling price increase for 3 nm wafers in 2025, which are currently priced at $20,000 or more per wafer.

Mature nodes like 16 nm are unlikely to see price increases due to sufficient capacity. However, TSMC is signaling potential shortages in leading-edge capacity to encourage customers to secure their allocations. Adding to the industry's challenges, advanced chip-on-wafer-on-substrate (CoWoS) packaging prices are expected to rise by 20% over the next two years, following previous increases in 2022 and 2023. TSMC aims to boost its gross margin to 53-54% by 2025, anticipating that customers will absorb these additional costs. The impact of these price hikes on end-user products remains uncertain. Competing foundries like Intel and Samsung may seize this opportunity to offer more competitive pricing, potentially prompting some chip designers to consider alternative manufacturing options. Additionally, TSMC's customers could reportedly be unable to secure their capacity allocation without "appreciating TSMC's value."

TrendForce reports that NVIDIA's Hopper H100 began to see a reduction in shortages in 1Q24. The new H200 from the same platform is expected to gradually ramp in Q2, with the Blackwell platform entering the market in Q3 and expanding to data center customers in Q4. However, this year will still primarily focus on the Hopper platform, which includes the H100 and H200 product lines. The Blackwell platform—based on how far supply chain integration has progressed—is expected to start ramping up in Q4, accounting for less than 10% of the total high-end GPU market.

The die size of Blackwell platform chips like the B100 is twice that of the H100. As Blackwell becomes mainstream in 2025, the total capacity of TSMC's CoWoS is projected to grow by 150% in 2024 and by over 70% in 2025, with NVIDIA's demand occupying nearly half of this capacity. For HBM, the NVIDIA GPU platform's evolution sees the H100 primarily using 80 GB of HBM3, while the 2025 B200 will feature 288 GB of HBM3e—a 3-4 fold increase in capacity per chip. The three major manufacturers' expansion plans indicate that HBM production volume will likely double by 2025.