Today, the Open Compute Project Foundation (OCP), the nonprofit organization bringing hyperscale innovations to all, and JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, announce the availability of new Chiplet Design Kits for use with today's EDA tools covering Assembly, Substrate, Material and Test developed in collaboration within the OCP Open Chiplet Economy Project. Leveraging the alliance between OCP and JEDEC, these design kits are now part of the Global Worldwide Standard JEDEC JEP30: Part Model Guidelines.

The release of the Assembly, Substrate, Material, and Test Design Kits build on earlier joint efforts between the OCP and JEDEC integrating OCP Chiplet Data Extensible Markup Language (CDXML) specification into JEDEC JEP30: Part Model Guidelines, enabling Chiplet builders to provide electronically a standardized Chiplet part description to their customers, paving the way for automating System-in-Package (SiP) design and build using Chiplets.

Broadcom Inc. today announced the availability of its 3.5D eXtreme Dimension System in Package (XDSiP) platform technology, enabling consumer AI customers to develop next-generation custom accelerators (XPUs). The 3.5D XDSiP integrates more than 6000 mm² of silicon and up to 12 high bandwidth memory (HBM) stacks in one packaged device to enable high-efficiency, low-power computing for AI at scale. Broadcom has achieved a significant milestone by developing and launching the industry's first Face-to-Face (F2F) 3.5D XPU.

The immense computational power required for training generative AI models relies on massive clusters of 100,000 growing to 1 million XPUs. These XPUs demand increasingly sophisticated integration of compute, memory, and I/O capabilities to achieve the necessary performance while minimizing power consumption and cost. Traditional methods like Moore's Law and process scaling are struggling to keep up with these demands. Therefore, advanced system-in-package (SiP) integration is becoming crucial for next-generation XPUs. Over the past decade, 2.5D integration, which involves integrating multiple chiplets up to 2500 mm² of silicon and HBM modules up to 8 HBMs on an interposer, has proven valuable for XPU development. However, as new and increasingly complex LLMs are introduced, their training necessitates 3D silicon stacking for better size, power, and cost. Consequently, 3.5D integration, which combines 3D silicon stacking with 2.5D packaging, is poised to become the technology of choice for next-generation XPUs in the coming decade.

Some of the first die-shots and annotations of the Intel Core Ultra 200V "Lunar Lake" processor surfaced on the web, thanks to die-shots by GeenWens and Kurnalsalts on Twitter. Be sure to check out our Lunar Lake Technical Deep-dive article to learn the basics of how Lunar Lake is different from "Meteor Lake." Both are disaggregated chiplet-based processors, but Lunar Lake remodels things a bit. All the logic engines of the processor—the CPU, the iGPU, and the NPU, are located in a centralized Compute tile that's built on the TSMC 3 nm process, while all the I/O controllers are spun out to the Platform Controller tile built on TSMC 6 nm, which sit on a Foveros base tile that acts as an interposer, facilitating high-density microscopic connections between the two tiles. The base tile sits on the fiberglass substrate, which also has stacked LPDDR5X memory for either 16 GB or 32 GB of on-package system memory.

The Kurnalsalts annotation provides a good lay of the land for the Compute tile. The most striking aspect of it is the CPU. "Lunar Lake" comes with a 4P+4E core hybrid CPU, but the two kinds of cores do not share a last-level cache or sit in a ringbus, unlike in case of the Compute tile of "Meteor Lake." The four "Lion Cove" P-cores each come with 2.5 MB of dedicated L2 caches, and share a 12 MB L3 cache. The four "Skymont" E-cores are not part of the ringbus connecting the four P-cores, rather they are physically separated, much like the low-power island E-cores on "Meteor Lake." The E-core cluster shares a 4 MB L2 cache among the four E-cores. This E-core cluster is directly connected to the switching fabric of the Compute tile.

Intel has begun sampling the test tools for their "Oak Stream" platform which will house the "Diamond Rapids" generation of processors sometime in late 2025 or early 2026. Previously rumored to continue using the "Birch Stream" platform LGA 7529 socket that will soon be shipping with the 288-core flavor of the "Sierra Forest" efficiency core Xeons as well as 120-core "Granite Rapids" performance core Xeons, "Diamond Rapids" appears to instead be moving up to a substantially larger LGA 9324 socket. This is Intel's next-next generation of Xeon from what is shipping today, following up on the next-gen Intel 18A based "Clearwater Forest" which was only just reported to be powering on earlier this month. Other than the codename there is almost nothing currently known about "Diamond Rapids" but the rumor mill is already fired up and mentioning things such as increased core counts, 16 DRAM channels (similar to what AMD is expected to introduce with EPYC "Venice") and PCI-E 6.0 support.

The LGA 9324 test interposer for use with Intel's Gen 5 VR Test Tool that appeared on their Design-in Tools storefront before the page went to a 404 error carried a price tag of $900 USD and stipulated that this was a pre-order with an expected shipment date in Q4 2024.

AMD reportedly plans to incorporate glass substrates into its high-performance system-in-packages (SiPs) sometimes between 2025 and 2026. Glass substrates offer several advantages over traditional organic substrates, including superior flatness, thermal properties, and mechanical strength. These characteristics make them well-suited for advanced SiPs containing multiple chiplets, especially in data center applications where performance and durability are critical. The adoption of glass substrates aligns with the industry's broader trend towards more complex chip designs. As leading-edge process technologies become increasingly expensive and yield gains diminish, manufacturers turn to multi-chiplet designs to improve performance. AMD's current EPYC server processors already incorporate up to 13 chiplets, while its Instinct AI accelerators feature 22 pieces of silicon. A more extreme testament is Intel's Ponte Vecchio, which utilized 63 tiles in a single package.

Glass substrates could enable AMD to create even more complex designs without relying on costly interposers, potentially reducing overall production expenses. This technology could further boost the performance of AI and HPC accelerators, which are a growing market and require constant innovation. The glass substrate market is heating up, with major players like Intel, Samsung, and LG Innotek also investing heavily in this technology. Market projections suggest explosive growth, from $23 million in 2024 to $4.2 billion by 2034. Last year, Intel committed to investing up to 1.3 trillion Won (almost one billion USD) to start applying glass substrates to its processors by 2028. Everything suggests that glass substrates are the future of chip design, and we await to see first high-volume production designs.

JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, today announced it is nearing completion of the next version of its highly anticipated High Bandwidth Memory (HBM) DRAM standard: HBM4. Designed as an evolutionary step beyond the currently published HBM3 standard, HBM4 aims to further enhance data processing rates while maintaining essential features such as higher bandwidth, lower power consumption, and increased capacity per die and/or stack. These advancements are vital for applications that require efficient handling of large datasets and complex calculations, including generative artificial intelligence (AI), high-performance computing, high-end graphics cards, and servers.

HBM4 is set to introduce a doubled channel count per stack compared to HBM3, with a larger physical footprint. To support device compatibility, the standard ensures that a single controller can work with both HBM3 and HBM4 if needed. Different configurations will require various interposers to accommodate the differing footprints. HBM4 will specify 24 Gb and 32 Gb layers, with options for supporting 4-high, 8-high, 12-high and 16-high TSV stacks. The committee has initial agreement on speeds bins up to 6.4 Gbps with discussion ongoing for higher frequencies.

Samsung Electronics, a world leader in advanced semiconductor technology, today announced that it will provide turnkey semiconductor solutions using the 2-nanometer (nm) foundry process and the advanced 2.5D packaging technology Interposer-Cube S (I-Cube S) to Preferred Networks, a leading Japanese AI company.

By leveraging Samsung's leading-edge foundry and advanced packaging products, Preferred Networks aims to develop powerful AI accelerators that meet the ever-growing demand for computing power driven by generative AI.

PanelSemi, a developer of ultra-thin flexible LED displays and semiconductor substrates, has partnered with NGK Insulators to create high-performance hybrid packaging solutions. Leveraging its tiled thin-film transistor (TFT) circuit fabrication technology, PanelSemi is developing a hybrid circuit board that combines fine wiring and functional circuits on polyimide film with a ceramic substrate. The company is expanding into high-performance circuit boards for semiconductor modules, targeting large-scale panel manufacturing for wireless communications and opto-electronic integration. The collaboration with NGK extends the application of ceramic substrates to higher power and thermal scenarios.

NGK aims to integrate PanelSemi's circuit fabrication technology with its own products, including the ultra-compact EnerCera lithium-ion rechargeable battery, ceramic substrates, and ceramic packages. PanelSemi's HyBrid Substrate (HBS) technology platform features ultra-fine line width and spacing achieved through Thin Film (TF) and Panel Level Packaging (PLP) processes. HBS enables high-density interconnection, functioning as both an interposer and package substrate in advanced packaging, with the top die directly bonded to the HBS.

During the European Technology Symposium 2024, TSMC has announced its readiness to manufacture next-generation HBM4 base dies using both 12 nm and 5 nm nodes. This significant development is expected to substantially improve the performance, power consumption, and logic density of HBM4 memory, catering to the demands of high-performance computing (HPC) and artificial intelligence (AI) applications. The shift from a traditional 1024-bit interface to an ultra-wide 2048-bit interface is a key aspect of the new HBM4 standard. This change will enable the integration of more logic and higher performance while reducing power consumption. TSMC's N12FFC+ and N5 processes will be used to produce these base dies, with the N12FFC+ process offering a cost-effective solution for achieving HBM4 performance and the N5 process providing even more logic and lower power consumption at HBM4 speeds.

The company is collaborating with major HBM memory partners, including Micron, Samsung, and SK Hynix, to integrate advanced nodes for HBM4 full-stack integration. TSMC's base die, fabricated using the N12FFC+ process, will be used to install HBM4 memory stacks on a silicon interposer alongside system-on-chips (SoCs). This setup will enable the creation of 12-Hi (48 GB) and 16-Hi (64 GB) stacks with per-stack bandwidth exceeding 2 TB/s. TSMC's collaboration with EDA partners like Cadence, Synopsys, and Ansys ensures the integrity of HBM4 channel signals, thermal accuracy, and electromagnetic interference (EMI) in the new HBM4 base dies. TSMC is also optimizing CoWoS-L and CoWoS-R for HBM4 integration, meaning that massive high-performance chips are already utilizing this technology and getting ready for volume manufacturing.

TSMC today unveiled its newest semiconductor process, advanced packaging, and 3D IC technologies for powering the next generation of AI innovations with silicon leadership at the Company's 2024 North America Technology Symposium. TSMC debuted the TSMC A16 technology, featuring leading nanosheet transistors with innovative backside power rail solution for production in 2026, bringing greatly improved logic density and performance. TSMC also introduced its System-on-Wafer (TSMC-SoW) technology, an innovative solution to bring revolutionary performance to the wafer level in addressing the future AI requirements for hyperscaler datacenters.

This year marks the 30th anniversary of TSMC's North America Technology Symposium, and more than 2,000 attended the event, growing from less than 100 attendees 30 years ago. The North America Technology Symposium in Santa Clara, California kicks off TSMC Technology Symposiums around the world in the coming months. The symposium also features an "Innovation Zone," designed to highlight the technology achievements of our emerging start-up customers.

According to the report from a journal called Fundamental Research, researchers from the Institute of Computing Technology at the Chinese Academy of Sciences have developed a 256-core multi-chiplet processor called Zhejiang Big Chip, with plans to scale up to 1,600 cores by utilizing an entire wafer. As transistor density gains slow, alternatives like multi-chiplet architectures become crucial for continued performance growth. The Zhejiang chip combines 16 chiplets, each holding 16 RISC-V cores, interconnected via network-on-chip. This design can theoretically expand to 100 chiplets and 1,600 cores on an advanced 2.5D packaging interposer. While multi-chiplet is common today, using the whole wafer for one system would match Cerebras' breakthrough approach. Built on 22 nm process technology, the researchers cite exascale supercomputing as an ideal application for massively parallel multi-chiplet architectures.

Careful software optimization is required to balance workloads across the system hierarchy. Integrating near-memory processing and 3D stacking could further optimize efficiency. The paper explores lithography and packaging limits, proposing hierarchical chiplet systems as a flexible path to future computing scale. While yield and cooling challenges need further work, the 256-core foundation demonstrates the potential of modular designs as an alternative to monolithic integration. China's focus mirrors multiple initiatives from American giants like AMD and Intel for data center CPUs. But national semiconductor ambitions add urgency to prove domestically designed solutions can rival foreign innovation. Although performance details are unclear, the rapid progress shows promise in mastering modular chip integration. Combined with improving domestic nodes like the 7 nm one from SMIC, China could easily create a viable Exascale system in-house.

This is likely our last Framework Laptop 16 Deep Dive before we start shipping, and those of you who ordered one can dive deep on your own. We began mass production of Mainboards last week, which we'll hold onto as we resolve the last few remaining open items to begin full system manufacturing. You may be thinking, do we really need a deep dive on connectors? The answer is a resounding "Yes!"—as connectors are surprisingly among the most complex and critical parts of building a product that is slim, durable, high performance, and easy to repair. Connectors are the electrical and mechanical interfaces between modules in the system.

They are what actually makes the product modular! Each connector needs to be easy to engage, hard to accidentally disengage during vibration or drop, robust across repeated re-connections, thin enough to fit within a tiny space, electrically sound from a signal integrity and power perspective, readily manufacturable, and cheap. Our most complicated connectors are made up of dozens of tiny formed metal parts in plastic or metal shells. Given the complexity, our preference is always to find well-proven off-the-shelf connectors. However, occasionally we run into unique interconnect scenarios that don't match anything out there. In these instances, we're forced to customize our own solutions. With Framework Laptop 16, we developed two of these to enable our new module ecosystems.

Zero ASIC, a semiconductor startup, came out of stealth today to announce early access to its one-of-a-kind ChipMaker platform, demonstrating a number of world firsts:

• 3D chiplet composability enabling billions of new silicon products
• Fully automated no-code chiplet-based chip design
• Zero install interactive RTL-based chip emulation
• Roadmap to 100X reduction in chip development costs

"Custom Application Specific Integrated Circuits (ASICs) offer 10-100X cost and energy advantage over commercial off the shelf (COTS) devices, but the enormous development cost makes ASICs non-viable for most applications," said Andreas Olofsson, CEO and founder of Zero ASIC. "To build the next wave of world changing silicon devices, we need to reduce the barrier to ASICs by orders of magnitude. Our mission at Zero ASIC is to make ordering an ASIC as easy as ordering catalog parts from an electronics distributor."

Winbond Electronics Corporation, a leading global supplier of semiconductor memory solutions, has unveiled a powerful enabling technology for affordable Edge AI computing in mainstream use cases. The Company's new customized ultra-bandwidth elements (CUBE) enable memory technology to be optimized for seamless performance running generative AI on hybrid edge/cloud applications.

CUBE enhances the performance of front-end 3D structures such as chip on wafer (CoW) and wafer on wafer (WoW), as well as back-end 2.5D/3D chip on Si-interposer on substrate and fan-out solutions. Designed to meet the growing demands of edge AI computing devices, it is compatible with memory density from 256 Mb to 8 Gb with a single die, and it can also be 3D stacked to enhance bandwidth while reducing data transfer power consumption.

Synopsys, Inc. today announced it is extending its collaboration with TSMC to advance multi-die system designs with a comprehensive solution supporting the latest 3Dblox 2.0 standard and TSMC's 3DFabric technologies. The Synopsys Multi-Die System solution includes 3DIC Compiler, a unified exploration-to-signoff platform that delivers the highest levels of design efficiency for capacity and performance. In addition, Synopsys has achieved first-pass silicon success of its Universal Chiplet Interconnect Express (UCIe) IP on TSMC's leading N3E process for seamless die-to-die connectivity.

"TSMC has been working closely with Synopsys to deliver differentiated solutions that address designers' most complex challenges from early architecture to manufacturing," said Dan Kochpatcharin, head of the Design Infrastructure Management Division at TSMC. "Our long history of collaboration with Synopsys benefits our mutual customers with optimized solutions for performance and power efficiency to help them address multi-die system design requirements for high-performance computing, data center, and automotive applications."

Intel recently updated its website to highlight interposers used for testing upcoming chips before their actual product integration. A specific webpage now showcases components used by various tools, notably the "Gen5 VR," which stands for CPU Voltage Regulator in this context. The highlight of the update reveals at least four yet-to-be-announced products: Battlemage (BMG), Arrow Lake (ARL), and Lunar Lake (LNL), slated for launch in 2024. Particularly interesting are the two Battlemage interposers: BGA2362-BMG-X2 and BGA2727-BMG-X3. This hints that a Battlemage GPU could have more pins than Intel's current top-tier GPU from the Alchemist series, known as DG2, which features 2660 pins (BGA2660-DG2-512EU).

This unveiling could indicate Intel's plans to introduce two GPUs in its new series or potentially two different package sizes. Manufacturers often use consistent package sizes for multiple GPUs, granting flexibility to interchange processors with similar specifications and presenting a feasible production strategy. Another notable mention is the Arrow Lake-HX, intended for premium desktop/laptop hybrids.. While there was some buzz about the ARL-HX series before, this update provides clear confirmation from Intel. Lastly, the reveal includes an interposer for the Lunar Lake-M series (LNL-M), which is expected to be Intel's most energy-efficient line. Drawing parallels from the Alder Lake series, such chips were designed for tablets with power consumption between 5 to 7 watts.

Teledyne LeCroy, the worldwide leader in protocol test and measurement solutions, is pleased to announce availability of the OakGate R350-G5-PowerPlus 3U Rackmount Appliance for PCI Express 5.0, with solid state drive (SSD) power and sideband test capabilities.

Data centers and Hyperscalers are measured on their power sustainability and power usage goals and require SSD vendors to test SSD performance during normal system shutdown, abnormal system shutdown, power surges, low and/or idle power states, and voltage fluctuations. SSD vendors would ideally like these test results to highlight competitive product differentiators, often citing lower active power consumption, better power efficiencies and/or reduced cooling efficiencies. SSD design and validation test engineers can now use the OakGate R350-G5-PowerPlus Rackmount Appliance to analyze voltage and current over time and under stress to determine SSD power utilization, efficiency, and consumption, and possibly find opportunities to improve SSD power consumption. Moreover, the R350-G5-PowerPlus operates without the use of 3rd-party power interposers, reducing cost and simplifying test setup.

The Intel Design tools webpage has this week once again provided an early preview of upcoming processors - following on from an LGA1851-MTL-S CPU interposer appearing on the site late last month - indicating that a Meteor Lake-S desktop CPU range was due at some point later in 2023. Intel's latest webpage entry features the "BGA2114-ARL-HX Interposer for the Gen 5 VR Test Tool" with an SKU code that reads: "Q6B2114ARLHX."

The BGA 2114 design points to a mobile processor platform, and industry analysts are fairly certain that Intel is preparing next generation high-end laptop CPUs in the form of its rumored Arrow Lake-HX lineup. This range is set to succeed the 13th generation Core-HX Raptor Lake family of mobile processors. The new BGA package looks to be slightly larger than the closest predecessor, possibly accommodating Intel's new "disaggregated" tile-based (tile is their term for chiplet) internal layout.