Intel's first three generations of client processors implementing hybrid CPU cores, namely "Alder Lake," "Raptor Lake," and "Meteor Lake," have them arranged along a ringbus, sharing an L3 cache. This usually sees the larger P-cores to one region of the die, and the E-core clusters to the other region. From the perspective of the bidirectional ringbus, the ring-stops would follow the order: one half of the P-cores, one half of the E-core clusters, iGPU, the other half of E-cores, the other half of the P-cores, and the Uncore, as shown in the "Raptor Lake" die-shot, below. Intel plans to rearrange the P-cores and E-core clusters in "Arrow Lake-S."

With "Arrow Lake," Intel plans to disperse the E-core clusters between the P-cores. This would see a P-core followed by an E-core cluster, followed by two P-cores, and then another E-core cluster, then a lone P-core, and a repeat of this pattern. Kepler_L2 illustrated what "Raptor Lake" would have looked like, had Intel applied this arrangement on it. Dispersing the E-core clusters among the P-cores has two possible advantages. For one, the average latency between a P-core ring-stop and an E-core cluster ring-stop would reduce; and secondly, there will also be certain thermal advantages, particularly when gaming, as it reduces the concentration of heat in a region of the die.

Intel today launched its 13th Gen Core "Raptor Lake" desktop processors, and companion 700-series motherboard chipset. These processors are built in the same LGA1700 package as the previous generation "Alder Lake," and are backwards-compatible with 600-series chipset motherboards through a BIOS update. Likewise, 700-series chipset motherboards support older "Alder Lake" processors. With the new 13th Gen Core, Intel is broadly promising an up to 15% uplift in single-threaded performance, which has a bigger bearing on gaming performance; and an up to 41% multi-threaded performance uplift; over the previous-generation, when comparing the top Core i9-13900K with its predecessor, the i9-12900K. Intel also claims to have outclassed the AMD Ryzen 9 5950X in multi-threaded performance, and the Ryzen 7 5800X3D in gaming performance.

Intel's performance claims are backed by some impressive hardware changes despite the company sticking with the same Intel 7 (10 nm Enhanced SuperFin) foundry node as "Alder Lake." To begin with, the single-thread performance uplift comes from the new "Raptor Cove" performance-core, which promises an IPC uplift over the previous-generation "Golden Cove," comes with more dedicated L2 cache of 2 MB per core (compared to 1.25 MB per core in the previous-generation); and significantly higher clock-speeds, going all the way up to 5.80 GHz. "Raptor Lake" has up to 8 P-cores, but the company has put in a lot of work in improving the contribution of E-cores to the processor's overall multi-threaded performance uplift. This is achieved by doubling the E-core count to 16. These are the same "Gracemont" E-cores as previous-generation, but Intel has doubled the L2 cache that's shared in a 4-core Gracemont cluster, from 2 MB per cluster to 4 MB. There are upgrades to even the hardware prefetchers of these cores.

AMD's "Zen 3" CCD, or compute complex die, the physical building-block of both its client- and enterprise processors, possibly has a core count limitation owing to the way the various on-die bandwidth-heavy components are interconnected, says an AnandTech report. This cites what is possibly the first insights AMD provided on the CCD's switching fabric, which confirms the presence of a Ring Bus topology. More specifically, the "Zen 3" CCD uses a bi-directional Ring Bus to connect the eight CPU cores with the 32 MB of shared L3 cache, and other key components of the CCD, such as the IFOP interface that lets the CCD talk to the I/O die (IOD).

Imagine a literal bus driving around a city block, picking up and dropping off people between four buildings. The "bus" here resembles a strobe, the buildings resemble components (cores, uncore, etc.,) while the the bus-stops are ring-stops. Each component has its ring-stops. To disable components (eg: in product-stack segmentation), SKU designers simply disable ring-stops, making the component inaccessible. A bi-directional Ring Bus would see two "vehicles" driving in opposite directions around the city block. The Ring Bus topology comes with limitations of scale, mainly resulting from the latency added from too many ring-stops. This is precisely why coaxial ring-topology faded out in networking.

Intel today launches its 11th Gen Core "Tiger Lake" mobile processors that introduce several new technologies on the backs of new IP. As described in the Architecture Day, "Tiger Lake" is built on the 10 nm SuperFin process, and combines new "Willow Cove" CPU cores with the first commercial debut of the Xe Gen12 graphics architecture that Intel is betting big on, to make a stab at the consumer graphics and scalar compute markets. Join us in this live-blog.Update 16:00 UTC: GB (Gregory Bryant, EVP Client), leads the event from the comfort of his home.Update 16:04 UTC: Here it is, the "world's best processor for thin and light laptops. You'll notice that like most Intel U-segment chips, this is an MCM of the processor and PCH die. Intel bases its "world's best" claims on a per-segment basis.

Intel's "Xeon Scalable" lineup is designed to compete directly with AMD's Naples platform. Naples, a core-laden, high performance server platform that relies deeply on linking multiple core complexes together via AMD's own HyperTransport derived Infinity Fabric Interconnect has given intel some challenges in terms of how to structure its own high-core count family of devices. This has led to a new mesh-based interconnect technology from Intel.