Monday, July 1st 2024
Intel "Arrow Lake-S" to See a Rearrangement of P-cores and E-cores Along the Ringbus
Intel's first three generations of client processors implementing hybrid CPU cores, namely "Alder Lake," "Raptor Lake," and "Meteor Lake," have them arranged along a ringbus, sharing an L3 cache. This usually sees the larger P-cores to one region of the die, and the E-core clusters to the other region. From the perspective of the bidirectional ringbus, the ring-stops would follow the order: one half of the P-cores, one half of the E-core clusters, iGPU, the other half of E-cores, the other half of the P-cores, and the Uncore, as shown in the "Raptor Lake" die-shot, below. Intel plans to rearrange the P-cores and E-core clusters in "Arrow Lake-S."
With "Arrow Lake," Intel plans to disperse the E-core clusters between the P-cores. This would see a P-core followed by an E-core cluster, followed by two P-cores, and then another E-core cluster, then a lone P-core, and a repeat of this pattern. Kepler_L2 illustrated what "Raptor Lake" would have looked like, had Intel applied this arrangement on it. Dispersing the E-core clusters among the P-cores has two possible advantages. For one, the average latency between a P-core ring-stop and an E-core cluster ring-stop would reduce; and secondly, there will also be certain thermal advantages, particularly when gaming, as it reduces the concentration of heat in a region of the die.Every P-core would be no more than one ring-stop away from an E-core cluster, which should benefit migration of threads between the two core types. Thread Director prefers E-cores, and when a workload overwhelms an E-core, it is graduated to a P-core. This E-core to P-core migration should see reduced latencies under the new arrangement.
Source:
Kepler_L2 (Twitter)
With "Arrow Lake," Intel plans to disperse the E-core clusters between the P-cores. This would see a P-core followed by an E-core cluster, followed by two P-cores, and then another E-core cluster, then a lone P-core, and a repeat of this pattern. Kepler_L2 illustrated what "Raptor Lake" would have looked like, had Intel applied this arrangement on it. Dispersing the E-core clusters among the P-cores has two possible advantages. For one, the average latency between a P-core ring-stop and an E-core cluster ring-stop would reduce; and secondly, there will also be certain thermal advantages, particularly when gaming, as it reduces the concentration of heat in a region of the die.Every P-core would be no more than one ring-stop away from an E-core cluster, which should benefit migration of threads between the two core types. Thread Director prefers E-cores, and when a workload overwhelms an E-core, it is graduated to a P-core. This E-core to P-core migration should see reduced latencies under the new arrangement.
100 Comments on Intel "Arrow Lake-S" to See a Rearrangement of P-cores and E-cores Along the Ringbus
Looks pretty promising.
Lower clocks, no hyperthreading, etc should help with performance per watt but I’m not holding my breath on absolute performance being higher than a 13900k.
The point is on the vast majority of segments Intel has a much more efficient CPU at iso power in both ST and MT workloads. It's really not even competitive. R5 vs i5, R7 vs i7 etc.
Take your 7600x, it consumes 100w in CBR23 according to the same tests. Is there any Intel CPU that isn't actually faster than your 7600x while consuming the same watts? The answer is, maybe an i3 or something. Everything else handily beats the 7600x - in both performance and efficiency.
We all see the same numbers and 99.9999% of us know Intel’s product are hugely inefficient. So don’t forgive Intel by ignoring their faults, wish for them to do better.
12900KS
13900K
So in answer to your question, yes.
Overall the 12-13th gen were massive improvements in IPC from the previous Skylake based systems, are still faster core for core against Zen, and didn't have the core count/process issues of Rocket Lake.
If you strictly care about out of the box efficiency then TPU has tested that too, here is a simulated T and non k intel chip. Nothing is nowhere near in efficiency.
Alderlake was a 40% jump in ST performance from cometlake within 15 months. It was also a huge uplift in MT performance, again during the same timespan. If you weren't impressed with that, I don't know man.
This is from almost a year ago. It's probably close to 80% of AMD users on TPU now. It will probably hit 90% by next year. We DIYers like to buy AMD because of the efficiency and I don't see AMD letting go of this advantage anytime soon. How you see the exact opposite of what we see is mind boggling.