Monday, July 1st 2024
Intel "Arrow Lake-S" to See a Rearrangement of P-cores and E-cores Along the Ringbus
Intel's first three generations of client processors implementing hybrid CPU cores, namely "Alder Lake," "Raptor Lake," and "Meteor Lake," have them arranged along a ringbus, sharing an L3 cache. This usually sees the larger P-cores to one region of the die, and the E-core clusters to the other region. From the perspective of the bidirectional ringbus, the ring-stops would follow the order: one half of the P-cores, one half of the E-core clusters, iGPU, the other half of E-cores, the other half of the P-cores, and the Uncore, as shown in the "Raptor Lake" die-shot, below. Intel plans to rearrange the P-cores and E-core clusters in "Arrow Lake-S."
With "Arrow Lake," Intel plans to disperse the E-core clusters between the P-cores. This would see a P-core followed by an E-core cluster, followed by two P-cores, and then another E-core cluster, then a lone P-core, and a repeat of this pattern. Kepler_L2 illustrated what "Raptor Lake" would have looked like, had Intel applied this arrangement on it. Dispersing the E-core clusters among the P-cores has two possible advantages. For one, the average latency between a P-core ring-stop and an E-core cluster ring-stop would reduce; and secondly, there will also be certain thermal advantages, particularly when gaming, as it reduces the concentration of heat in a region of the die.
Every P-core would be no more than one ring-stop away from an E-core cluster, which should benefit migration of threads between the two core types. Thread Director prefers E-cores, and when a workload overwhelms an E-core, it is graduated to a P-core. This E-core to P-core migration should see reduced latencies under the new arrangement.
Source:
Kepler_L2 (Twitter)
With "Arrow Lake," Intel plans to disperse the E-core clusters between the P-cores. This would see a P-core followed by an E-core cluster, followed by two P-cores, and then another E-core cluster, then a lone P-core, and a repeat of this pattern. Kepler_L2 illustrated what "Raptor Lake" would have looked like, had Intel applied this arrangement on it. Dispersing the E-core clusters among the P-cores has two possible advantages. For one, the average latency between a P-core ring-stop and an E-core cluster ring-stop would reduce; and secondly, there will also be certain thermal advantages, particularly when gaming, as it reduces the concentration of heat in a region of the die.
86 Comments on Intel "Arrow Lake-S" to See a Rearrangement of P-cores and E-cores Along the Ringbus
I actually now regret not going DDR5, as I think in some workloads its probably hindering the performance and its crazy that the improvement I am noticing would have been even higher. However I am not going to swap out the board and swap the RAM at this point, not rebuilding again.
I think the two most sensible things Intel can do on Arrow Lake is ditch HTT, its out dated and inefficient now, and also ship CPUs lower on the v/f curve.
My comment was about intel not having Ht on arrow lake, or did you not get that?
My current specs have nothing to do with my comment
I have a brain, so yes, I disabled HT. But I won't tell you what I found after trying this for 2 weeks... I'll let you put your money where your mouth is first. Please come back and share.
How i run my rig has nothing to do with Arrow lake or this thread.