Intel Labs recently opened the Intel Research Center for Integrated Photonics for Data Center Interconnects. The center's mission is to accelerate optical input/output (I/O) technology innovation in performance scaling and integration with a specific focus on photonics technology and devices, CMOS circuits and link architecture, and package integration and fiber coupling.

"At Intel Labs, we're strong believers that no one organization can successfully turn all the requisite innovations into research reality. By collaborating with some of the top scientific minds from across the United States, Intel is opening the doors for the advancement of integrated photonics for the next generation of compute interconnect. We look forward to working closely with these researchers to explore how we can overcome impending performance barriers," said James Jaussi, senior principal engineer and director of the PHY Research Lab in Intel Labs.

GLOBALFOUNDRIES (GF ), the global leader in feature-rich semiconductor manufacturing, today announced it is expanding its global manufacturing footprint with the construction of a new fab on its Singapore campus. In partnership with the Singapore Economic Development Board and with co-investments from committed customers, GF's more than US $4B (S$5B) investment will play an integral role in meeting the growing demand for the company's industry-leading manufacturing technologies and services to enable companies worldwide to develop and scale their business.

In a virtual groundbreaking ceremony, Singapore Minister for Transport and Minister-in-charge of Trade Relations S. Iswaran and Mubadala Investment Company Managing Director and Group CEO H.E. Khaldoon Khalifa Al Mubarak, were joined by: UAE Ambassador to Singapore H.E. Jamal Abdulla Al Suwaidi; Singapore Ambassador to the UAE H.E. Kamal R Vaswani; Singapore Economic Development Board Managing Director Chng Kai Fong; GF Board Chairman Ahmed Yahia Al Idrissi; along with GF executives including CEO Tom Caulfield; CFO David Reeder; SVP and Head of Global Operations KC Ang; SVP of Global Sales Juan Cordovez; VP of Human Resource for APAC and International Fabs Janice Lee; and VP of Technology Development in Singapore Dr. Soh Yun Siah.

GLOBALFOUNDRIES (GF ), the global leader in feature-rich semiconductor manufacturing, and GlobalWafers Co., Ltd. (GWC), one of the top silicon wafer manufacturers in the world, today announced an $800 million agreement to add 300 mm silicon-on-insulator (SOI) wafer manufacturing and expand existing 200 mm SOI wafer production at GWC's MEMC facility in O'Fallon, Missouri.

The silicon wafers produced by GWC are key input materials for semiconductors and an integral part of GF's supply chain. The wafers are used in GF's multi-billion dollar manufacturing facilities, or fabs, where they are used to manufacture the computer chips that are pervasive and vital to the global economy. Today's announcement expands GF's domestic silicon wafer supply from the United States.

Korean DRAM and NAND flash giant, SK Hynix, admitted that a rather big batch of its DRAM wafers is defective and in circulation. The size of this defective batch is rumored to be 240,000 wafers according to a Yonhap report, although the company downplays the scale of the problem citing its monthly production output of 1.8 million wafers.

The company said that it is working with its customers who received these wafers, for recall and replacement. "We're currently talking to a limited number of customers affected by this to address the issue. While it's too early to estimate the potential losses, we don't think they would be that significant as the defect is within the range of typical quality issue check." Besides this, the company is battling rumors surrounding the scale of defective DRAM wafers by the company, in circulation. "The scale of the potential losses mentioned in the rumor is absolutely not true and exaggerated," the company said, in a statement to The Register.

AMD in a filing with the U.S. Securities and Exchange Commission (SEC), revealed that its wafer supply agreement with GlobalFoundries has been amended. Under the new terms, AMD places orders for wafers from GlobalFoundries up to 2024, with purchase targets set for each year leading up to 2024. Beyond meeting these targets, AMD is free from all other exclusivity commitments. The agreement was previously amended in January 2019, setting annual purchase targets for 2019, 2020, and 2021, while beginning a de-coupling between AMD and GlobalFoundries. This enabled the company to source 7 nm (or smaller) chips, such as CCDs and GPUs, from other foundries, such as TSMC, while keeping GlobalFoundries exclusive for 12 nm (or larger) nodes.

The updated wafer supply agreement unlocks many possibilities for AMD. For starters, it can finally build a next-generation sIOD (server I/O die) on a more efficient node than GlobalFoundries 12LP, such as TSMC 7 nm. This transition to 7 nm will be needed as the next-gen "Genoa" EPYC processor could feature future I/O standards such as DDR5 memory and PCI-Express Gen 5, and the switching fabric for these could be too power-hungry on 12 nm. The "Zen 4" CPU core complex dies (CCDs) of "Genoa" are expected to be built on TSMC 5 nm.

NAND Flash demand continues to rise as strong sales of notebook (laptop) computers spur PC OEMs to place additional orders for client SSDs, according to TrendForce's latest investigations. Also, the supply-side inventory for NAND Flash memory has already fallen considerably due to the aggressive stock-up activities of some smartphone brands. With customers in the data center segment expected to ramp up procurement in 2Q21, NAND Flash suppliers have decided to scale back the supply of NAND Flash wafers. Compared with other product categories, wafers have a lower gross margin. As a result of these factors, the decline in contract prices of wafers has been easing over the past two months (i.e., from December of last year to January of this year).

Semiconductor foundries across the board are preparing to raise price quotes of their 8-inch wafers from 2021. A DigiTimes report sheds light on various foundry companies, including UMC (United Microelectronics), Global Foundries, and Vanguard International Semiconductor (VIS) have raised their 8-inch foundry quotes by 10-15% in Q4-2020, with the quotes set to rise by another 20-40% in 2021. Foundries don't tend to use flat pricing, and instead rely on quotes specific to the size and design requirements of an order (by a fabless chip designer).

The foundry industry operates broadly on silicon fabrication nodes and wafer sizes. This article by Telescope Magazine provides insights into the typical use-cases for each wafer size. Although pertaining strictly to pricing of 8-inch (200 mm) wafers, an impending price-rise across the semiconductor industry can be extrapolated on the basis on significant labor cost increases. TSMC is planning to implement a 20% pay hike for its personnel in 2021.

TSMC, the world's leading semiconductor manufacturing company, is rumored to start production of its 6th generation Chip-on-Wafer-on-Substrate (CoWoS) packaging technology. As the silicon scaling is getting ever so challenging, the manufacturers have to come up with a way to get as much performance as possible. That is where TSMC's CoWoS and other chiplet technologies come. They allow designers to integrate many integrated circuits on a single package, making for a cheaper overall product compared to if the product used one big die. So what is so special about 6th generation CoWoS technology from TSMC, you might wonder. The new generation is said to enable a massive 12 stacks of HBM memory on a package. You are reading that right. Imagine if each stack would be an HBM2E variant with 16 GB capacity that would be 192 GB of memory on the package present. Of course, that would be a very expensive chip to manufacture, however, it is just a showcase of what the technology could achieve.

Update 16:44 UTC—TheEnglish DigiTimes report indicates that this technology is expected to see mass production in 2023.

TSMC has had quite a good time recently. They are having all of their capacity fully booked and the development of new semiconductor nodes is going good. Today, thanks to the report of DigiTimes, we have found out that TSMC is ramping up the production lines to prepare for 3 nm high-volume manufacturing. The 3 nm node is expected to enter HVM in 2022, which is not that far away. In the beginning, the new node is going to be manufactured on 55.000 wafers of 300 mm size, and it is expected to reach as much as 100.000 wafers per month output by 2023. With the accelerated purchase of EUV machines, TSMC already has all of the equipment required for the manufacturing of the latest node. We are waiting to see more details on the 3 nm node as we approach its official release.

TSMC, one of the biggest silicon manufacturers in the world, usually doesn't disclose company pricing of the silicon it manufactures and only shares that with its customers. It appears that RetiredEngineer (@chiakokhua on Twitter) got a hold of the pricing of TSMCs wafers on every manufacturing node starting from 90 nm down to 5 nm. That includes a wide portfolio of 65, 40, 28, 20, 16/12, 10, and 7 nm nodes as well. The table shown below includes information dating to April 2020, so it is possible that some things are now different and they surely are. There are a few quite interesting notes from the image, namely the price increase as the node shrinks.

From 90 nm to 20 nm, the price of the wafer didn't increase as much, however, starting from 16/12 nm node(s), TSMC has seen costs per wafer, and other costs increase exponentially. For example, just compare the 10 nm wafer price of $5992 with the price of a 5 nm wafer which costs an amazing $16988. This is more than a 180% price increase in just three years, however, the cost per transistor is down as you get around 229% higher density in that period, making TSMC actually in line with Moore's Law. That is comparing Transistor density (MTr / mm²) of52.51 million transistors for the 10 nm node and 173 million transistors per mm² of the 5 nm node .

Rambus Inc. (NASDAQ: RMBS), a premier silicon IP and chip provider making data faster and safer, today announced it has achieved a record 4 Gbps performance with the Rambus HBM2E memory interface solution consisting of a fully-integrated PHY and controller. Paired with the industry's fastest HBM2E DRAM from SK hynix operating at 3.6 Gbps, the solution can deliver 460 GB/s of bandwidth from a single HBM2E device. This performance meets the terabyte-scale bandwidth needs of accelerators targeting the most demanding AI/ML training and high-performance computing (HPC) applications.

"With this achievement by Rambus, designers of AI and HPC systems can now implement systems using the world's fastest HBM2E DRAM running at 3.6 Gbps from SK hynix," said Uksong Kang, vice president of product planning at SK hynix. "In July, we announced full-scale mass-production of HBM2E for state-of-the-art computing applications demanding the highest bandwidth available."

TSMC had been working super hard in the past few years and has been investing in lots of new technologies to drive the innovation forward. At TSMC's Technology Symposium held this week was, the company has presented various things like the update on its 12 nm node, as well as future plans for node development. One of the most interesting announcements made this week was TSMC's state and ownership of Extreme Ultra-Violet (EUV) machines. ASML, the maker of these EUV machines used to etch the pattern on silicon, has been the supplier of the Taiwanese company. TSMC has announced that they own an amazing 50% of all EUV machine installations.

What is more important is the capacity that the company achieves with it. It is reported that TSMC achieves 60% of all EUV wafer capacity in the world, which is a massive achievement of what TSMC can do with the equipment. The company right now has only two nodes on EUV in high-volume manufacturing, the 7 nm+ node and 5 nm node (which is going HVM in Q4), however, that is more than any of its competitors. All of the future nodes are to be manufactured using the EUV machines and the smaller nodes require it. As far as the competitors go, only Samsung is currently making EUV silicon on the 7 nm LPP node. Intel is yet to release some products on a 7 nm node of its own, which is the first EUV node from the company.

Wafer-scale design is getting popular it seems. Starting from the wafer-scale engine presented by Cerebras last year, which caused quite the shakeup in the industry, it seems that this design approach might be more useful than anyone thought. During VLSI Symposium 2020, Shigeo Oshima, Chief Engineer at Kioxia, had a presentation about new developments in SSD designs and implementations. What was one of the highlights of the presentation was the information that Kioxia is working on, was a technology Kioxia is referring to as wafer-level SSD.

The NAND chips used in SSDs would no longer be cut from the wafer and packaged separately. Instead, the wafer itself would represent the SSD. This is a similar approach Cerebras used with its wafer-scale engine AI processor. What would be gains of this approach compared to traditional methods of cutting up NAND chips and packaging them separately you might wonder? Well, for starters you wouldn't need to cut the wafer, package individual memory chips, and build the SSD out of them. Those steps could be skipped and there would be some cost savings present. And imagine if you decide to do wafer stacking. You could build super scaling SSDs with immense performance capable of millions of IOPS. However, for now, this is only a concept and it is just in early development. There is no possibility to find it in a final product anytime soon.